Lines Matching defs:madr
1466 memregs->madr[j][0]),
1468 memregs->madr[j][1]));
1473 memregs->madr[j][2]),
1475 memregs->madr[j][3]));
1496 memregs->madr[j][0]),
1498 memregs->madr[j][1]));
1503 memregs->madr[j][2]),
1505 memregs->madr[j][3]));
1527 memregs->madr[j][0]),
1529 memregs->madr[j][1]));
1534 memregs->madr[j][2]),
1536 memregs->madr[j][3]));
2845 drmach_mem_read_madr(drmach_mem_t *mp, int bank, uint64_t *madr)
2849 /* get register address, read madr value */
2851 *madr = lddmcdecode(DRMACH_MC_ASI_ADDR(mp, bank));
2853 *madr = lddphysio(DRMACH_MC_ADDR(mp, bank));
2867 uint64_t madr, bank_offset;
2869 /* fetch mc's bank madr register value */
2870 drmach_mem_read_madr(mp, bank, &madr);
2871 if (madr & DRMACH_MC_VALID_MASK) {
2874 bank_offset = (DRMACH_MC_UM_TO_PA(madr) |
2875 DRMACH_MC_LM_TO_PA(madr)) - current_basepa;
2878 /* encode new base pa into madr */
2879 madr &= ~DRMACH_MC_UM_MASK;
2880 madr |= DRMACH_MC_PA_TO_UM(bankpa);
2881 madr &= ~DRMACH_MC_LM_MASK;
2882 madr |= DRMACH_MC_PA_TO_LM(bankpa);
2889 *p++ = madr;
6287 uint64_t madr;
6289 drmach_mem_read_madr(mp, bank, &madr);
6290 if (madr & DRMACH_MC_VALID_MASK) {
6497 uint64_t madr;
6500 drmach_mem_read_madr(mp, bank, &madr);
6502 if (!(madr & DRMACH_MC_VALID_MASK))
6505 uk = DRMACH_MC_UK(madr);
6551 uint64_t addr, madr;
6553 drmach_mem_read_madr(mp, bank, &madr);
6554 if (madr & DRMACH_MC_VALID_MASK) {
6555 addr = DRMACH_MC_UM_TO_PA(madr) |
6556 DRMACH_MC_LM_TO_PA(madr);
6588 uint64_t madr;
6590 drmach_mem_read_madr(mp, bank, &madr);
6591 if (madr & DRMACH_MC_VALID_MASK) {
6594 pa = DRMACH_MC_UM_TO_PA(madr);
6595 pa |= DRMACH_MC_LM_TO_PA(madr);
8763 uint64_t madr;
8785 drmach_mem_read_madr(mp, bank, &madr);
8786 if (madr & DRMACH_MC_VALID_MASK) {
8787 DRMACH_PR("%d.%d.%d.madr = 0x%lx\n",
8788 exp, mcnum, bank, madr);
8789 memregs->madr[mcnum][bank].hi =
8790 DRMACH_U64_TO_MCREGHI(madr);
8791 memregs->madr[mcnum][bank].lo =
8792 DRMACH_U64_TO_MCREGLO(madr);