Lines Matching defs:n
444 DB_DEBUG0(DB_INIT|DB_DONT_DISPLAY_DIP, NULL, "enter\n");
449 DB_DEBUG1(DB_INIT|DB_DONT_DISPLAY_DIP, NULL, "exit rc=%d\n", rc);
459 DB_DEBUG0(DB_FINI|DB_DONT_DISPLAY_DIP, NULL, "enter\n");
462 DB_DEBUG1(DB_FINI|DB_DONT_DISPLAY_DIP, NULL, "exit rc=%d\n", rc);
471 DB_DEBUG1(DB_INFO|DB_DONT_DISPLAY_DIP, NULL, "exit rc=%d\n", rc);
484 DB_DEBUG1(DB_GETINFO|DB_DONT_DISPLAY_DIP, dip, "enter:cmd=%d\n",
507 "exit: result=%x, rc=%d\n", *result, rc);
527 DB_DEBUG1(DB_ATTACH, dip, "enter: cmd=%d\n", cmd);
707 DB_DEBUG1(DB_ATTACH, dip, "exit: rc=%d\n", rc);
721 DB_DEBUG1(DB_DETACH, dip, "enter: cmd=%d\n", cmd);
760 DB_DEBUG1(DB_DETACH, dip, "exit: rc=%d\n", rc);
885 "db_orientation: pif secondary\n");
891 "db_orientation: pif primary\n");
930 DB_DEBUG0(DB_ATTACH, dip, "db_orientation: chip primary\n");
932 DB_DEBUG0(DB_ATTACH, dip, "db_orientation: chip secondary\n");
953 DB_DEBUG0(DB_ATTACH, dip, "db_enable_io: primary\n");
958 DB_DEBUG0(DB_ATTACH, dip, "db_enable_io: secondary\n");
979 "db_enable_io: latency %d, cache line size %d\n",
1013 "Failed to read reg property\n");
1032 "db_enable_io: setting up MEM0_TR_BASE\n");
1033 DB_DEBUG1(DB_ATTACH, dip, "BASE0 register = %x\n",
1043 "db_enable_io: MEM0_TR_BASE set value = %x\n",
1077 DB_DEBUG1(DB_ATTACH, dip, "db_enable_io: CSR value before: %x\n",
1088 DB_DEBUG1(DB_ATTACH, dip, "db_enable_io: CSR value after: %x\n",
1097 DB_DEBUG1(DB_ATTACH, dip, "db_enable_io: IO_CSR value before: %x\n",
1108 DB_DEBUG1(DB_ATTACH, dip, "db_enable_io: IO_CSR value after: %x\n",
1124 "db_enable_io: CHIP_CTRL0 value before: %x\n", regval);
1137 "db_enable_io: CHIP_CTRL0 value after: %x\n", regval);
1149 "db_enable_io: chip ctrl (0x%x) before\n", regval);
1157 "db_enable_io: chip ctrl (0x%x) after\n", regval);
1203 "DVMA Range is %lx,%lx\n", dvma_start, dvma_len);
1225 DB_DEBUG2(DB_DVMA, dbp->dip, "DVMA size register pair %lx, %lx\n",
1275 DB_DEBUG2(DB_DVMA, dbp->dip, "DVMA BARs set as %x, %x\n",
1731 DB_DEBUG0(DB_PCI_MAP, dip, "enter\n");
1766 DB_DEBUG3(DB_PCI_MAP, dip, "rdip=%lx, rnum=%d(%d)\n",
1800 "unmap rdip=%lx\n", rdip);
1875 DB_DEBUG0(DB_PCI_MAP, dip, "primary\n");
1880 "INDIRECT_CONF\n");
1902 "DIRECT_CONF\n");
1924 "secondary\n");
1929 "INDIRECT_CONF\n");
1951 "DIRECT_CONF\n");
1976 DB_DEBUG0(DB_PCI_MAP, dip, "PCI_ADDR_IO\n");
1981 DB_DEBUG0(DB_PCI_MAP, dip, "primary\n");
1997 "secondary\n");
2016 "PCI_ADDR unknown\n");
2029 "access mode type 0\n");
2038 "access mode type 1\n");
2040 DB_DEBUG4(DB_PCI_MAP, dip, "addrp<%x,%x,%x> = %lx\n",
2047 DB_DEBUG1(DB_PCI_MAP, dip, "DDI other %x\n",
2051 DB_DEBUG0(DB_PCI_MAP, dip, "exit\n");
2096 DB_DEBUG1(DB_CTLOPS, dip, "ctlop=%s\n", db_ctlop_name[ctlop]);
2098 DB_DEBUG1(DB_CTLOPS, dip, "ctlop=%d\n", ctlop);
2105 cmn_err(CE_CONT, "?PCI-device: %s@%s, %s#%d\n",
2153 DB_DEBUG1(DB_INTR_OPS, dip, "intr_op=%d\n", intr_op);
2192 DB_DEBUG3(DB_INTR_OPS, dip, "intr=%d, d=%d, is_intr=%d\n",
2205 uint_t n, slot, func;
2213 DDI_PROP_DONTPASS, "unit-address", &unit_addr, &n) !=
2219 if (n != 1 || *unit_addr == NULL || **unit_addr == 0) {
2233 (int **)&pci_rp, &n) != DDI_SUCCESS)
2255 uint_t n;
2325 "initializing device vend=%x, devid=%x\n",
2353 n = pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ);
2354 if (n != 0) {
2356 "cache-line-size", n);
2359 "\nChild Device Cache Size %x\n", dbp->cache_line_size);
2380 n = pci_config_get8(config_handle, PCI_CONF_LATENCY_TIMER);
2381 if (n != 0) {
2383 "latency-timer", n);
2386 "\nChild Device latency %x\n", latency_timer);
2470 "%s#%d: No memory to save state for child %s#%d\n",