Lines Matching defs:softsp
118 iommu_init(struct sbus_soft_state *softsp, caddr_t address)
138 softsp->iommu_ctrl_reg = REG_ADDR(address, OFF_IOMMU_CTRL_REG);
139 softsp->tsb_base_addr = REG_ADDR(address, OFF_TSB_BASE_ADDR);
140 softsp->iommu_flush_reg = REG_ADDR(address, OFF_IOMMU_FLUSH_REG);
141 softsp->iommu_tlb_tag = REG_ADDR(address, OFF_IOMMU_TLB_TAG);
142 softsp->iommu_tlb_data = REG_ADDR(address, OFF_IOMMU_TLB_DATA);
146 mutex_init(&softsp->dma_pool_lock, NULL, MUTEX_DEFAULT, NULL);
147 mutex_init(&softsp->intr_poll_list_lock, NULL, MUTEX_DEFAULT, NULL);
150 if ((softsp->iommu_tsb_cookie = iommu_tsb_alloc(softsp->upa_id)) ==
153 ddi_driver_name(softsp->dip),
154 ddi_get_instance(softsp->dip));
157 softsp->soft_tsb_base_addr =
158 iommu_tsb_cookie_to_va(softsp->iommu_tsb_cookie);
159 softsp->iommu_dvma_size =
160 iommu_tsb_cookie_to_size(softsp->iommu_tsb_cookie) <<
162 softsp->iommu_dvma_base = (ioaddr_t)
163 (0 - (ioaddr_t)softsp->iommu_dvma_size);
166 ddi_driver_name(softsp->dip), ddi_get_instance(softsp->dip));
171 softsp->dvma_arena = vmem_create(name,
172 (void *)(uintptr_t)softsp->iommu_dvma_base,
173 softsp->iommu_dvma_size, PAGESIZE, NULL, NULL, NULL,
177 softsp->dma_reserve = iommu_btop(softsp->iommu_dvma_size >> 1);
180 mutex_init(&softsp->iomemlock, NULL, MUTEX_DEFAULT, NULL);
181 softsp->iomem = (struct io_mem_list *)0;
193 (void) iommu_resume_init(softsp);
196 if (*softsp->tsb_base_addr !=
197 va_to_pa((caddr_t)softsp->soft_tsb_base_addr)) {
198 iommu_tsb_free(softsp->iommu_tsb_cookie);
202 softsp->sbus_io_lo_pfn = UINT32_MAX;
203 softsp->sbus_io_hi_pfn = 0;
204 for (i = 0; i < sysio_pd_getnrng(softsp->dip); i++) {
209 rangep = sysio_pd_getrng(softsp->dip, i);
216 softsp->sbus_io_lo_pfn = (lopfn < softsp->sbus_io_lo_pfn) ?
217 lopfn : softsp->sbus_io_lo_pfn;
219 softsp->sbus_io_hi_pfn = (hipfn > softsp->sbus_io_hi_pfn) ?
220 hipfn : softsp->sbus_io_hi_pfn;
225 (void *)softsp->iommu_ctrl_reg, (void *)softsp->tsb_base_addr,
226 (void *)softsp->iommu_flush_reg,
227 (void *)softsp->soft_tsb_base_addr));
238 iommu_uninit(struct sbus_soft_state *softsp)
240 vmem_destroy(softsp->dvma_arena);
243 *softsp->iommu_ctrl_reg &=
246 iommu_tsb_free(softsp->iommu_tsb_cookie);
256 iommu_resume_init(struct sbus_soft_state *softsp)
265 *softsp->tsb_base_addr = va_to_pa((caddr_t)softsp->soft_tsb_base_addr);
275 tsb_bytes = iommu_tsb_cookie_to_size(softsp->iommu_tsb_cookie);
286 *softsp->iommu_ctrl_reg = (uint64_t)(tsb_size << TSB_SIZE_SHIFT
293 iommu_tlb_flush(struct sbus_soft_state *softsp, ioaddr_t addr, pgcnt_t npages)
301 *softsp->iommu_flush_reg = (uint64_t)addr;
302 tmpreg = *softsp->sbus_ctrl_reg;
307 for (i = 0, vaddr_reg = softsp->iommu_tlb_tag,
308 valid_bit_reg = softsp->iommu_tlb_data;
327 *softsp->iommu_flush_reg = (uint64_t)ioaddr;
334 tmpreg = *softsp->sbus_ctrl_reg;
347 softsp->iommu_dvma_base)))
366 struct sbus_soft_state *softsp = mppriv->softsp;
372 ASSERT(softsp != NULL);
381 mutex_enter(&softsp->iomemlock);
382 prevp = &softsp->iomem;
383 walk = softsp->iomem;
394 mutex_exit(&softsp->iomemlock);
400 iotte_ptr = IOTTE_NDX(ioaddr, softsp->soft_tsb_base_addr);
407 iommu_tlb_flush(softsp, ioaddr, 1);
428 struct sbus_soft_state *softsp = mppriv->softsp;
435 ASSERT(softsp != NULL);
443 iotte_ptr = IOTTE_NDX(ioaddr, softsp->soft_tsb_base_addr);
459 } else if (softsp->stream_buf_off) {
480 iommu_tlb_flush(softsp, ioaddr, npages);
504 if (IS_INTRA_SBUS(softsp, pfn)) {
536 iommu_tlb_flush(softsp, ioaddr, 1);
551 mutex_enter(&softsp->iomemlock);
552 iomemp->next = softsp->iomem;
553 softsp->iomem = iomemp;
554 mutex_exit(&softsp->iomemlock);
578 struct sbus_soft_state *softsp = mppriv->softsp;
589 ASSERT(softsp != NULL);
594 iotte_ptr = IOTTE_NDX(ioaddr, softsp->soft_tsb_base_addr);
605 } else if (softsp->stream_buf_off) {
626 iommu_tlb_flush(softsp, ioaddr, npages);
647 iommu_tlb_flush(softsp, ioaddr, 1);
664 mutex_enter(&softsp->iomemlock);
665 iomemp->next = softsp->iomem;
666 softsp->iomem = iomemp;
667 mutex_exit(&softsp->iomemlock);
676 struct sbus_soft_state *softsp, uint_t *burstsizep, uint_t burstsize64,
686 *burstsizep &= softsp->sbus_burst_sizes;
694 if (!softsp->sbus64_burst_sizes || (ddi_get_parent(rdip) != dip)) {
699 *burstsizep &= softsp->sbus_burst_sizes;
705 *burstsizep &= softsp->sbus_burst_sizes;
712 *burstsizep &= (softsp->sbus64_burst_sizes |
713 softsp->sbus_burst_sizes);
719 *burstsizep &= (softsp->sbus64_burst_sizes >>
728 (1 << (ddi_ffs(softsp->sbus64_burst_sizes) - 1)));
742 struct sbus_soft_state *softsp = (struct sbus_soft_state *)
748 (void) iommu_dma_lim_setup(dip, rdip, softsp,
764 (addrhigh < (ioaddr_t)softsp->iommu_dvma_base)) {
776 &softsp->dvma_call_list_id);
797 mppriv->softsp = softsp;
809 struct sbus_soft_state *softsp = mppriv->softsp;
810 ASSERT(softsp != NULL);
814 if (softsp->dvma_call_list_id != 0) {
815 ddi_run_callback(&softsp->dvma_call_list_id);
862 struct sbus_soft_state *softsp;
921 softsp = mppriv->softsp;
922 ASSERT(softsp != NULL);
955 if (npages >= iommu_btop(softsp->iommu_dvma_size) -
970 ioaddr = (ioaddr_t)(uintptr_t)vmem_alloc(softsp->dvma_arena,
993 softsp->soft_tsb_base_addr);
998 } else if (softsp->stream_buf_off)
1008 iommu_tlb_flush(softsp, ioaddr, 1);
1037 mutex_enter(&softsp->iomemlock);
1038 iomemp->next = softsp->iomem;
1039 softsp->iomem = iomemp;
1040 mutex_exit(&softsp->iomemlock);
1046 ioaddr = (ioaddr_t)(uintptr_t)vmem_xalloc(softsp->dvma_arena,
1065 ASSERT(mp->dmai_mapping >= softsp->iommu_dvma_base);
1104 vmem_free(softsp->dvma_arena, (void *)(uintptr_t)ioaddr,
1107 vmem_xfree(softsp->dvma_arena, (void *)(uintptr_t)ioaddr,
1115 dmareq->dmar_arg, &softsp->dvma_call_list_id);
1131 struct sbus_soft_state *softsp = mppriv->softsp;
1132 ASSERT(softsp != NULL);
1144 sync_stream_buf(softsp, addr, npages, (int *)&mppriv->sync_flag,
1157 vmem_free(softsp->dvma_arena, (void *)(uintptr_t)addr, size);
1159 vmem_xfree(softsp->dvma_arena, (void *)(uintptr_t)addr, size);
1165 if (softsp->dvma_call_list_id != 0)
1166 ddi_run_callback(&softsp->dvma_call_list_id);
1181 sync_stream_buf(mppriv->softsp, mp->dmai_mapping,
1296 sync_stream_buf(mppriv->softsp, mp->dmai_mapping,
1322 return (iommu_dma_lim_setup(dip, rdip, mppriv->softsp,
1336 struct sbus_soft_state *softsp =
1347 if ((AHI <= ALO) || (AHI < softsp->iommu_dvma_base)) {
1354 mutex_enter(&softsp->dma_pool_lock);
1355 if (np > softsp->dma_reserve) {
1356 mutex_exit(&softsp->dma_pool_lock);
1362 softsp->dma_reserve -= np;
1363 mutex_exit(&softsp->dma_pool_lock);
1370 ioaddr = (ioaddr_t)(uintptr_t)vmem_xalloc(softsp->dvma_arena,
1377 mutex_enter(&softsp->dma_pool_lock);
1378 softsp->dma_reserve += np;
1379 mutex_exit(&softsp->dma_pool_lock);
1413 iommu_fast_dvma->softsp = (caddr_t)softsp;
1433 struct sbus_soft_state *softsp = (struct sbus_soft_state *)
1434 iommu_fast_dvma->softsp;
1436 ASSERT(softsp != NULL);
1439 iotte_ptr = IOTTE_NDX(ioaddr, softsp->soft_tsb_base_addr);
1443 iommu_tlb_flush(softsp, ioaddr, 1);
1451 mutex_enter(&softsp->dma_pool_lock);
1452 softsp->dma_reserve += np;
1453 mutex_exit(&softsp->dma_pool_lock);
1456 vmem_free(softsp->dvma_arena,
1459 vmem_xfree(softsp->dvma_arena,
1477 if (softsp->dvma_call_list_id != 0)
1478 ddi_run_callback(&softsp->dvma_call_list_id);
1509 struct sbus_soft_state *softsp = (struct sbus_soft_state *)
1510 iommu_fast_dvma->softsp;
1516 ASSERT(softsp != NULL);
1539 iotte_ptr = IOTTE_NDX(ioaddr, softsp->soft_tsb_base_addr);
1545 else if (!softsp->stream_buf_off)
1559 iommu_tlb_flush(softsp, ioaddr, 1);
1578 mutex_enter(&softsp->iomemlock);
1579 iomemp->next = softsp->iomem;
1580 softsp->iomem = iomemp;
1581 mutex_exit(&softsp->iomemlock);
1594 struct sbus_soft_state *softsp = (struct sbus_soft_state *)
1595 iommu_fast_dvma->softsp;
1600 ASSERT(softsp != NULL);
1606 mutex_enter(&softsp->iomemlock);
1607 prevp = &softsp->iomem;
1608 walk = softsp->iomem;
1618 mutex_exit(&softsp->iomemlock);
1631 sync_stream_buf(softsp, ioaddr, npages,
1646 struct sbus_soft_state *softsp = (struct sbus_soft_state *)
1647 iommu_fast_dvma->softsp;
1652 ASSERT(softsp != NULL);
1661 sync_stream_buf(softsp, ioaddr, npages,