Lines Matching defs:counter
128 * Add counter number to base address to get corresponding MSR address.
134 * Base MSR addresses for the PerfEvtSel registers and counters. The counter and
135 * event select registers are interleaved, so one needs to multiply the counter
179 uint64_t opt_rawpic; /* Raw counter value */
211 * When programming a performance counter there are two different values that we
492 opt_pcbe_pes_addr(uint_t counter)
494 ASSERT3U(counter, <, opd.opd_ncounters);
495 return (PES_BASE_ADDR + counter);
499 opt_pcbe_pes_ext_addr(uint_t counter)
501 ASSERT3U(counter, <, opd.opd_ncounters);
502 return (PES_EXT_BASE_ADDR + 2 * counter);
506 opt_pcbe_pic_addr(uint_t counter)
508 ASSERT3U(counter, <, opd.opd_ncounters);
509 return (PIC_BASE_ADDR + 2 * counter);
513 opt_pcbe_pic_ext_addr(uint_t counter)
515 ASSERT3U(counter, <, opd.opd_ncounters);
516 return (PIC_EXT_BASE_ADDR + 2 * counter);
546 * Determine whether or not the extended counter set is supported on
693 * Check whether counter event is supported
708 * Unfortunately, this chip cannot detect which counter overflowed, so
728 * the counter value.
853 * Program in two loops. The first configures and presets the counter,
878 * Disable non-privileged access to the counter registers.