Lines Matching defs:new

112 	x86pte_t new);
303 	 * tables for the new hat.
835  * part of the address range.  From this point on we can't use any new
979  * Switch to a new active hat, maintaining bit masks to track active CPUs.
1119 hat_dup(hat_t *old, hat_t *new, caddr_t addr, size_t len, uint_t flag)
1122 	ASSERT(new != kas.a_hat);
1335 	 * Set the new pte, retrieving the old one at the same time.
1356 	 * Install a new mapping in the page's mapping list
1473 	 * construct the new PTE
1566  * Installing new valid PTE's and creation of the mapping list
1747  *	until another store occurs.  The default is to fetch new data
1989 #define	CAS_TLB_INFO(cpu, old, new)	\
1990 	atomic_cas_ulong((ulong_t *)&(cpu)->cpu_m.mcpu_tlb_info, (old), (new))
2509 	x86pte_t	new;
2554 			new = pte;
2555 			PTE_CLR(new, PT_REF | PT_MOD);
2556 			pte = hati_update_pte(ht, entry, pte, new);
2661 		 * figure out the new attributes.
2714 		 * If new PTE really changed, update the table.
3036 		 * create new mappings from the values in the ISM mappings.
3060 			 * Make a new pte for the PFN for this level.
3190 	x86pte_t	new;
3216 			new = old;
3217 			PTE_CLR(new, PT_REF | PT_MOD | PT_WRITABLE);
3218 			old = hati_update_pte(ht, entry, old, new);
3518 	 * and no new can be setup since pp is locked exclusively.
3669 	x86pte_t	new;
3720 			new = old;
3721 			PTE_CLR(new, PT_REF | PT_MOD);
3722 			old = hati_update_pte(ht, entry, old, new);
3844  * Setup the given brand new hat structure as the new HAT on this cpu's mmu.
3966 	 * Remap the given PTE to the new page's PFN. Invalidate only
4092  * Atomically update a new translation for a single page.  If the
4100 hati_update_pte(htable_t *ht, uint_t entry, x86pte_t expected, x86pte_t new)
4108 	    (PTE_GET(new, PT_NOSYNC) || !PTE_GET(new, PT_WRITABLE) ||
4109 	    !PTE_GET(new, PT_MOD | PT_REF))) {
4118 		PTE_CLR(new, PT_MOD | PT_REF);
4121 	replaced = x86pte_update(ht, entry, expected, new);