Lines Matching defs:port

275 yge_mii_readreg(yge_port_t *port, uint8_t phy, uint8_t reg)
277 yge_dev_t *dev = port->p_dev;
278 int pnum = port->p_port;
304 yge_mii_writereg(yge_port_t *port, uint8_t phy, uint8_t reg, uint16_t val)
306 yge_dev_t *dev = port->p_dev;
307 int pnum = port->p_port;
319 yge_error(NULL, port, "phy write timeout");
325 yge_port_t *port = arg;
328 PHY_LOCK(port->p_dev);
329 rv = yge_mii_readreg(port, phy, reg);
330 PHY_UNLOCK(port->p_dev);
337 yge_port_t *port = arg;
339 PHY_LOCK(port->p_dev);
340 yge_mii_writereg(port, phy, reg, val);
341 PHY_UNLOCK(port->p_dev);
351 yge_port_t *port = arg;
352 yge_dev_t *dev = port->p_dev;
359 fc = mii_get_flowctrl(port->p_mii);
360 duplex = mii_get_duplex(port->p_mii);
361 speed = mii_get_speed(port->p_mii);
368 CSR_WRITE_1(dev, MR_ADDR(port->p_port, GMAC_IRQ_MSK),
418 GMAC_WRITE_2(dev, port->p_port, GM_GP_CTRL, gpcr);
421 (void) GMAC_READ_2(dev, port->p_port, GM_GP_CTRL);
424 CSR_WRITE_4(dev, MR_ADDR(port->p_port, GMAC_CTRL), gmac);
428 gpcr = GMAC_READ_2(dev, port->p_port, GM_GP_CTRL);
430 GMAC_WRITE_2(dev, port->p_port, GM_GP_CTRL, gpcr);
433 (void) GMAC_READ_2(dev, port->p_port, GM_GP_CTRL);
438 mac_link_update(port->p_mh, link);
440 if (port->p_running && (link == LINK_STATE_UP)) {
441 mac_tx_update(port->p_mh);
446 yge_setrxfilt(yge_port_t *port)
454 dev = port->p_dev;
455 pnum = port->p_port;
456 ea = port->p_curraddr;
457 mchash = port->p_mchash;
474 if (port->p_promisc) {
489 yge_init_rx_ring(yge_port_t *port)
495 port->p_rx_cons = 0;
496 port->p_rx_putwm = YGE_PUT_WM;
497 ring = &port->p_rx_ring;
504 rxb = &port->p_rx_buf[prod];
507 PUTCTRL(ring, prod, port->p_framesize | OP_PACKET | HW_OWNER);
512 yge_set_prefetch(port->p_dev, port->p_rxq, ring);
515 CSR_WRITE_2(port->p_dev,
516 Y2_PREF_Q_ADDR(port->p_rxq, PREF_UNIT_PUT_IDX_REG),
521 yge_init_tx_ring(yge_port_t *port)
523 yge_ring_t *ring = &port->p_tx_ring;
525 port->p_tx_prod = 0;
526 port->p_tx_cons = 0;
527 port->p_tx_cnt = 0;
532 yge_set_prefetch(port->p_dev, port->p_txq, ring);
822 * On dual port PCI-X card, there is an problem where status
909 yge_init_port(yge_port_t *port)
911 yge_dev_t *dev = port->p_dev;
915 port->p_flags = dev->d_pflags;
916 port->p_ppa = ddi_get_instance(dev->d_dip) + (port->p_port * 100);
918 port->p_tx_buf = kmem_zalloc(sizeof (yge_buf_t) * YGE_TX_RING_CNT,
920 port->p_rx_buf = kmem_zalloc(sizeof (yge_buf_t) * YGE_RX_RING_CNT,
924 if (port->p_port == YGE_PORT_A) {
925 port->p_txq = Q_XA1;
926 port->p_txsq = Q_XS1;
927 port->p_rxq = Q_R1;
929 port->p_txq = Q_XA2;
930 port->p_txsq = Q_XS2;
931 port->p_rxq = Q_R2;
936 port->p_flags |= PORT_FLAG_NOJUMBO;
945 port->p_mtu = ETHERMTU;
947 port->p_mii = mii_alloc(port, dev->d_dip, &yge_mii_ops);
948 if (port->p_mii == NULL) {
949 yge_error(NULL, port, "MII handle allocation failed");
953 mii_set_pauseable(port->p_mii, B_TRUE, B_TRUE);
957 * dual port cards actually come with three station
958 * addresses: one for each port, plus an extra. The
965 port->p_curraddr[i] =
966 CSR_READ_1(dev, B2_MAC_1 + (port->p_port * 8) + i);
971 yge_error(NULL, port, "MAC handle allocation failed");
975 macp->m_driver = port;
977 macp->m_src_addr = port->p_curraddr;
980 macp->m_max_sdu = port->p_mtu;
981 macp->m_instance = port->p_ppa;
984 port->p_mreg = macp;
1010 * it would be nice to have a separate interrupt per port. But right
1333 yge_port_t *port = dev->d_port[i];
1334 if (yge_init_port(port) != DDI_SUCCESS) {
1345 yge_port_t *port = dev->d_port[i];
1346 if (yge_register_port(port) == DDI_SUCCESS) {
1372 yge_register_port(yge_port_t *port)
1374 if (mac_register(port->p_mreg, &port->p_mh) != DDI_SUCCESS) {
1375 yge_error(NULL, port, "MAC registration failed");
1383 * Free up port specific resources. This is called only when the
1384 * port is not registered (and hence not running).
1387 yge_uninit_port(yge_port_t *port)
1389 ASSERT(!port->p_running);
1391 if (port->p_mreg)
1392 mac_free(port->p_mreg);
1394 if (port->p_mii)
1395 mii_free(port->p_mii);
1397 yge_txrx_dma_free(port);
1399 if (port->p_tx_buf)
1400 kmem_free(port->p_tx_buf,
1402 if (port->p_rx_buf)
1403 kmem_free(port->p_rx_buf,
1465 yge_alloc_ring(yge_port_t *port, yge_dev_t *dev, yge_ring_t *ring, uint32_t num)
1474 if (port && !dev)
1475 dev = port->p_dev;
1483 yge_error(dev, port, "Unable to allocate ring DMA handle");
1491 yge_error(dev, port, "Unable to allocate ring DMA memory");
1503 yge_error(dev, port, "Unable to bind ring DMA handle");
1528 yge_alloc_buf(yge_port_t *port, yge_buf_t *b, size_t bufsz, int flag)
1530 yge_dev_t *dev = port->p_dev;
1543 yge_error(NULL, port, "Unable to alloc DMA handle for buffer");
1550 yge_error(NULL, port, "Unable to alloc DMA memory for buffer");
1557 yge_error(NULL, port, "Unable to bind DMA handle for buffer");
1581 yge_txrx_dma_alloc(yge_port_t *port)
1600 bufsz = port->p_mtu;
1603 rv = yge_alloc_ring(port, NULL, &port->p_tx_ring, YGE_TX_RING_CNT);
1609 b = port->p_tx_buf;
1611 rv = yge_alloc_buf(port, b, bufsz,
1620 rv = yge_alloc_ring(port, NULL, &port->p_rx_ring, YGE_RX_RING_CNT);
1626 b = port->p_rx_buf;
1628 rv = yge_alloc_buf(port, b, bufsz,
1640 yge_txrx_dma_free(yge_port_t *port)
1645 yge_free_ring(&port->p_tx_ring);
1648 yge_free_ring(&port->p_rx_ring);
1651 b = port->p_tx_buf;
1656 b = port->p_rx_buf;
1663 yge_send(yge_port_t *port, mblk_t *mp)
1665 yge_ring_t *ring = &port->p_tx_ring;
1675 if (len > port->p_framesize) {
1682 if (port->p_tx_cnt + 1 >=
1684 port->p_wantw = B_TRUE;
1688 prod = port->p_tx_prod;
1690 txb = &port->p_tx_buf[prod];
1697 port->p_tx_cnt++;
1702 port->p_tx_prod = prod;
1711 yge_port_t *port = dev->d_port[i];
1712 mii_suspend(port->p_mii);
1719 yge_port_t *port = dev->d_port[i];
1721 if (port->p_running) {
1722 yge_stop_port(port);
1787 yge_port_t *port = dev->d_port[i];
1789 if (port != NULL && port->p_running) {
1790 yge_start_port(port);
1799 yge_port_t *port = dev->d_port[i];
1801 if (port->p_running) {
1802 mii_resume(port->p_mii);
1803 mac_tx_update(port->p_mh);
1811 yge_rxeof(yge_port_t *port, uint32_t status, int len)
1813 yge_dev_t *dev = port->p_dev;
1821 if (!port->p_running)
1824 ring = &port->p_rx_ring;
1825 cons = port->p_rx_cons;
1827 rxb = &port->p_rx_buf[cons];
1838 if ((len > port->p_framesize) || (rxlen != len)) {
1842 if ((len > port->p_framesize) || (rxlen != len) ||
1857 port->p_stats.rx_nobuf++;
1862 PUTCTRL(ring, cons, port->p_framesize | OP_PACKET | HW_OWNER);
1866 Y2_PREF_Q_ADDR(port->p_rxq, PREF_UNIT_PUT_IDX_REG),
1869 YGE_INC(port->p_rx_cons, YGE_RX_RING_CNT);
1875 yge_txeof_locked(yge_port_t *port, int idx)
1881 if (!port->p_running) {
1885 cons = port->p_tx_cons;
1888 if (port->p_tx_cnt <= 0)
1891 port->p_tx_cnt--;
1895 port->p_tx_cons = cons;
1898 resched = port->p_wantw;
1899 port->p_tx_wdog = 0;
1900 port->p_wantw = B_FALSE;
1908 yge_txeof(yge_port_t *port, int idx)
1912 TX_LOCK(port->p_dev);
1914 resched = yge_txeof_locked(port, idx);
1916 TX_UNLOCK(port->p_dev);
1918 if (resched && port->p_running) {
1919 mac_tx_update(port->p_mh);
1926 yge_port_t *port;
1932 port = dev->d_port[i];
1933 if (port->p_running)
1938 port = dev->d_port[i];
1940 if (port->p_running)
1941 yge_start_port(port);
1947 port = dev->d_port[i];
1949 mii_reset(port->p_mii);
1950 if (port->p_running)
1951 mac_tx_update(port->p_mh);
1959 yge_port_t *port;
1972 port = dev->d_port[i];
1974 if (!port->p_running)
1977 if (port->p_tx_cnt) {
1984 ridx = port->p_port == YGE_PORT_A ?
1987 if (port->p_tx_cons != idx) {
1988 resched = yge_txeof_locked(port, idx);
1993 port->p_tx_wdog++;
1994 if (port->p_tx_wdog > YGE_TX_TIMEOUT) {
1995 port->p_tx_wdog = 0;
1996 yge_error(NULL, port,
2010 port = dev->d_port[i];
2012 if (port->p_running)
2013 mac_tx_update(port->p_mh);
2020 yge_intr_gmac(yge_port_t *port)
2022 yge_dev_t *dev = port->p_dev;
2023 int pnum = port->p_port;
2032 yge_error(NULL, port, "Rx FIFO overrun!");
2038 yge_error(NULL, port, "Tx FIFO underrun!");
2043 * status LEs would affect the other port in dual MAC
2053 yge_handle_hwerr(yge_port_t *port, uint32_t status)
2055 yge_dev_t *dev = port->p_dev;
2058 yge_error(NULL, port, "RAM buffer read parity error");
2060 CSR_WRITE_2(dev, SELECT_RAM_BUFFER(port->p_port, B3_RI_CTRL),
2064 yge_error(NULL, port, "RAM buffer write parity error");
2066 CSR_WRITE_2(dev, SELECT_RAM_BUFFER(port->p_port, B3_RI_CTRL),
2070 yge_error(NULL, port, "Tx MAC parity error");
2072 CSR_WRITE_4(dev, MR_ADDR(port->p_port, TX_GMF_CTRL_T),
2076 yge_error(NULL, port, "Rx parity error");
2078 CSR_WRITE_4(dev, Q_ADDR(port->p_rxq, Q_CSR), BMU_CLR_IRQ_PAR);
2081 yge_error(NULL, port, "TCP segmentation error");
2083 CSR_WRITE_4(dev, Q_ADDR(port->p_txq, Q_CSR), BMU_CLR_IRQ_TCP);
2175 yge_port_t *port;
2206 port = dev->d_port[pnum];
2207 if (port == NULL) {
2208 yge_error(dev, NULL, "Invalid port opcode: 0x%08x",
2215 mp = yge_rxeof(port, status, len);
2376 yge_set_tx_stfwd(yge_port_t *port)
2378 yge_dev_t *dev = port->p_dev;
2379 int pnum = port->p_port;
2386 if (port->p_mtu > ETHERMTU)
2395 if (port->p_mtu > ETHERMTU) {
2412 yge_start_port(yge_port_t *port)
2414 yge_dev_t *dev = port->p_dev;
2421 pnum = port->p_port;
2422 txq = port->p_txq;
2423 rxq = port->p_rxq;
2425 if (port->p_mtu < ETHERMTU)
2426 port->p_framesize = ETHERMTU;
2428 port->p_framesize = port->p_mtu;
2429 port->p_framesize += sizeof (struct ether_vlan_header);
2455 yge_stats_clear(port);
2474 if (port->p_mtu > ETHERMTU)
2493 yge_setrxfilt(port);
2519 if ((port->p_flags & PORT_FLAG_RAMBUF) == 0) {
2534 yge_set_tx_stfwd(port);
2555 yge_set_rambuffer(port);
2558 CSR_WRITE_1(dev, RB_ADDR(port->p_txsq, RB_CTRL), RB_RST_SET);
2598 yge_init_tx_ring(port);
2604 yge_init_rx_ring(port);
2607 if (port == dev->d_port[YGE_PORT_A]) {
2610 } else if (port == dev->d_port[YGE_PORT_B]) {
2622 GMAC_WRITE_2(port->p_dev, port->p_port, GM_GP_CTRL, gmac);
2627 port->p_tx_wdog = 0;
2631 yge_set_rambuffer(yge_port_t *port)
2639 dev = port->p_dev;
2640 pnum = port->p_port;
2641 rxq = port->p_rxq;
2642 txq = port->p_txq;
2644 if ((port->p_flags & PORT_FLAG_RAMBUF) == 0)
2705 yge_stop_port(yge_port_t *port)
2707 yge_dev_t *dev = port->p_dev;
2708 int pnum = port->p_port;
2709 uint32_t txq = port->p_txq;
2710 uint32_t rxq = port->p_rxq;
2714 dev = port->p_dev;
2719 port->p_tx_wdog = 0;
2742 yge_stats_update(port);
2757 yge_error(NULL, port, "Tx BMU stop failed");
2803 yge_error(NULL, port, "Rx BMU stop failed");
2828 yge_stats_clear(yge_port_t *port)
2834 pnum = port->p_port;
2835 dev = port->p_dev;
2849 yge_stats_update(yge_port_t *port)
2856 dev = port->p_dev;
2857 pnum = port->p_port;
2859 if (dev->d_suspended || !port->p_running) {
2862 stats = &port->p_stats;
2943 yge_port_t *port = arg;
2944 struct yge_hw_stats *stats = &port->p_stats;
2952 DEV_LOCK(port->p_dev);
2953 yge_stats_update(port);
2954 DEV_UNLOCK(port->p_dev);
2957 if (mii_m_getstat(port->p_mii, stat, val) == 0) {
3055 yge_port_t *port = arg;
3057 DEV_LOCK(port->p_dev);
3062 * elsewhere, if the port is not actually being used.
3067 if (yge_txrx_dma_alloc(port) != DDI_SUCCESS) {
3069 yge_txrx_dma_free(port);
3070 DEV_UNLOCK(port->p_dev);
3074 if (!port->p_dev->d_suspended)
3075 yge_start_port(port);
3076 port->p_running = B_TRUE;
3077 DEV_UNLOCK(port->p_dev);
3079 mii_start(port->p_mii);
3087 yge_port_t *port = arg;
3088 yge_dev_t *dev = port->p_dev;
3092 yge_stop_port(port);
3094 port->p_running = B_FALSE;
3097 yge_txrx_dma_free(port);
3104 yge_port_t *port = arg;
3106 DEV_LOCK(port->p_dev);
3109 port->p_promisc = on;
3110 yge_setrxfilt(port);
3112 DEV_UNLOCK(port->p_dev);
3120 yge_port_t *port = arg;
3127 DEV_LOCK(port->p_dev);
3129 if (port->p_mccount[bit] == 0) {
3131 port->p_mchash[bit / 32] |= (1 << (bit % 32));
3134 port->p_mccount[bit]++;
3136 ASSERT(port->p_mccount[bit] > 0);
3137 port->p_mccount[bit]--;
3138 if (port->p_mccount[bit] == 0) {
3139 port->p_mchash[bit / 32] &= ~(1 << (bit % 32));
3145 yge_setrxfilt(port);
3147 DEV_UNLOCK(port->p_dev);
3154 yge_port_t *port = arg;
3156 DEV_LOCK(port->p_dev);
3158 bcopy(macaddr, port->p_curraddr, ETHERADDRL);
3159 yge_setrxfilt(port);
3161 DEV_UNLOCK(port->p_dev);
3169 yge_port_t *port = arg;
3176 TX_LOCK(port->p_dev);
3178 if (port->p_dev->d_suspended) {
3180 TX_UNLOCK(port->p_dev);
3191 ridx = port->p_port == YGE_PORT_A ?
3193 idx = CSR_READ_2(port->p_dev, ridx);
3194 if (port->p_tx_cons != idx)
3195 resched = yge_txeof_locked(port, idx);
3201 if (!yge_send(port, mp)) {
3211 CSR_WRITE_2(port->p_dev,
3212 Y2_PREF_Q_ADDR(port->p_txq, PREF_UNIT_PUT_IDX_REG),
3213 port->p_tx_prod);
3216 TX_UNLOCK(port->p_dev);
3219 mac_tx_update(port->p_mh);
3229 yge_port_t *port = arg;
3236 if (mii_m_loop_ioctl(port->p_mii, wq, mp))
3249 yge_port_t *port = arg;
3253 err = mii_m_setprop(port->p_mii, pr_name, pr_num, pr_valsize, pr_val);
3258 DEV_LOCK(port->p_dev);
3267 if (new_mtu == port->p_mtu) {
3273 yge_error(NULL, port,
3278 if (new_mtu > (port->p_flags & PORT_FLAG_NOJUMBO ?
3280 yge_error(NULL, port,
3285 if (port->p_running) {
3286 yge_error(NULL, port,
3319 err = mac_maxsdu_update(port->p_mh, new_mtu);
3322 yge_error(NULL, port,
3325 port->p_mtu = new_mtu;
3335 DEV_UNLOCK(port->p_dev);
3344 yge_port_t *port = arg;
3346 return (mii_m_getprop(port->p_mii, pr_name, pr_num, pr_valsize,
3354 yge_port_t *port = arg;
3359 port->p_flags & PORT_FLAG_NOJUMBO ?
3363 mii_m_propinfo(port->p_mii, pr_name, pr_num, prh);
3407 yge_error(yge_dev_t *dev, yge_port_t *port, char *fmt, ...)
3417 if (dev == NULL && port == NULL) {
3420 if (port != NULL)
3421 ppa = port->p_ppa;
3525 yge_port_t *port = dev->d_port[i];
3526 if (port->p_running)
3527 yge_stop_port(port);