Lines Matching defs:adapter
54 static int phy_lock(struct unm_adapter_s *adapter)
61 adapter->unm_nic_pci_read_immediate(adapter,
70 adapter->unm_crb_writelit_adapter(adapter, UNM_PHY_LOCK_ID,
76 phy_unlock(struct unm_adapter_s *adapter)
81 adapter->unm_nic_pci_read_immediate(adapter,
99 unm_niu_gbe_phy_read(struct unm_adapter_s *adapter, long reg,
102 long phy = adapter->physical_port;
112 if (phy_lock(adapter) != 0)
119 adapter->unm_nic_hw_read_wx(adapter, UNM_NIU_GB_MAC_CONFIG_0(0),
128 adapter->unm_nic_hw_write_wx(adapter,
136 adapter->unm_nic_hw_write_wx(adapter, UNM_NIU_GB_MII_MGMT_ADDR(0),
140 adapter->unm_nic_hw_write_wx(adapter, UNM_NIU_GB_MII_MGMT_COMMAND(0),
145 adapter->unm_nic_hw_write_wx(adapter, UNM_NIU_GB_MII_MGMT_COMMAND(0),
150 adapter->unm_nic_hw_read_wx(adapter,
157 adapter->unm_nic_hw_read_wx(adapter,
164 adapter->unm_nic_hw_write_wx(adapter,
167 phy_unlock(adapter);
177 unm_niu_macaddr_get(struct unm_adapter_s *adapter, unsigned char *addr)
180 int phy = adapter->physical_port;
187 UNM_WRITE_LOCK_IRQS(&adapter->adapter_lock, flags);
188 if (adapter->curr_window != 0) {
189 adapter->unm_nic_pci_change_crbwindow(adapter, 0);
192 result = UNM_NIC_PCI_READ_32((void *)pci_base_offset(adapter,
195 adapter, UNM_NIU_GB_STATION_ADDR_0(phy)))) << 16;
199 adapter->unm_nic_pci_change_crbwindow(adapter, 1);
201 UNM_WRITE_UNLOCK_IRQR(&adapter->adapter_lock, flags);
211 unm_niu_macaddr_set(struct unm_adapter_s *adapter, unm_ethernet_macaddr_t addr)
214 int phy = adapter->physical_port;
221 adapter->unm_nic_hw_write_wx(adapter, UNM_NIU_GB_STATION_ADDR_1(phy),
225 adapter->unm_nic_hw_write_wx(adapter, UNM_NIU_GB_STATION_ADDR_0(phy),
232 native_t unm_niu_enable_gbe_port(struct unm_adapter_s *adapter,
238 native_t port = adapter->physical_port;
249 if (adapter->link_speed != MBPS_10 &&
250 adapter->link_speed != MBPS_100 &&
251 adapter->link_speed != MBPS_1000) {
253 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
258 adapter->link_speed = MBPS_1000;
264 port_mode = adapter->unm_nic_pci_read_normalize(adapter,
270 adapter);
272 adapter);
277 adapter);
289 adapter);
299 switch (adapter->link_speed) {
304 (port), &mac_cfg1, adapter);
309 &zero, adapter);
312 &one, adapter);
319 &mac_cfg1, adapter);
324 &zero, adapter);
327 &one, adapter);
338 &mii_cfg, adapter);
346 &mac_cfg0, adapter);
354 unm_niu_disable_gbe_port(struct unm_adapter_s *adapter)
356 native_t port = adapter->physical_port;
365 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
366 adapter->unm_nic_hw_write_wx(adapter,
369 adapter->unm_nic_hw_write_wx(adapter,
376 unm_niu_disable_xg_port(struct unm_adapter_s *adapter)
378 native_t port = adapter->physical_port;
384 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
387 adapter->unm_nic_hw_write_wx(adapter, UNM_NIU_XGE_CONFIG_0,
392 adapter->unm_nic_hw_write_wx(adapter, UNM_NIU_XGE_CONFIG_0 +
401 unm_niu_set_promiscuous_mode(struct unm_adapter_s *adapter,
404 native_t port = adapter->physical_port;
415 adapter->unm_nic_hw_read_wx(adapter, UNM_NIU_GB_MAC_CONFIG_0(port),
418 adapter->unm_nic_hw_write_wx(adapter, UNM_NIU_GB_MAC_CONFIG_0(port),
424 adapter->unm_crb_writelit_adapter(adapter, UNM_NIU_FRAME_COUNT_SELECT,
428 adapter->unm_nic_hw_read_wx(adapter, UNM_NIU_FRAME_COUNT,
445 adapter->unm_nic_hw_read_wx(adapter, UNM_NIU_GB_DROP_WRONGADDR,
464 adapter->unm_nic_hw_write_wx(adapter, UNM_NIU_GB_DROP_WRONGADDR,
470 adapter->unm_nic_hw_write_wx(adapter, UNM_NIU_GB_MAC_CONFIG_0(port),
481 unm_niu_xg_macaddr_set(struct unm_adapter_s *adapter,
484 int phy = adapter->physical_port;
495 port_mode = adapter->unm_nic_pci_read_normalize(adapter,
498 adapter->unm_nic_hw_write_wx(adapter,
503 adapter->unm_nic_hw_write_wx(adapter,
506 adapter->unm_nic_hw_write_wx(adapter,
511 adapter->unm_nic_hw_write_wx(adapter,
519 port_mode = adapter->unm_nic_pci_read_normalize(adapter,
522 adapter->unm_nic_hw_write_wx(adapter,
527 adapter->unm_nic_hw_write_wx(adapter,
530 adapter->unm_nic_hw_write_wx(adapter,
535 adapter->unm_nic_hw_write_wx(adapter,
549 unm_niu_xg_set_promiscuous_mode(struct unm_adapter_s *adapter,
554 native_t port = adapter->physical_port;
562 port_mode = adapter->unm_nic_pci_read_normalize(adapter,
567 adapter->unm_nic_hw_write_wx(adapter,
571 adapter->unm_nic_hw_read_wx(adapter, UNM_NIU_XGE_CONFIG_0 +
574 adapter->unm_nic_hw_write_wx(adapter, UNM_NIU_XGE_CONFIG_0 +
578 if ((adapter->ahw.boardcfg.board_type !=
580 (adapter->ahw.boardcfg.board_type !=
584 adapter->unm_crb_writelit_adapter(adapter,
589 adapter->unm_crb_writelit_adapter(adapter,
593 adapter->unm_nic_hw_read_wx(adapter,
605 adapter->unm_nic_hw_read_wx(adapter,
612 adapter->unm_crb_writelit_adapter(adapter,
618 adapter->unm_nic_hw_write_wx(adapter, UNM_NIU_XGE_CONFIG_0 +
626 unm_niu_xg_set_tx_flow_ctl(struct unm_adapter_s *adapter, int enable)
628 int port = adapter->physical_port;
634 adapter->unm_nic_hw_read_wx(adapter, UNM_NIU_XG_PAUSE_CTL, ®, 4);
640 adapter->unm_nic_hw_write_wx(adapter, UNM_NIU_XG_PAUSE_CTL, ®, 4);
646 unm_niu_gbe_set_tx_flow_ctl(struct unm_adapter_s *adapter, int enable)
648 int port = adapter->physical_port;
654 adapter->unm_nic_hw_read_wx(adapter, UNM_NIU_GB_PAUSE_CTL, ®, 4);
670 adapter->unm_nic_hw_write_wx(adapter, UNM_NIU_GB_PAUSE_CTL, ®, 4);
676 unm_niu_gbe_set_rx_flow_ctl(struct unm_adapter_s *adapter, int enable)
678 int port = adapter->physical_port;
684 adapter->unm_nic_hw_read_wx(adapter, UNM_NIU_GB_MAC_CONFIG_0(port),
687 adapter->unm_nic_hw_write_wx(adapter, UNM_NIU_GB_MAC_CONFIG_0(port),