Lines Matching defs:chp
85 static int ch_set_config_data(ch_t *chp);
86 void pe_rbuf_pool_free(ch_t *chp);
89 static int pe_change_mtu(ch_t *chp);
109 static int pe_make_fake_arp(ch_t *chp, unsigned char *arpp);
660 rm.chp = sa;
714 rm.chp = sa;
907 pe_attach(ch_t *chp)
913 (void) ch_set_config_data(chp);
915 bi = pe_sa_init(chp);
919 if (t1_init_sw_modules(chp, bi) < 0)
922 if (pe_small_rbuf_pool_init(chp) == NULL)
925 if (pe_big_rbuf_pool_init(chp) == NULL)
936 if (board_info(chp)->caps & SUPPORTED_10000baseT_Full) {
937 (void) t1_os_pci_read_config_4(chp, A_PCICFG_PCIX_CMD,
942 if (chp->ch_config.burstsize_set) {
944 pcix_cmd |= (chp->ch_config.burstsize << 18);
949 if (chp->ch_config.transaction_cnt_set) {
951 pcix_cmd |= (chp->ch_config.transaction_cnt << 20);
957 pcix_cmd |= (chp->ch_config.relaxed_ordering << 17);
959 (void) t1_os_pci_write_config_4(chp, A_PCICFG_PCIX_CMD,
968 if (board_info(chp)->caps & SUPPORTED_10000baseT_Full) {
969 (void) t1_os_pci_write_config_4(chp, 0xc, 0xf800);
977 update_mtu_tab(chp);
983 t1_interrupts_clear(chp);
1003 ch_set_config_data(ch_t *chp)
1005 pe_config_data_t *p_config = (pe_config_data_t *)&chp->config_data;
1554 pe_dma_handle_init(ch_t *chp, int cnt)
1561 dhe = ch_get_dvma_handle(chp);
1564 mutex_enter(&chp->ch_dh_lck);
1565 dhe->dhe_next = chp->ch_vdh;
1566 chp->ch_vdh = dhe;
1567 mutex_exit(&chp->ch_dh_lck);
1573 dhe = ch_get_dma_handle(chp);
1576 mutex_enter(&chp->ch_dh_lck);
1577 dhe->dhe_next = chp->ch_dh;
1578 chp->ch_dh = dhe;
1579 mutex_exit(&chp->ch_dh_lck);
1603 pe_change_mtu(ch_t *chp)
1605 struct cmac *mac = chp->port[0].mac;
1611 if (chp->ch_mtu < 68) {
1614 if (ret = mac->ops->set_mtu(mac, chp->ch_mtu)) {
1642 pe_make_fake_arp(ch_t *chp, unsigned char *arpp)
1644 pesge *sge = chp->sge;
1669 chp->ch_ip = fap->fa_src_ip; /* not used yet */