Lines Matching defs:os2
178 * os1, os2, os3: scratch registers, may be out
181 #define SERVE_INTR_PRE(iv_p, cpu, ls1, ls2, os1, os2, os3, regs) \
184 SERVE_INTR_TRACE(iv_p, os1, os2, os3, regs);
208 #define SERVE_INTR(os5, cpu, ls1, ls2, os1, os2, os3, os4) \
209 ldn [ls1 + IV_HANDLER], os2; \
212 call os2; \
222 add os1, CPU_STATS_SYS_INTR - 8, os2; \
223 ldx [cpu + os2], os3; \
225 stx os3, [cpu + os2]; \
226 sll ls1, CPTRSHIFT, os2; \
228 add os1, os2, os1; \
237 * os1, os2, os4, os5 - scratch reg, can be out (not preserved)
239 #define SERVE_INTR_NEXT(os5, cpu, ls1, ls2, os1, os2, os3, os4) \
244 lduh [os3 + IV_FLAGS], os2; \
245 and os2, IV_SOFTINT_MT, os2; \
246 brz,pt os2, 4f; \
247 add os3, IV_PIL_NEXT, os2; \
250 add os2, os5, os2; \
251 4: ldn [os2], os5; \
262 stn %g0, [os2]; \
266 SERVE_INTR_TRACE2(os5, os1, os2, os3, os4);
272 #define SERVE_INTR_TRACE(inum, os1, os2, os3, os4) \
274 andn os3, PSTATE_IE | PSTATE_AM, os2; \
275 wrpr %g0, os2, %pstate; \
276 TRACE_PTR(os1, os2); \
277 ldn [os4 + PC_OFF], os2; \
278 stna os2, [os1 + TRAP_ENT_TPC]%asi; \
279 ldx [os4 + TSTATE_OFF], os2; \
280 stxa os2, [os1 + TRAP_ENT_TSTATE]%asi; \
282 GET_TRACE_TICK(os2, os3); \
283 stxa os2, [os1 + TRAP_ENT_TICK]%asi; \
284 TRACE_SAVE_TL_GL_REGS(os1, os2); \
285 set TT_SERVE_INTR, os2; \
287 or os2, os3, os2; \
288 stha os2, [os1 + TRAP_ENT_TT]%asi; \
295 TRACE_NEXT(os1, os2, os3); \
298 #define SERVE_INTR_TRACE(inum, os1, os2, os3, os4)
305 #define SERVE_INTR_TRACE2(inum, os1, os2, os3, os4) \
307 andn os3, PSTATE_IE | PSTATE_AM, os2; \
308 wrpr %g0, os2, %pstate; \
309 TRACE_PTR(os1, os2); \
313 GET_TRACE_TICK(os2, os3); \
314 stxa os2, [os1 + TRAP_ENT_TICK]%asi; \
315 TRACE_SAVE_TL_GL_REGS(os1, os2); \
316 set TT_SERVE_INTR, os2; \
318 or os2, os3, os2; \
319 stha os2, [os1 + TRAP_ENT_TT]%asi; \
326 TRACE_NEXT(os1, os2, os3); \
329 #define SERVE_INTR_TRACE2(inum, os1, os2, os3, os4)