Lines Matching defs:pp

55 #define	ECPP_MAP_REGS(pp)		(pp)->hw->map_regs(pp)
56 #define ECPP_UNMAP_REGS(pp) (pp)->hw->unmap_regs(pp)
57 #define ECPP_CONFIG_CHIP(pp) (pp)->hw->config_chip(pp)
58 #define ECPP_CONFIG_MODE(pp) (pp)->hw->config_mode(pp)
59 #define ECPP_MASK_INTR(pp) (pp)->hw->mask_intr(pp)
60 #define ECPP_UNMASK_INTR(pp) (pp)->hw->unmask_intr(pp)
61 #define ECPP_DMA_START(pp) (pp)->hw->dma_start(pp)
62 #define ECPP_DMA_STOP(pp, cnt) (pp)->hw->dma_stop(pp, cnt)
63 #define ECPP_DMA_GETCNT(pp) (pp)->hw->dma_getcnt(pp)
413 #define DSR_READ(pp) PP_GETB((pp)->i_handle, &(pp)->i_reg->dsr)
414 #define DCR_READ(pp) PP_GETB((pp)->i_handle, &(pp)->i_reg->dcr)
415 #define ECR_READ(pp) \
416 (pp->noecpregs) ? 0xff : PP_GETB((pp)->f_handle, &(pp)->f_reg->ecr)
417 #define DATAR_READ(pp) PP_GETB((pp)->i_handle, &(pp)->i_reg->ir.datar)
418 #define DFIFO_READ(pp) \
419 (pp->noecpregs) ? 0xff : PP_GETB((pp)->f_handle, &(pp)->f_reg->fr.dfifo)
420 #define TFIFO_READ(pp) \
421 (pp->noecpregs) ? 0xff : PP_GETB((pp)->f_handle, &(pp)->f_reg->fr.tfifo)
423 #define DCR_WRITE(pp, val) PP_PUTB((pp)->i_handle, &(pp)->i_reg->dcr, val)
424 #define ECR_WRITE(pp, val) \
425 if (!pp->noecpregs) PP_PUTB((pp)->f_handle, &(pp)->f_reg->ecr, val)
426 #define DATAR_WRITE(pp, val) \
427 PP_PUTB((pp)->i_handle, &(pp)->i_reg->ir.datar, val)
428 #define DFIFO_WRITE(pp, val) \
429 if (!pp->noecpregs) PP_PUTB((pp)->f_handle, &(pp)->f_reg->fr.dfifo, val)
430 #define TFIFO_WRITE(pp, val) \
431 if (!pp->noecpregs) PP_PUTB((pp)->f_handle, &(pp)->f_reg->fr.tfifo, val)
480 #define SET_DMAC_CSR(pp, val) ddi_put32(pp->uh.ebus.d_handle, \
481 ((uint32_t *)&pp->uh.ebus.dmac->csr), \
483 #define GET_DMAC_CSR(pp) ddi_get32(pp->uh.ebus.d_handle, \
484 (uint32_t *)&(pp->uh.ebus.dmac->csr))
486 #define SET_DMAC_ACR(pp, val) ddi_put32(pp->uh.ebus.d_handle, \
487 ((uint32_t *)&pp->uh.ebus.dmac->acr), \
490 #define GET_DMAC_ACR(pp) ddi_get32(pp->uh.ebus.d_handle, \
491 (uint32_t *)&pp->uh.ebus.dmac->acr)
493 #define SET_DMAC_BCR(pp, val) ddi_put32(pp->uh.ebus.d_handle, \
494 ((uint32_t *)&pp->uh.ebus.dmac->bcr), \
497 #define GET_DMAC_BCR(pp) ddi_get32(pp->uh.ebus.d_handle, \
498 ((uint32_t *)&pp->uh.ebus.dmac->bcr))
505 #define COMPAT_PIO(pp) (((pp)->io_mode == ECPP_PIO) && \
506 ((pp)->current_mode == ECPP_CENTRONICS || \
507 (pp)->current_mode == ECPP_COMPAT_MODE))
509 #define COMPAT_DMA(pp) (((pp)->io_mode == ECPP_DMA) && \
510 ((pp)->current_mode == ECPP_CENTRONICS || \
511 (pp)->current_mode == ECPP_COMPAT_MODE))