Lines Matching defs:Queue

332 #define	B3_RI_WTO_R1	0x0190	/*  8 bit WR Timeout Queue R1 (TO0) */
333 #define B3_RI_WTO_XA1 0x0191 /* 8 bit WR Timeout Queue XA1 (TO1) */
334 #define B3_RI_WTO_XS1 0x0192 /* 8 bit WR Timeout Queue XS1 (TO2) */
335 #define B3_RI_RTO_R1 0x0193 /* 8 bit RD Timeout Queue R1 (TO3) */
336 #define B3_RI_RTO_XA1 0x0194 /* 8 bit RD Timeout Queue XA1 (TO4) */
337 #define B3_RI_RTO_XS1 0x0195 /* 8 bit RD Timeout Queue XS1 (TO5) */
338 #define B3_RI_WTO_R2 0x0196 /* 8 bit WR Timeout Queue R2 (TO6) */
339 #define B3_RI_WTO_XA2 0x0197 /* 8 bit WR Timeout Queue XA2 (TO7) */
340 #define B3_RI_WTO_XS2 0x0198 /* 8 bit WR Timeout Queue XS2 (TO8) */
341 #define B3_RI_RTO_R2 0x0199 /* 8 bit RD Timeout Queue R2 (TO9) */
342 #define B3_RI_RTO_XA2 0x019a /* 8 bit RD Timeout Queue XA2 (TO10) */
343 #define B3_RI_RTO_XS2 0x019b /* 8 bit RD Timeout Queue XS2 (TO11) */
376 /* Receive and Transmit Queue Registers, use Q_ADDR() to access */
379 /* Queue Register Offsets, use Q_ADDR() to access */
404 #define Q_ADDR(Queue, Offs) (B8_Q_REGS + (Queue) + (Offs))
406 /* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address */
422 #define Y2_PREF_Q_ADDR(Queue, Offs) (Y2_B8_PREF_REGS + (Queue) + (Offs))
691 #define Y2_IS_PAR_RX2 BIT(10) /* Parity Error Rx Queue 2 */
697 #define Y2_IS_PAR_RX1 BIT(2) /* Parity Error Rx Queue 1 */
941 #define BMU_STOP BIT(9) /* Stop Rx/Tx Queue */
942 #define BMU_START BIT(8) /* Start Rx/Tx Queue */
974 /* Queue Prefetch Unt Offsts, use Y2_PREF_Q_ADDR() to addrss (Yukon-2 only) */
981 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
1037 #define Q_R1 0x0000 /* Receive Queue 1 */
1038 #define Q_R2 0x0080 /* Receive Queue 2 */
1039 #define Q_XS1 0x0200 /* Synchronous Transmit Queue 1 */
1040 #define Q_XA1 0x0280 /* Asynchronous Transmit Queue 1 */
1041 #define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */
1042 #define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */
1044 #define Q_ASF_R1 0x100 /* ASF Rx Queue 1 */
1045 #define Q_ASF_R2 0x180 /* ASF Rx Queue 2 */
1046 #define Q_ASF_T1 0x140 /* ASF Tx Queue 1 */
1047 #define Q_ASF_T2 0x1c0 /* ASF Tx Queue 2 */
1049 #define RB_ADDR(Queue, Offs) (B16_RAM_REGS + (Queue) + (Offs))
1051 /* Minimum RAM Buffer Rx Queue Size */
1053 /* Minimum RAM Buffer Tx Queue Size */
2247 uint32_t p_txq; /* Tx. Async Queue offset */
2248 uint32_t p_txsq; /* Tx. Syn Queue offset */