Lines Matching defs:data

272  * a specified delay status is checked until the data is present.
299  * data and the target registers address are written to the PHY.
2785 	 * incoming data, we must reset the BMU while it is not during a DMA
2788 	 * data will not trigger a DMA. After the RAM buffer is stopped, the
2924 	uint_t		data;
2930 		for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) {
2932 			    ^ ((((crc >> 31) ^ data) & 1) ? POLY_BE : 0);
3313 		 * minimum they must not hold any locks across data
3315 		 * references to mac data structures are cleaned up