Lines Matching defs:sc
310 ural_read(struct ural_softc *sc, uint16_t reg)
327 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp,
347 ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len)
364 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp,
382 ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val)
397 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, NULL,
412 struct ural_softc *sc = (struct ural_softc *)req->bulk_client_private;
413 struct ieee80211com *ic = &sc->sc_ic;
420 sc->tx_queued);
423 sc->sc_tx_err++;
425 mutex_enter(&sc->tx_lock);
427 sc->tx_queued--;
428 sc->sc_tx_timer = 0;
430 if (sc->sc_need_sched) {
431 sc->sc_need_sched = 0;
435 mutex_exit(&sc->tx_lock);
443 struct ural_softc *sc = (struct ural_softc *)req->bulk_client_private;
444 struct ieee80211com *ic = &sc->sc_ic;
462 sc->rx_queued);
465 sc->sc_rx_err++;
475 sc->sc_rx_err++;
489 sc->sc_rx_err++;
507 sc->sc_rx_nobuf++;
523 mutex_enter(&sc->rx_lock);
524 sc->rx_queued--;
525 mutex_exit(&sc->rx_lock);
530 if (RAL_IS_RUNNING(sc))
531 (void) ural_rx_trigger(sc);
619 ural_setup_tx_desc(struct ural_softc *sc, struct ural_tx_desc *desc,
622 struct ieee80211com *ic = &sc->sc_ic;
667 struct ural_softc *sc = (struct ural_softc *)ic;
682 if (!RAL_IS_RUNNING(sc)) {
687 mutex_enter(&sc->tx_lock);
689 if (sc->tx_queued > RAL_TX_LIST_COUNT) {
694 sc->sc_need_sched = 1;
696 sc->sc_tx_nobuf++;
723 sc->sc_tx_err++;
736 sc->sc_tx_err++;
788 ural_setup_tx_desc(sc, desc, flags, pktlen, rate);
805 (void) ural_tx_trigger(sc, m);
819 mutex_exit(&sc->tx_lock);
827 struct ural_softc *sc = (struct ural_softc *)arg;
828 struct ieee80211com *ic = &sc->sc_ic;
857 ural_set_testmode(struct ural_softc *sc)
872 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, NULL,
884 ural_eeprom_read(struct ural_softc *sc, uint16_t addr, void *buf, int len)
900 err = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp,
918 ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val)
924 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY))
934 ural_write(sc, RAL_PHY_CSR7, tmp);
938 ural_bbp_read(struct ural_softc *sc, uint8_t reg)
944 ural_write(sc, RAL_PHY_CSR7, val);
947 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY))
955 return (ural_read(sc, RAL_PHY_CSR7) & 0xff);
959 ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val)
965 if (!(ural_read(sc, RAL_PHY_CSR10) & RAL_RF_LOBUSY))
975 ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff);
976 ural_write(sc, RAL_PHY_CSR10, tmp >> 16);
978 /* remember last written value in sc */
979 sc->rf_regs[reg] = val;
988 ural_disable_rf_tune(struct ural_softc *sc)
992 if (sc->rf_rev != RAL_RF_2523) {
993 tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE;
994 ural_rf_write(sc, RAL_RF1, tmp);
997 tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE;
998 ural_rf_write(sc, RAL_RF3, tmp);
1005 ural_set_chan(struct ural_softc *sc, struct ieee80211_channel *c)
1007 struct ieee80211com *ic = &sc->sc_ic;
1016 power = min(sc->txpow[chan - 1], 31);
1026 switch (sc->rf_rev) {
1028 ural_rf_write(sc, RAL_RF1, 0x00814);
1029 ural_rf_write(sc, RAL_RF2, ural_rf2522_r2[chan - 1]);
1030 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040);
1034 ural_rf_write(sc, RAL_RF1, 0x08804);
1035 ural_rf_write(sc, RAL_RF2, ural_rf2523_r2[chan - 1]);
1036 ural_rf_write(sc, RAL_RF3, power << 7 | 0x38044);
1037 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
1041 ural_rf_write(sc, RAL_RF1, 0x0c808);
1042 ural_rf_write(sc, RAL_RF2, ural_rf2524_r2[chan - 1]);
1043 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040);
1044 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
1048 ural_rf_write(sc, RAL_RF1, 0x08808);
1049 ural_rf_write(sc, RAL_RF2, ural_rf2525_hi_r2[chan - 1]);
1050 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
1051 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
1053 ural_rf_write(sc, RAL_RF1, 0x08808);
1054 ural_rf_write(sc, RAL_RF2, ural_rf2525_r2[chan - 1]);
1055 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
1056 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
1060 ural_rf_write(sc, RAL_RF1, 0x08808);
1061 ural_rf_write(sc, RAL_RF2, ural_rf2525e_r2[chan - 1]);
1062 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
1063 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282);
1067 ural_rf_write(sc, RAL_RF2, ural_rf2526_hi_r2[chan - 1]);
1068 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381);
1069 ural_rf_write(sc, RAL_RF1, 0x08804);
1071 ural_rf_write(sc, RAL_RF2, ural_rf2526_r2[chan - 1]);
1072 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
1073 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381);
1082 ural_rf_write(sc, RAL_RF1, ural_rf5222[i].r1);
1083 ural_rf_write(sc, RAL_RF2, ural_rf5222[i].r2);
1084 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040);
1085 ural_rf_write(sc, RAL_RF4, ural_rf5222[i].r4);
1092 tmp = ural_bbp_read(sc, 70);
1098 ural_bbp_write(sc, 70, tmp);
1101 (void) ural_read(sc, RAL_STA_CSR0);
1104 ural_disable_rf_tune(sc);
1113 ural_enable_tsf_sync(struct ural_softc *sc)
1115 struct ieee80211com *ic = &sc->sc_ic;
1119 ural_write(sc, RAL_TXRX_CSR19, 0);
1122 ural_write(sc, RAL_TXRX_CSR18, tmp);
1127 ural_write(sc, RAL_TXRX_CSR20, tmp);
1135 ural_write(sc, RAL_TXRX_CSR19, tmp);
1148 struct ural_softc *sc = (struct ural_softc *)ic;
1166 ural_write(sc, RAL_MAC_CSR10, slottime);
1167 ural_write(sc, RAL_MAC_CSR11, sifs);
1168 ural_write(sc, RAL_MAC_CSR12, eifs);
1172 ural_set_txpreamble(struct ural_softc *sc)
1176 tmp = ural_read(sc, RAL_TXRX_CSR10);
1179 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE)
1182 ural_write(sc, RAL_TXRX_CSR10, tmp);
1186 ural_set_basicrates(struct ural_softc *sc)
1188 struct ieee80211com *ic = &sc->sc_ic;
1193 ural_write(sc, RAL_TXRX_CSR11, 0x3);
1196 ural_write(sc, RAL_TXRX_CSR11, 0x150);
1199 ural_write(sc, RAL_TXRX_CSR11, 0x15f);
1204 ural_set_bssid(struct ural_softc *sc, uint8_t *bssid)
1209 ural_write(sc, RAL_MAC_CSR5, tmp);
1212 ural_write(sc, RAL_MAC_CSR6, tmp);
1215 ural_write(sc, RAL_MAC_CSR7, tmp);
1221 ural_set_macaddr(struct ural_softc *sc, uint8_t *addr)
1226 ural_write(sc, RAL_MAC_CSR2, tmp);
1229 ural_write(sc, RAL_MAC_CSR3, tmp);
1232 ural_write(sc, RAL_MAC_CSR4, tmp);
1239 ural_update_promisc(struct ural_softc *sc)
1243 tmp = ural_read(sc, RAL_TXRX_CSR2);
1246 if (!(sc->sc_rcr & RAL_RCR_PROMISC))
1249 ural_write(sc, RAL_TXRX_CSR2, tmp);
1252 (sc->sc_rcr & RAL_RCR_PROMISC) ? "entering" : "leaving");
1271 ural_read_eeprom(struct ural_softc *sc)
1273 struct ieee80211com *ic = &sc->sc_ic;
1276 ural_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2);
1278 sc->rf_rev = (val >> 11) & 0x7;
1279 sc->hw_radio = (val >> 10) & 0x1;
1280 sc->led_mode = (val >> 6) & 0x7;
1281 sc->rx_ant = (val >> 4) & 0x3;
1282 sc->tx_ant = (val >> 2) & 0x3;
1283 sc->nb_ant = val & 0x3;
1286 ural_eeprom_read(sc, RAL_EEPROM_ADDRESS, ic->ic_macaddr, 6);
1289 ural_eeprom_read(sc, RAL_EEPROM_BBP_BASE, sc->bbp_prom, 2 * 16);
1292 ural_eeprom_read(sc, RAL_EEPROM_TXPOWER, sc->txpow, 14);
1296 ural_bbp_init(struct ural_softc *sc)
1302 if (ural_bbp_read(sc, RAL_BBP_VERSION) != 0)
1313 ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val);
1319 ural_set_txantenna(struct ural_softc *sc, int antenna)
1324 tx = ural_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK;
1333 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526 ||
1334 sc->rf_rev == RAL_RF_5222)
1337 ural_bbp_write(sc, RAL_BBP_TX, tx);
1340 tmp = ural_read(sc, RAL_PHY_CSR5) & ~0x7;
1341 ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7));
1343 tmp = ural_read(sc, RAL_PHY_CSR6) & ~0x7;
1344 ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7));
1348 ural_set_rxantenna(struct ural_softc *sc, int antenna)
1352 rx = ural_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK;
1361 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526)
1364 ural_bbp_write(sc, RAL_BBP_RX, rx);
1374 struct ural_softc *sc = arg;
1375 struct ieee80211com *ic = &sc->sc_ic;
1384 struct ural_softc *sc = (struct ural_softc *)ic;
1389 RAL_LOCK(sc);
1393 if (sc->sc_scan_id != 0) {
1394 (void) untimeout(sc->sc_scan_id);
1395 sc->sc_scan_id = 0;
1398 if (sc->sc_amrr_id != 0) {
1399 (void) untimeout(sc->sc_amrr_id);
1400 sc->sc_amrr_id = 0;
1407 ural_write(sc, RAL_TXRX_CSR19, 0);
1409 ural_write(sc, RAL_MAC_CSR20, 0);
1414 ural_set_chan(sc, ic->ic_curchan);
1415 sc->sc_scan_id = timeout(ural_next_scan, (void *)sc,
1416 drv_usectohz(sc->dwelltime * 1000));
1420 ural_set_chan(sc, ic->ic_curchan);
1424 ural_set_chan(sc, ic->ic_curchan);
1428 ural_set_chan(sc, ic->ic_curchan);
1434 ural_set_txpreamble(sc);
1435 ural_set_basicrates(sc);
1436 ural_set_bssid(sc, ni->in_bssid);
1441 ural_write(sc, RAL_MAC_CSR20, 1);
1444 ural_enable_tsf_sync(sc);
1449 ural_amrr_start(sc, ni);
1454 RAL_UNLOCK(sc);
1456 err = sc->sc_newstate(ic, nstate, arg);
1469 ural_close_pipes(struct ural_softc *sc)
1473 if (sc->sc_rx_pipeh != NULL) {
1474 usb_pipe_reset(sc->sc_dev, sc->sc_rx_pipeh, flags, NULL, 0);
1475 usb_pipe_close(sc->sc_dev, sc->sc_rx_pipeh, flags, NULL, 0);
1476 sc->sc_rx_pipeh = NULL;
1479 if (sc->sc_tx_pipeh != NULL) {
1480 usb_pipe_reset(sc->sc_dev, sc->sc_tx_pipeh, flags, NULL, 0);
1481 usb_pipe_close(sc->sc_dev, sc->sc_tx_pipeh, flags, NULL, 0);
1482 sc->sc_tx_pipeh = NULL;
1487 ural_open_pipes(struct ural_softc *sc)
1493 ep_node = usb_lookup_ep_data(sc->sc_dev, sc->sc_udev, 0, 0, 0,
1499 if ((err = usb_pipe_open(sc->sc_dev,
1501 &sc->sc_tx_pipeh)) != USB_SUCCESS) {
1507 ep_node = usb_lookup_ep_data(sc->sc_dev, sc->sc_udev, 0, 0, 0,
1513 if ((err = usb_pipe_open(sc->sc_dev,
1515 &sc->sc_rx_pipeh)) != USB_SUCCESS) {
1524 if (sc->sc_rx_pipeh != NULL) {
1525 usb_pipe_close(sc->sc_dev, sc->sc_rx_pipeh,
1527 sc->sc_rx_pipeh = NULL;
1530 if (sc->sc_tx_pipeh != NULL) {
1531 usb_pipe_close(sc->sc_dev, sc->sc_tx_pipeh,
1533 sc->sc_tx_pipeh = NULL;
1540 ural_tx_trigger(struct ural_softc *sc, mblk_t *mp)
1545 sc->sc_tx_timer = RAL_TX_TIMEOUT;
1547 req = usb_alloc_bulk_req(sc->sc_dev, 0, USB_FLAGS_SLEEP);
1557 req->bulk_client_private = (usb_opaque_t)sc;
1565 if ((err = usb_pipe_bulk_xfer(sc->sc_tx_pipeh, req, 0))
1574 sc->tx_queued++;
1580 ural_rx_trigger(struct ural_softc *sc)
1585 req = usb_alloc_bulk_req(sc->sc_dev, RAL_RXBUF_SIZE, USB_FLAGS_SLEEP);
1593 req->bulk_client_private = (usb_opaque_t)sc;
1602 err = usb_pipe_bulk_xfer(sc->sc_rx_pipeh, req, 0);
1612 mutex_enter(&sc->rx_lock);
1613 sc->rx_queued++;
1614 mutex_exit(&sc->rx_lock);
1620 ural_init_tx_queue(struct ural_softc *sc)
1622 sc->tx_queued = 0;
1626 ural_init_rx_queue(struct ural_softc *sc)
1630 sc->rx_queued = 0;
1633 if (ural_rx_trigger(sc) != 0) {
1642 ural_stop(struct ural_softc *sc)
1644 struct ieee80211com *ic = &sc->sc_ic;
1649 RAL_LOCK(sc);
1651 sc->sc_tx_timer = 0;
1652 sc->sc_flags &= ~RAL_FLAG_RUNNING; /* STOP */
1655 ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX);
1658 ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP);
1659 ural_write(sc, RAL_MAC_CSR1, 0);
1661 ural_close_pipes(sc);
1663 RAL_UNLOCK(sc);
1667 ural_init(struct ural_softc *sc)
1669 struct ieee80211com *ic = &sc->sc_ic;
1673 ural_set_testmode(sc);
1674 ural_write(sc, 0x308, 0x00f0); /* magic */
1676 ural_stop(sc);
1680 ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val);
1684 tmp = ural_read(sc, RAL_MAC_CSR17);
1697 ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY);
1700 ural_write(sc, RAL_TXRX_CSR11, 0x15f);
1702 if (ural_bbp_init(sc) != 0)
1706 ural_set_chan(sc, ic->ic_curchan);
1709 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof (sc->sta));
1711 ural_set_txantenna(sc, sc->tx_ant);
1712 ural_set_rxantenna(sc, sc->rx_ant);
1714 ural_set_macaddr(sc, ic->ic_macaddr);
1716 if (ural_open_pipes(sc) != USB_SUCCESS) {
1722 ural_init_tx_queue(sc);
1724 if (ural_init_rx_queue(sc) != USB_SUCCESS)
1733 if (!(sc->sc_rcr & RAL_RCR_PROMISC))
1736 ural_write(sc, RAL_TXRX_CSR2, tmp);
1737 sc->sc_flags |= RAL_FLAG_RUNNING; /* RUNNING */
1741 ural_stop(sc);
1748 struct ural_softc *sc;
1755 sc = ddi_get_soft_state(ural_soft_state_p, ddi_get_instance(devinfo));
1756 ASSERT(sc != NULL);
1758 if (!RAL_IS_RUNNING(sc)) /* different device or not inited */
1761 ic = &sc->sc_ic;
1765 RAL_LOCK(sc);
1767 sc->sc_tx_timer = 0;
1768 sc->sc_flags &= ~RAL_FLAG_RUNNING; /* STOP */
1770 ural_close_pipes(sc);
1772 RAL_UNLOCK(sc);
1780 struct ural_softc *sc;
1783 sc = ddi_get_soft_state(ural_soft_state_p, ddi_get_instance(devinfo));
1784 ASSERT(sc != NULL);
1787 if (usb_check_same_device(sc->sc_dev, NULL, USB_LOG_L2, -1,
1793 err = ural_init(sc);
1799 ural_resume(struct ural_softc *sc)
1802 if (usb_check_same_device(sc->sc_dev, NULL, USB_LOG_L2, -1,
1808 (void) ural_init(sc);
1887 struct ural_softc *sc = (struct ural_softc *)arg;
1888 struct ural_amrr *amrr = &sc->amrr;
1890 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof (sc->sta));
1893 sc->sc_tx_err += sc->sta[9];
1894 sc->sc_tx_retries += (sc->sta[7] + sc->sta[8]);
1897 sc->sta[7] + /* TX one-retry ok count */
1898 sc->sta[8] + /* TX more-retry ok count */
1899 sc->sta[9]; /* TX retry-fail count */
1903 sc->sta[6]; /* TX no-retry ok count */
1905 ural_ratectl(amrr, sc->sc_ic.ic_bss);
1907 sc->sc_amrr_id = timeout(ural_amrr_timeout, (void *)sc,
1913 ural_amrr_start(struct ural_softc *sc, struct ieee80211_node *ni)
1915 struct ural_amrr *amrr = &sc->amrr;
1919 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof (sc->sta));
1934 sc->sc_amrr_id = timeout(ural_amrr_timeout, (void *)sc,
1941 struct ural_softc *sc = arg;
1942 struct ieee80211com *ic = &sc->sc_ic;
1945 RAL_LOCK(sc);
1948 if (!RAL_IS_RUNNING(sc)) {
1949 RAL_UNLOCK(sc);
1953 if (sc->sc_tx_timer > 0) {
1954 if (--sc->sc_tx_timer == 0) {
1956 RAL_UNLOCK(sc);
1957 (void) ural_init(sc);
1966 RAL_UNLOCK(sc);
1977 struct ural_softc *sc = (struct ural_softc *)arg;
1983 err = ural_init(sc);
1988 sc->sc_flags |= RAL_FLAG_RUNNING; /* RUNNING */
1992 ural_stop(sc);
1999 struct ural_softc *sc = (struct ural_softc *)arg;
2001 (void) ural_stop(sc);
2002 sc->sc_flags &= ~RAL_FLAG_RUNNING; /* STOP */
2008 struct ural_softc *sc = (struct ural_softc *)arg;
2009 struct ieee80211com *ic = &sc->sc_ic;
2015 (void) ural_set_macaddr(sc, (uint8_t *)macaddr);
2016 (void) ural_init(sc);
2031 struct ural_softc *sc = (struct ural_softc *)arg;
2034 sc->sc_rcr |= RAL_RCR_PROMISC;
2035 sc->sc_rcr |= RAL_RCR_MULTI;
2037 sc->sc_rcr &= ~RAL_RCR_PROMISC;
2038 sc->sc_rcr &= ~RAL_RCR_PROMISC;
2041 ural_update_promisc(sc);
2052 struct ural_softc *sc = (struct ural_softc *)arg;
2053 struct ieee80211com *ic = &sc->sc_ic;
2058 RAL_LOCK(sc);
2060 if (RAL_IS_RUNNING(sc)) {
2061 RAL_UNLOCK(sc);
2062 (void) ural_init(sc);
2064 RAL_LOCK(sc);
2068 RAL_UNLOCK(sc);
2077 struct ural_softc *sc = (struct ural_softc *)arg;
2080 err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num,
2090 struct ural_softc *sc = (struct ural_softc *)arg;
2092 ieee80211_propinfo(&sc->sc_ic, pr_name, wldp_pr_num, mph);
2098 struct ural_softc *sc = (struct ural_softc *)arg;
2099 struct ieee80211com *ic = &sc->sc_ic;
2103 RAL_LOCK(sc);
2105 if (RAL_IS_RUNNING(sc)) {
2106 RAL_UNLOCK(sc);
2107 (void) ural_init(sc);
2109 RAL_LOCK(sc);
2112 RAL_UNLOCK(sc);
2118 struct ural_softc *sc = (struct ural_softc *)arg;
2119 ieee80211com_t *ic = &sc->sc_ic;
2123 RAL_LOCK(sc);
2131 *val = sc->sc_tx_nobuf;
2134 *val = sc->sc_rx_nobuf;
2137 *val = sc->sc_rx_err;
2153 *val = sc->sc_tx_err;
2156 *val = sc->sc_tx_retries;
2168 RAL_UNLOCK(sc);
2171 RAL_UNLOCK(sc);
2174 RAL_UNLOCK(sc);
2183 struct ural_softc *sc;
2197 sc = ddi_get_soft_state(ural_soft_state_p,
2199 ASSERT(sc != NULL);
2200 ural_resume(sc);
2214 sc = ddi_get_soft_state(ural_soft_state_p, instance);
2215 ic = (ieee80211com_t *)&sc->sc_ic;
2216 sc->sc_dev = devinfo;
2224 if (usb_get_dev_data(devinfo, &sc->sc_udev,
2226 sc->sc_udev = NULL;
2230 mutex_init(&sc->sc_genlock, NULL, MUTEX_DRIVER, NULL);
2231 mutex_init(&sc->tx_lock, NULL, MUTEX_DRIVER, NULL);
2232 mutex_init(&sc->rx_lock, NULL, MUTEX_DRIVER, NULL);
2235 sc->asic_rev = ural_read(sc, RAL_MAC_CSR0);
2238 ural_read_eeprom(sc);
2241 sc->asic_rev, ural_get_rf(sc->rf_rev));
2262 if (sc->rf_rev == RAL_RF_5222) {
2304 sc->sc_newstate = ic->ic_newstate;
2310 sc->sc_rcr = 0;
2311 sc->dwelltime = 300;
2312 sc->sc_flags &= 0;
2329 macp->m_driver = sc;
2373 mutex_destroy(&sc->sc_genlock);
2374 mutex_destroy(&sc->tx_lock);
2375 mutex_destroy(&sc->rx_lock);
2377 usb_client_detach(sc->sc_dev, sc->sc_udev);
2387 struct ural_softc *sc;
2389 sc = ddi_get_soft_state(ural_soft_state_p, ddi_get_instance(devinfo));
2390 ASSERT(sc != NULL);
2396 if (RAL_IS_RUNNING(sc))
2397 (void) ural_stop(sc);
2403 if (mac_disable(sc->sc_ic.ic_mach) != 0)
2406 ural_stop(sc);
2412 (void) mac_unregister(sc->sc_ic.ic_mach);
2417 ieee80211_detach(&sc->sc_ic);
2419 mutex_destroy(&sc->sc_genlock);
2420 mutex_destroy(&sc->tx_lock);
2421 mutex_destroy(&sc->rx_lock);
2424 usb_client_detach(devinfo, sc->sc_udev);
2425 sc->sc_udev = NULL;