Lines Matching defs:sc
424 mwl_alloc_cmdbuf(struct mwl_softc *sc)
431 err = mwl_alloc_dma_mem(sc->sc_dev, &mwl_dma_attr, size,
434 &sc->sc_cmd_dma);
441 sc->sc_cmd_mem = (uint16_t *)sc->sc_cmd_dma.mem_va;
442 sc->sc_cmd_dmaaddr = sc->sc_cmd_dma.cookie.dmac_address;
448 mwl_free_cmdbuf(struct mwl_softc *sc)
450 if (sc->sc_cmd_mem != NULL)
451 mwl_free_dma_mem(&sc->sc_cmd_dma);
455 mwl_alloc_rx_ring(struct mwl_softc *sc, int count)
462 ring = &sc->sc_rxring;
465 err = mwl_alloc_dma_mem(sc->sc_dev, &mwl_dma_attr,
499 (void) mwl_alloc_dma_mem(sc->sc_dev, &mwl_dma_attr,
500 sc->sc_dmabuf_size,
520 mwl_free_rx_ring(struct mwl_softc *sc)
526 ring = &sc->sc_rxring;
543 mwl_alloc_tx_ring(struct mwl_softc *sc, struct mwl_tx_ring *ring,
553 err = mwl_alloc_dma_mem(sc->sc_dev, &mwl_dma_attr,
583 (void) mwl_alloc_dma_mem(sc->sc_dev, &mwl_dma_attr,
584 sc->sc_dmabuf_size,
605 mwl_free_tx_ring(struct mwl_softc *sc, struct mwl_tx_ring *ring)
630 mwl_hal_sethwdma(struct mwl_softc *sc, const struct mwl_hal_txrxdma *dma)
653 if (sc->sc_revs.mh_macRev < 5)
656 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_HW_SPEC);
659 sc->sc_hw_flags &= ~MHF_MBSS;
661 sc->sc_hw_flags |= MHF_MBSS;
674 mwl_setupdma(struct mwl_softc *sc)
678 sc->sc_hwdma.rxDescRead = sc->sc_rxring.physaddr;
679 mwl_mem_write4(sc, sc->sc_hwspecs.rxDescRead, sc->sc_hwdma.rxDescRead);
680 mwl_mem_write4(sc, sc->sc_hwspecs.rxDescWrite, sc->sc_hwdma.rxDescRead);
683 struct mwl_tx_ring *txring = &sc->sc_txring[i];
684 sc->sc_hwdma.wcbBase[i] = txring->physaddr;
685 mwl_mem_write4(sc, sc->sc_hwspecs.wcbBase[i],
686 sc->sc_hwdma.wcbBase[i]);
688 sc->sc_hwdma.maxNumTxWcb = MWL_TX_RING_COUNT;
689 sc->sc_hwdma.maxNumWCB = MWL_NUM_TX_QUEUES - MWL_NUM_ACK_QUEUES;
691 err = mwl_hal_sethwdma(sc, &sc->sc_hwdma);
703 mwl_txq_init(struct mwl_softc *sc, struct mwl_tx_ring *txring, int qnum)
729 mwl_tx_setup(struct mwl_softc *sc, int ac, int mvtype)
734 if (ac >= N(sc->sc_ac2q)) {
737 ac, (uint_t)N(sc->sc_ac2q));
746 txring = &sc->sc_txring[mvtype];
747 mwl_txq_init(sc, txring, mvtype);
748 sc->sc_ac2q[ac] = txring;
754 mwl_setup_txq(struct mwl_softc *sc)
759 if (!mwl_tx_setup(sc, WME_AC_BK, MWL_WME_AC_BK)) {
766 if (!mwl_tx_setup(sc, WME_AC_BE, MWL_WME_AC_BE) ||
767 !mwl_tx_setup(sc, WME_AC_VI, MWL_WME_AC_VI) ||
768 !mwl_tx_setup(sc, WME_AC_VO, MWL_WME_AC_VO)) {
776 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK];
777 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK];
778 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK];
822 mwlFwReset(struct mwl_softc *sc)
824 if (mwl_ctl_read4(sc, MACREG_REG_INT_CODE) == 0xffffffff) {
830 mwl_ctl_write4(sc, MACREG_REG_H2A_INTERRUPT_EVENTS, ISR_RESET);
831 sc->sc_hw_flags &= ~MHF_FWHANG;
835 mwlPokeSdramController(struct mwl_softc *sc, int SDRAMSIZE_Addr)
838 mwl_ctl_write4(sc, 0x00006014, 0x33);
839 mwl_ctl_write4(sc, 0x00006018, 0xa3a2632);
840 mwl_ctl_write4(sc, 0x00006010, SDRAMSIZE_Addr);
844 mwlTriggerPciCmd(struct mwl_softc *sc)
846 (void) ddi_dma_sync(sc->sc_cmd_dma.dma_hdl,
848 sc->sc_cmd_dma.alength,
851 mwl_ctl_write4(sc, MACREG_REG_GEN_PTR, sc->sc_cmd_dmaaddr);
852 (void) mwl_ctl_read4(sc, MACREG_REG_INT_CODE);
854 mwl_ctl_write4(sc, MACREG_REG_INT_CODE, 0x00);
855 (void) mwl_ctl_read4(sc, MACREG_REG_INT_CODE);
857 mwl_ctl_write4(sc, MACREG_REG_H2A_INTERRUPT_EVENTS,
859 (void) mwl_ctl_read4(sc, MACREG_REG_INT_CODE);
863 mwlWaitFor(struct mwl_softc *sc, uint32_t val)
869 if (mwl_ctl_read4(sc, MACREG_REG_INT_CODE) == val)
879 mwlSendBlock(struct mwl_softc *sc, int bsize, const void *data, size_t dsize)
881 sc->sc_cmd_mem[0] = LE_16(HostCmd_CMD_CODE_DNLD);
882 sc->sc_cmd_mem[1] = LE_16(bsize);
883 (void) memcpy(&sc->sc_cmd_mem[4], data, dsize);
884 mwlTriggerPciCmd(sc);
886 if (mwlWaitFor(sc, MACREG_INT_CODE_CMD_FINISHED)) {
887 mwl_ctl_write4(sc, MACREG_REG_INT_CODE, 0);
893 mwl_ctl_read4(sc, MACREG_REG_INT_CODE));
901 mwlSendBlock2(struct mwl_softc *sc, const void *data, size_t dsize)
903 (void) memcpy(&sc->sc_cmd_mem[0], data, dsize);
904 mwlTriggerPciCmd(sc);
905 if (mwlWaitFor(sc, MACREG_INT_CODE_CMD_FINISHED)) {
906 mwl_ctl_write4(sc, MACREG_REG_INT_CODE, 0);
912 mwl_ctl_read4(sc, MACREG_REG_INT_CODE));
918 mwl_fwload(struct mwl_softc *sc, void *fwargs)
1006 mwlFwReset(sc);
1008 mwl_ctl_write4(sc, MACREG_REG_A2H_INTERRUPT_CLEAR_SEL,
1010 mwl_ctl_write4(sc, MACREG_REG_A2H_INTERRUPT_CAUSE, 0x00);
1011 mwl_ctl_write4(sc, MACREG_REG_A2H_INTERRUPT_MASK, 0x00);
1012 mwl_ctl_write4(sc, MACREG_REG_A2H_INTERRUPT_STATUS_MASK,
1014 if (sc->sc_SDRAMSIZE_Addr != 0) {
1016 mwlPokeSdramController(sc, sc->sc_SDRAMSIZE_Addr);
1034 if (!mwlSendBlock(sc, fwboot_size, fwboot, fwboot_size) ||
1035 !mwlSendBlock(sc, 0, NULL, 0)) {
1040 if (sc->sc_SDRAMSIZE_Addr != 0) {
1042 mwlPokeSdramController(sc, sc->sc_SDRAMSIZE_Addr);
1046 mwl_ctl_write4(sc, MACREG_REG_INT_CODE, 0);
1047 blocksize = mwl_ctl_read4(sc, MACREG_REG_SCRATCH);
1075 if (!mwlSendBlock2(sc, fp, nbytes)) {
1085 if (!mwlSendBlock(sc, FW_DOWNLOAD_BLOCK_SIZE, fp,
1099 sc->sc_cmd_mem[1] = 0;
1104 mwlTriggerPciCmd(sc);
1106 mwl_ctl_write4(sc, MACREG_REG_GEN_PTR, OpMode);
1108 if (mwl_ctl_read4(sc, MACREG_REG_INT_CODE) ==
1110 mwl_ctl_write4(sc, MACREG_REG_INT_CODE, 0x00);
1111 return (mwlResetHalState(sc));
1118 mwlFwReset(sc);
1135 mwlSendCmd(struct mwl_softc *sc)
1137 (void) ddi_dma_sync(sc->sc_cmd_dma.dma_hdl,
1139 sc->sc_cmd_dma.alength,
1142 mwl_ctl_write4(sc, MACREG_REG_GEN_PTR, sc->sc_cmd_dmaaddr);
1143 (void) mwl_ctl_read4(sc, MACREG_REG_INT_CODE);
1145 mwl_ctl_write4(sc, MACREG_REG_H2A_INTERRUPT_EVENTS,
1150 mwlExecuteCmd(struct mwl_softc *sc, unsigned short cmd)
1152 if (mwl_ctl_read4(sc, MACREG_REG_INT_CODE) == 0xffffffff) {
1157 mwlSendCmd(sc);
1158 if (!mwlWaitForCmdComplete(sc, 0x8000 | cmd)) {
1163 (void) ddi_dma_sync(sc->sc_cmd_dma.dma_hdl,
1165 sc->sc_cmd_dma.alength,
1172 dumpresult(sc, 1);
1178 mwlWaitForCmdComplete(struct mwl_softc *sc, uint16_t cmdCode)
1184 if (sc->sc_cmd_mem[0] == LE_16(cmdCode))
1253 dumpresult(struct mwl_softc *sc, int showresult)
1255 const FWCmdHdr *h = (const FWCmdHdr *)sc->sc_cmd_mem;
1284 mwlGetCalTable(struct mwl_softc *sc, uint8_t annex, uint8_t index)
1294 retval = mwlExecuteCmd(sc, HostCmd_CMD_GET_CALTABLE);
1389 mwlGetPwrCalTable(struct mwl_softc *sc)
1396 data = ((const HostCmd_FW_GET_CALTABLE *) sc->sc_cmd_mem)->calTbl;
1397 if (mwlGetCalTable(sc, 33, 0) == 0) {
1402 get2Ghz(&sc->sc_20M, &data[12], len);
1404 if (mwlGetCalTable(sc, 34, 0) == 0) {
1409 ci = &sc->sc_40M;
1412 if (mwlGetCalTable(sc, 35, 0) == 0) {
1417 get5Ghz(&sc->sc_20M_5G, &data[20], len);
1419 if (mwlGetCalTable(sc, 36, 0) == 0) {
1424 ci = &sc->sc_40M_5G;
1427 sc->sc_hw_flags |= MHF_CALDATA;
1435 mwlResetHalState(struct mwl_softc *sc)
1444 if ((sc->sc_hw_flags & MHF_CALDATA) == 0)
1445 err = mwlGetPwrCalTable(sc);
1565 mwl_hal_getchannelinfo(struct mwl_softc *sc, int band, int chw,
1570 *ci = (chw == MWL_CH_20_MHz_WIDTH) ? &sc->sc_20M : &sc->sc_40M;
1574 &sc->sc_20M_5G : &sc->sc_40M_5G;
1583 getchannels(struct mwl_softc *sc, int maxchans, int *nchans,
1595 if (mwl_hal_getchannelinfo(sc,
1598 if (mwl_hal_getchannelinfo(sc,
1601 if (mwl_hal_getchannelinfo(sc,
1605 if (mwl_hal_getchannelinfo(sc,
1612 mwl_getchannels(struct mwl_softc *sc)
1619 (void) memset(sc->sc_channels, 0, sizeof (sc->sc_channels));
1620 sc->sc_nchans = 0;
1621 getchannels(sc, IEEE80211_CHAN_MAX, &sc->sc_nchans, sc->sc_channels);
1623 sc->sc_regdomain.regdomain = SKU_DEBUG;
1624 sc->sc_regdomain.country = CTRY_DEFAULT;
1625 sc->sc_regdomain.location = 'I';
1626 sc->sc_regdomain.isocc[0] = ' '; /* XXX? */
1627 sc->sc_regdomain.isocc[1] = ' ';
1628 return (sc->sc_nchans == 0 ? EIO : 0);
1641 mwl_gethwspecs(struct mwl_softc *sc)
1647 hw = &sc->sc_hwspecs;
1650 pCmd->ulFwAwakeCookie = LE_32((unsigned int)sc->sc_cmd_dmaaddr + 2048);
1652 retval = mwlExecuteCmd(sc, HostCmd_CMD_GET_HW_SPEC);
1669 sc->sc_revs.mh_macRev = hw->hwVersion; /* XXX */
1670 sc->sc_revs.mh_phyRev = hw->hostInterface; /* XXX */
1677 mwl_hal_setmac_locked(struct mwl_softc *sc,
1688 return (mwlExecuteCmd(sc, HostCmd_CMD_SET_MAC_ADDR));
1707 mwl_hal_newstation(struct mwl_softc *sc,
1730 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_NEW_STN);
1741 mwl_hal_setantenna(struct mwl_softc *sc, MWL_HAL_ANTENNA dirSet, int ant)
1756 retval = mwlExecuteCmd(sc, HostCmd_CMD_802_11_RF_ANTENNA);
1766 mwl_hal_setradio(struct mwl_softc *sc, int onoff, MWL_HAL_PREAMBLE preamble)
1780 retval = mwlExecuteCmd(sc, HostCmd_CMD_802_11_RADIO_CONTROL);
1785 mwl_hal_setwmm(struct mwl_softc *sc, int onoff)
1794 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_WMM_MODE);
1841 mwl_hal_setchannel(struct mwl_softc *sc, const MWL_HAL_CHANNEL *chan)
1851 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_RF_CHANNEL);
1856 mwl_hal_settxpower(struct mwl_softc *sc,
1863 hc = findhalchannel(sc, c);
1885 retval = mwlExecuteCmd(sc, HostCmd_CMD_802_11_RF_TX_POWER);
1893 mwl_hal_settxrate(struct mwl_softc *sc, MWL_HAL_TXRATE_HANDLING handling,
1939 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_FIXED_RATE);
1944 mwl_hal_settxrate_auto(struct mwl_softc *sc, const MWL_HAL_TXRATE *rate)
1959 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_FIXED_RATE);
1968 mwl_hal_setrateadaptmode(struct mwl_softc *sc, uint16_t mode)
1978 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_RATE_ADAPT_MODE);
1983 mwl_hal_setoptimizationlevel(struct mwl_softc *sc, int level)
1992 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_OPTIMIZATION_LEVEL);
2000 mwl_hal_setregioncode(struct mwl_softc *sc, int regionCode)
2017 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_REGION_CODE);
2022 mwl_hal_setassocid(struct mwl_softc *sc,
2025 HostCmd_FW_SET_AID *pCmd = (HostCmd_FW_SET_AID *) &sc->sc_cmd_mem[0];
2032 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_AID);
2043 struct mwl_softc *sc = (struct mwl_softc *)ic;
2059 return (mwl_hal_settxrate(sc, RATE_AUTO, &rates));
2068 mwl_hal_setrtsthreshold(struct mwl_softc *sc, int threshold)
2078 retval = mwlExecuteCmd(sc, HostCmd_CMD_802_11_RTS_THSD);
2083 mwl_hal_setcsmode(struct mwl_softc *sc, MWL_HAL_CSMODE csmode)
2093 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_LINKADAPT_CS_MODE);
2098 mwl_hal_setpromisc(struct mwl_softc *sc, int ena)
2102 v = mwl_ctl_read4(sc, MACREG_REG_PROMISCUOUS);
2103 mwl_ctl_write4(sc, MACREG_REG_PROMISCUOUS, ena ? v | 1 : v & ~1);
2109 mwl_hal_start(struct mwl_softc *sc)
2117 retval = mwlExecuteCmd(sc, HostCmd_CMD_BSS_START);
2125 mwl_hal_setinframode(struct mwl_softc *sc)
2133 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_INFRA_MODE);
2138 mwl_hal_stop(struct mwl_softc *sc)
2146 retval = mwlExecuteCmd(sc, HostCmd_CMD_BSS_START);
2152 mwl_hal_keyset(struct mwl_softc *sc, const MWL_HAL_KEYVAL *kv,
2195 retval = mwlExecuteCmd(sc, HostCmd_CMD_UPDATE_ENCRYPTION);
2200 mwl_hal_keyreset(struct mwl_softc *sc, const MWL_HAL_KEYVAL *kv,
2218 retval = mwlExecuteCmd(sc, HostCmd_CMD_UPDATE_ENCRYPTION);
2246 // delstaid(sc, mn->mn_staid);
2294 struct mwl_softc *sc = (struct mwl_softc *)ic;
2317 return (mwl_hal_keyreset(sc, &hk, bcastaddr) == 0);
2334 struct mwl_softc *sc = (struct mwl_softc *)ic;
2396 (void) mwl_hal_keyset(sc, &hk, ic->ic_macaddr);
2398 return (mwl_hal_keyset(sc, &hk, macaddr) == 0);
2446 mwl_chan_set(struct mwl_softc *sc, struct mwl_channel *chan)
2461 mwl_hal_intrset(sc, 0); /* disable interrupts */
2463 (void) mwl_hal_setchannel(sc, &hchan);
2474 (void) mwl_hal_settxpower(sc, &hchan, maxtxpow / 2);
2476 (void) mwl_setcurchanrates(sc);
2478 sc->sc_curchan = hchan;
2479 mwl_hal_intrset(sc, sc->sc_imask);
2560 mwl_setcurchanrates(struct mwl_softc *sc)
2562 struct ieee80211com *ic = &sc->sc_ic;
2567 rs = mwl_get_suprates(ic, sc->sc_cur_chan);
2573 return (mwl_hal_settxrate_auto(sc, &rates));
2577 findhalchannel(const struct mwl_softc *sc, const MWL_HAL_CHANNEL *c)
2586 ci = &sc->sc_40M;
2591 ci = &sc->sc_20M;
2596 ci = &sc->sc_40M_5G;
2601 ci = &sc->sc_20M_5G;
2651 mwl_startrecv(struct mwl_softc *sc)
2659 ring = &sc->sc_rxring;
2701 (void) mwl_mode_init(sc);
2707 mwl_mode_init(struct mwl_softc *sc)
2716 (void) mwl_hal_setpromisc(sc, 0);
2728 mwl_hal_txstart(struct mwl_softc *sc, int qnum)
2731 mwl_ctl_write4(sc, MACREG_REG_H2A_INTERRUPT_EVENTS,
2733 (void) mwl_ctl_read4(sc, MACREG_REG_INT_CODE);
2739 struct mwl_softc *sc = (struct mwl_softc *)ic;
2752 MWL_TXLOCK(sc);
2755 if (!MWL_IS_RUNNING(sc) || MWL_IS_SUSPEND(sc)) {
2760 ring = &sc->sc_txring[1];
2764 sc->sc_need_sched = 1;
2765 sc->sc_tx_nobuf++;
2789 sc->sc_tx_err++;
2803 sc->sc_tx_err++;
2887 mwl_hal_txstart(sc, 0);
2900 MWL_TXUNLOCK(sc);
2911 struct mwl_softc *sc = (struct mwl_softc *)arg;
2912 struct ieee80211com *ic = &sc->sc_ic;
2917 sc->sc_scan_id = 0;
2965 struct mwl_softc *sc = (struct mwl_softc *)ic;
2972 if (sc->sc_scan_id != 0) {
2973 (void) untimeout(sc->sc_scan_id);
2974 sc->sc_scan_id = 0;
2977 MWL_GLOCK(sc);
2992 sc->sc_cur_chan =
2993 &sc->sc_channels[3 * chan - 2];
2995 "chan num is %u, sc chan is %u\n",
2996 chan, sc->sc_cur_chan->ic_ieee);
2997 (void) mwl_chan_set(sc, sc->sc_cur_chan);
3000 sc->sc_scan_id = timeout(mwl_next_scan, (void *)sc,
3006 sc->sc_cur_chan = &sc->sc_channels[3 * chan - 2];
3008 "chan num is %u, sc chan is %u\n",
3009 chan, sc->sc_cur_chan->ic_ieee);
3010 (void) mwl_chan_set(sc, sc->sc_cur_chan);
3012 (void) mwl_hal_newstation(sc, ic->ic_macaddr, 0, 0, NULL, 0, 0);
3019 (void) mwl_hal_newstation(sc,
3022 (void) mwl_hal_setassocid(sc,
3025 (void) mwl_hal_setrtsthreshold(sc, ic->ic_rtsthreshold);
3026 (void) mwl_hal_setcsmode(sc, CSMODE_AUTO_ENA);
3032 MWL_GUNLOCK(sc);
3034 return (sc->sc_newstate(ic, nstate, arg));
3041 mwl_hal_intrset(struct mwl_softc *sc, uint32_t mask)
3043 mwl_ctl_write4(sc, MACREG_REG_A2H_INTERRUPT_MASK, 0);
3044 (void) mwl_ctl_read4(sc, MACREG_REG_INT_CODE);
3046 sc->sc_hal_imask = mask;
3047 mwl_ctl_write4(sc, MACREG_REG_A2H_INTERRUPT_MASK, mask);
3048 (void) mwl_ctl_read4(sc, MACREG_REG_INT_CODE);
3055 mwl_hal_getisr(struct mwl_softc *sc, uint32_t *status)
3059 cause = mwl_ctl_read4(sc, MACREG_REG_A2H_INTERRUPT_CAUSE);
3064 mwl_ctl_write4(sc, MACREG_REG_A2H_INTERRUPT_CAUSE,
3065 cause & ~sc->sc_hal_imask);
3066 (void) mwl_ctl_read4(sc, MACREG_REG_INT_CODE);
3067 cause &= sc->sc_hal_imask;
3073 mwl_tx_intr(struct mwl_softc *sc)
3075 struct ieee80211com *ic = &sc->sc_ic;
3081 MWL_TXLOCK(sc);
3083 ring = &sc->sc_txring[1];
3086 MWL_TXUNLOCK(sc);
3130 if (sc->sc_need_sched &&
3132 sc->sc_need_sched = 0;
3138 MWL_TXUNLOCK(sc);
3161 mwl_rx_intr(struct mwl_softc *sc)
3163 struct ieee80211com *ic = &sc->sc_ic;
3175 MWL_RXLOCK(sc);
3177 ring = &sc->sc_rxring;
3195 sc->sc_rx_err++;
3208 if (len < 32 || len > sc->sc_dmabuf_size) {
3211 sc->sc_rx_err++;
3215 mp0 = allocb(sc->sc_dmabuf_size, BPRI_MED);
3219 sc->sc_rx_nobuf++;
3281 MWL_RXUNLOCK(sc);
3288 struct mwl_softc *sc = (struct mwl_softc *)data;
3294 MWL_GLOCK(sc);
3295 if (sc->sc_rx_pend) {
3296 sc->sc_rx_pend = 0;
3297 MWL_GUNLOCK(sc);
3298 mwl_rx_intr(sc);
3301 MWL_GUNLOCK(sc);
3310 struct mwl_softc *sc = (struct mwl_softc *)arg;
3313 MWL_GLOCK(sc);
3315 if (!MWL_IS_RUNNING(sc) || MWL_IS_SUSPEND(sc)) {
3316 MWL_GUNLOCK(sc);
3323 mwl_hal_getisr(sc, &status); /* NB: clears ISR too */
3325 MWL_GUNLOCK(sc);
3330 sc->sc_rx_pend = 1;
3331 (void) ddi_intr_trigger_softint(sc->sc_softintr_hdl, NULL);
3334 mwl_tx_intr(sc);
3369 MWL_GUNLOCK(sc);
3375 mwl_init(struct mwl_softc *sc)
3377 struct ieee80211com *ic = &sc->sc_ic;
3380 mwl_hal_intrset(sc, 0);
3382 sc->sc_txantenna = 0; /* h/w default */
3383 sc->sc_rxantenna = 0; /* h/w default */
3385 err = mwl_hal_setantenna(sc, WL_ANTENNATYPE_RX, sc->sc_rxantenna);
3392 err = mwl_hal_setantenna(sc, WL_ANTENNATYPE_TX, sc->sc_txantenna);
3399 err = mwl_hal_setradio(sc, 1, WL_AUTO_PREAMBLE);
3406 err = mwl_hal_setwmm(sc, (ic->ic_flags & IEEE80211_F_WME) != 0);
3416 sc->sc_cur_chan = &sc->sc_channels[1];
3418 err = mwl_chan_set(sc, sc->sc_cur_chan);
3425 err = mwl_hal_setrateadaptmode(sc, 0);
3432 err = mwl_hal_setoptimizationlevel(sc,
3440 err = mwl_hal_setregioncode(sc, mwl_map2regioncode(&sc->sc_regdomain));
3447 err = mwl_startrecv(sc);
3457 sc->sc_imask = MACREG_A2HRIC_BIT_RX_RDY
3466 mwl_hal_intrset(sc, sc->sc_imask);
3468 err = mwl_hal_start(sc);
3475 err = mwl_hal_setinframode(sc);
3487 mwl_resume(struct mwl_softc *sc)
3491 err = mwl_fwload(sc, NULL);
3498 err = mwl_gethwspecs(sc);
3505 err = mwl_alloc_rx_ring(sc, MWL_RX_RING_COUNT);
3513 err = mwl_alloc_tx_ring(sc,
3514 &sc->sc_txring[qid], MWL_TX_RING_COUNT);
3522 err = mwl_setupdma(sc);
3529 err = mwl_setup_txq(sc);
3541 mwl_stop(struct mwl_softc *sc)
3546 if (!MWL_IS_QUIESCE(sc))
3547 MWL_GLOCK(sc);
3549 err = mwl_hal_stop(sc);
3556 if (!MWL_IS_QUIESCE(sc))
3557 MWL_GUNLOCK(sc);
3563 struct mwl_softc *sc = (struct mwl_softc *)arg;
3564 struct ieee80211com *ic = &sc->sc_ic;
3568 MWL_GLOCK(sc);
3578 *val = sc->sc_tx_nobuf;
3581 *val = sc->sc_rx_nobuf;
3584 *val = sc->sc_rx_err;
3600 *val = sc->sc_tx_err;
3603 *val = sc->sc_tx_retries;
3615 MWL_GUNLOCK(sc);
3618 MWL_GUNLOCK(sc);
3622 MWL_GUNLOCK(sc);
3629 struct mwl_softc *sc = (struct mwl_softc *)arg;
3630 struct ieee80211com *ic = &sc->sc_ic;
3633 err = mwl_init(sc);
3642 MWL_GLOCK(sc);
3643 sc->sc_flags |= MWL_F_RUNNING;
3644 MWL_GUNLOCK(sc);
3648 mwl_stop(sc);
3655 struct mwl_softc *sc = (struct mwl_softc *)arg;
3657 mwl_stop(sc);
3659 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1);
3661 MWL_GLOCK(sc);
3662 sc->sc_flags &= ~MWL_F_RUNNING;
3663 MWL_GUNLOCK(sc);
3670 struct mwl_softc *sc = (struct mwl_softc *)arg;
3673 err = mwl_hal_setpromisc(sc, on);
3695 struct mwl_softc *sc = (struct mwl_softc *)arg;
3696 struct ieee80211com *ic = &sc->sc_ic;
3699 if (MWL_IS_SUSPEND(sc)) {
3732 struct mwl_softc *sc = (struct mwl_softc *)arg;
3733 struct ieee80211com *ic = &sc->sc_ic;
3739 if (MWL_IS_RUNNING(sc)) {
3740 (void) mwl_init(sc);
3755 struct mwl_softc *sc = (struct mwl_softc *)arg;
3758 err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num,
3768 struct mwl_softc *sc = (struct mwl_softc *)arg;
3770 ieee80211_propinfo(&sc->sc_ic, pr_name, wldp_pr_num, prh);
3777 struct mwl_softc *sc = (struct mwl_softc *)arg;
3778 ieee80211com_t *ic = &sc->sc_ic;
3785 if (MWL_IS_RUNNING(sc)) {
3786 (void) mwl_init(sc);
3799 struct mwl_softc *sc;
3814 sc = ddi_get_soft_state(mwl_soft_state_p,
3816 ASSERT(sc != NULL);
3817 MWL_GLOCK(sc);
3818 sc->sc_flags &= ~MWL_F_SUSPEND;
3819 MWL_GUNLOCK(sc);
3820 if (mwl_resume(sc) != 0) {
3825 if (MWL_IS_RUNNING(sc)) {
3826 (void) mwl_init(sc);
3827 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1);
3844 sc = ddi_get_soft_state(mwl_soft_state_p, ddi_get_instance(devinfo));
3845 ic = &sc->sc_ic;
3846 sc->sc_dev = devinfo;
3849 err = ddi_regs_map_setup(devinfo, 0, (caddr_t *)&sc->sc_cfg_base, 0, 0,
3850 &mwl_reg_accattr, &sc->sc_cfg_handle);
3856 csz = ddi_get8(sc->sc_cfg_handle,
3857 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ));
3860 sc->sc_cachelsz = csz << 2;
3861 sc->sc_dmabuf_size = roundup(IEEE80211_MAX_LEN, sc->sc_cachelsz);
3862 vendor_id = ddi_get16(sc->sc_cfg_handle,
3863 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_VENID));
3864 device_id = ddi_get16(sc->sc_cfg_handle,
3865 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_DEVID));
3875 ddi_put16(sc->sc_cfg_handle,
3876 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_COMM),
3878 ddi_put8(sc->sc_cfg_handle,
3879 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_LATENCY_TIMER), 0xa8);
3880 ddi_put8(sc->sc_cfg_handle,
3881 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_ILINE), 0x10);
3885 &sc->sc_mem_base, 0, 0, &mwl_reg_accattr, &sc->sc_mem_handle);
3894 &sc->sc_io_base, 0, 0, &mwl_reg_accattr, &sc->sc_io_handle);
3907 err = mwl_alloc_cmdbuf(sc);
3914 sc->sc_imask = 0;
3915 sc->sc_hw_flags = 0;
3916 sc->sc_flags = 0;
3930 sc->sc_SDRAMSIZE_Addr = 0x40fe70b7; /* 8M SDRAM */
3933 sc->sc_SDRAMSIZE_Addr = 0x40fc70b7; /* 16M SDRAM */
3939 err = mwl_fwload(sc, NULL);
3949 err = mwl_gethwspecs(sc);
3956 err = mwl_getchannels(sc);
3966 err = mwl_alloc_rx_ring(sc, MWL_RX_RING_COUNT);
3977 err = mwl_alloc_tx_ring(sc,
3978 &sc->sc_txring[qid], MWL_TX_RING_COUNT);
3986 err = mwl_setupdma(sc);
3993 err = mwl_setup_txq(sc);
4000 IEEE80211_ADDR_COPY(ic->ic_macaddr, sc->sc_hwspecs.macAddr);
4010 err = mwl_hal_setmac_locked(sc, ic->ic_macaddr);
4017 mutex_init(&sc->sc_glock, NULL, MUTEX_DRIVER, NULL);
4018 mutex_init(&sc->sc_rxlock, NULL, MUTEX_DRIVER, NULL);
4019 mutex_init(&sc->sc_txlock, NULL, MUTEX_DRIVER, NULL);
4059 sc->sc_newstate = ic->ic_newstate;
4072 err = mwl_hal_newstation(sc, ic->ic_macaddr, 0, 0, NULL, 0, 0);
4096 sc->sc_intr_htable = kmem_zalloc(sizeof (ddi_intr_handle_t), KM_SLEEP);
4098 err = ddi_intr_alloc(devinfo, sc->sc_intr_htable,
4106 err = ddi_intr_get_pri(sc->sc_intr_htable[0], &sc->sc_intr_pri);
4113 err = ddi_intr_add_softint(devinfo, &sc->sc_softintr_hdl,
4114 DDI_INTR_SOFTPRI_MAX, mwl_softintr, (caddr_t)sc);
4121 err = ddi_intr_add_handler(sc->sc_intr_htable[0], mwl_intr,
4122 (caddr_t)sc, NULL);
4129 err = ddi_intr_enable(sc->sc_intr_htable[0]);
4151 macp->m_driver = sc;
4194 (void) ddi_intr_disable(sc->sc_intr_htable[0]);
4196 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]);
4198 (void) ddi_intr_remove_softint(sc->sc_softintr_hdl);
4199 sc->sc_softintr_hdl = NULL;
4201 (void) ddi_intr_free(sc->sc_intr_htable[0]);
4203 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t));
4205 mutex_destroy(&sc->sc_txlock);
4206 mutex_destroy(&sc->sc_rxlock);
4207 mutex_destroy(&sc->sc_glock);
4210 mwl_free_tx_ring(sc, &sc->sc_txring[qid]);
4212 mwl_free_rx_ring(sc);
4214 mwl_free_cmdbuf(sc);
4216 ddi_regs_map_free(&sc->sc_mem_handle);
4218 ddi_regs_map_free(&sc->sc_io_handle);
4220 ddi_regs_map_free(&sc->sc_cfg_handle);
4229 struct mwl_softc *sc;
4232 sc = ddi_get_soft_state(mwl_soft_state_p, ddi_get_instance(devinfo));
4233 ASSERT(sc != NULL);
4239 if (MWL_IS_RUNNING(sc))
4240 mwl_stop(sc);
4242 mwl_free_tx_ring(sc, &sc->sc_txring[qid]);
4243 mwl_free_rx_ring(sc);
4244 MWL_GLOCK(sc);
4245 sc->sc_flags |= MWL_F_SUSPEND;
4246 MWL_GUNLOCK(sc);
4254 if (mac_disable(sc->sc_ic.ic_mach) != 0)
4260 (void) mac_unregister(sc->sc_ic.ic_mach);
4262 (void) ddi_intr_remove_softint(sc->sc_softintr_hdl);
4263 sc->sc_softintr_hdl = NULL;
4264 (void) ddi_intr_disable(sc->sc_intr_htable[0]);
4265 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]);
4266 (void) ddi_intr_free(sc->sc_intr_htable[0]);
4267 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t));
4272 ieee80211_detach(&sc->sc_ic);
4276 mwl_free_tx_ring(sc, &sc->sc_txring[qid]);
4277 mwl_free_rx_ring(sc);
4278 mwl_free_cmdbuf(sc);
4280 mutex_destroy(&sc->sc_txlock);
4281 mutex_destroy(&sc->sc_rxlock);
4282 mutex_destroy(&sc->sc_glock);
4284 ddi_regs_map_free(&sc->sc_mem_handle);
4285 ddi_regs_map_free(&sc->sc_io_handle);
4286 ddi_regs_map_free(&sc->sc_cfg_handle);
4309 struct mwl_softc *sc;
4311 sc = ddi_get_soft_state(mwl_soft_state_p, ddi_get_instance(dip));
4312 if (sc == NULL)
4322 sc->sc_flags |= MWL_F_QUIESCE;
4327 mwl_stop(sc);