Lines Matching defs:mh
189 _mii_error(mii_handle_t mh, int errno)
195 if (mh->m_error != errno) {
196 cmn_err(CE_WARN, "%s: %s", mh->m_name, mii_errors[errno]);
197 mh->m_error = errno;
223 mii_handle_t mh;
231 mh = kmem_zalloc(sizeof (*mh), KM_SLEEP);
233 (void) snprintf(mh->m_name, sizeof (mh->m_name), "%s%d",
239 mh->m_dip = dip;
240 mh->m_ops = *ops;
241 mh->m_private = private;
242 mh->m_suspended = B_FALSE;
243 mh->m_started = B_FALSE;
244 mh->m_tstate = MII_STATE_PROBE;
245 mh->m_link = LINK_STATE_UNKNOWN;
246 mh->m_error = MII_EOK;
247 mh->m_addr = -1;
248 mutex_init(&mh->m_lock, NULL, MUTEX_DRIVER, NULL);
249 cv_init(&mh->m_cv, NULL, CV_DRIVER, NULL);
251 mh->m_tq = ddi_taskq_create(dip, tqname, 1, TASKQ_DEFAULTPRI, 0);
252 if (mh->m_tq == NULL) {
255 cv_destroy(&mh->m_cv);
256 mutex_destroy(&mh->m_lock);
257 kmem_free(mh, sizeof (*mh));
266 mh->m_en_aneg = GETPROP("adv_autoneg_cap");
267 mh->m_en_10_hdx = GETPROP("adv_10hdx_cap");
268 mh->m_en_10_fdx = GETPROP("adv_10fdx_cap");
269 mh->m_en_100_hdx = GETPROP("adv_100hdx_cap");
270 mh->m_en_100_fdx = GETPROP("adv_100fdx_cap");
271 mh->m_en_100_t4 = GETPROP("adv_100T4_cap");
272 mh->m_en_1000_hdx = GETPROP("adv_1000hdx_cap");
273 mh->m_en_1000_fdx = GETPROP("adv_1000fdx_cap");
275 mh->m_cap_pause = B_FALSE;
276 mh->m_cap_asmpause = B_FALSE;
278 bzero(&mh->m_bogus_phy, sizeof (mh->m_bogus_phy));
279 mh->m_bogus_phy.phy_link = LINK_STATE_UNKNOWN;
280 mh->m_bogus_phy.phy_duplex = LINK_DUPLEX_UNKNOWN;
281 mh->m_bogus_phy.phy_addr = 0xff;
282 mh->m_bogus_phy.phy_type = XCVR_NONE;
283 mh->m_bogus_phy.phy_id = (uint32_t)-1;
284 mh->m_bogus_phy.phy_loopback = PHY_LB_NONE;
285 mh->m_bogus_phy.phy_flowctrl = LINK_FLOWCTRL_NONE;
286 mh->m_phy = &mh->m_bogus_phy;
289 mh->m_phys[i].phy_mii = mh;
291 mh->m_bogus_phy.phy_mii = mh;
293 return (mh);
303 mii_set_pauseable(mii_handle_t mh, boolean_t pauseable, boolean_t asymetric)
307 mutex_enter(&mh->m_lock);
308 ph = mh->m_phy;
309 ph->phy_cap_pause = mh->m_cap_pause = pauseable;
310 ph->phy_cap_asmpause = mh->m_cap_asmpause = asymetric;
312 mh->m_en_flowctrl = LINK_FLOWCTRL_BI;
314 mh->m_en_flowctrl = LINK_FLOWCTRL_NONE;
316 mutex_exit(&mh->m_lock);
320 mii_free(mii_handle_t mh)
322 mutex_enter(&mh->m_lock);
323 mh->m_started = B_FALSE;
324 cv_broadcast(&mh->m_cv);
325 mutex_exit(&mh->m_lock);
327 ddi_taskq_destroy(mh->m_tq);
328 mutex_destroy(&mh->m_lock);
329 cv_destroy(&mh->m_cv);
330 kmem_free(mh, sizeof (*mh));
334 mii_reset(mii_handle_t mh)
336 mutex_enter(&mh->m_lock);
337 if (mh->m_tstate > MII_STATE_RESET)
338 mh->m_tstate = MII_STATE_RESET;
339 cv_broadcast(&mh->m_cv);
340 mutex_exit(&mh->m_lock);
344 mii_suspend(mii_handle_t mh)
346 mutex_enter(&mh->m_lock);
347 while ((!mh->m_suspended) && (mh->m_started)) {
348 mh->m_suspending = B_TRUE;
349 cv_broadcast(&mh->m_cv);
350 cv_wait(&mh->m_cv, &mh->m_lock);
352 mutex_exit(&mh->m_lock);
356 mii_resume(mii_handle_t mh)
358 mutex_enter(&mh->m_lock);
360 switch (mh->m_tstate) {
367 mh->m_tstate = MII_STATE_RESET;
372 (void) _mii_loopback(mh);
376 mh->m_suspended = B_FALSE;
377 cv_broadcast(&mh->m_cv);
378 mutex_exit(&mh->m_lock);
382 mii_start(mii_handle_t mh)
384 mutex_enter(&mh->m_lock);
385 if (!mh->m_started) {
386 mh->m_tstate = MII_STATE_PROBE;
387 mh->m_started = B_TRUE;
388 if (ddi_taskq_dispatch(mh->m_tq, _mii_task, mh, DDI_NOSLEEP) !=
392 mh->m_name);
393 mh->m_started = B_FALSE;
396 cv_broadcast(&mh->m_cv);
397 mutex_exit(&mh->m_lock);
401 mii_stop(mii_handle_t mh)
403 mutex_enter(&mh->m_lock);
404 mh->m_started = B_FALSE;
409 mh->m_link = LINK_STATE_UNKNOWN;
410 mh->m_phy = &mh->m_bogus_phy;
411 cv_broadcast(&mh->m_cv);
412 mutex_exit(&mh->m_lock);
417 _mii_notify(mh);
421 mii_probe(mii_handle_t mh)
423 mutex_enter(&mh->m_lock);
424 _mii_probe(mh);
425 mutex_exit(&mh->m_lock);
429 mii_check(mii_handle_t mh)
431 mutex_enter(&mh->m_lock);
432 cv_broadcast(&mh->m_cv);
433 mutex_exit(&mh->m_lock);
437 mii_get_speed(mii_handle_t mh)
439 phy_handle_t *ph = mh->m_phy;
445 mii_get_duplex(mii_handle_t mh)
447 phy_handle_t *ph = mh->m_phy;
453 mii_get_state(mii_handle_t mh)
455 phy_handle_t *ph = mh->m_phy;
461 mii_get_flowctrl(mii_handle_t mh)
463 phy_handle_t *ph = mh->m_phy;
469 mii_get_loopmodes(mii_handle_t mh, lb_property_t *modes)
471 phy_handle_t *ph = mh->m_phy;
523 mii_get_loopback(mii_handle_t mh)
525 phy_handle_t *ph = mh->m_phy;
531 mii_set_loopback(mii_handle_t mh, uint32_t loop)
536 mutex_enter(&mh->m_lock);
537 ph = mh->m_phy;
539 if ((!mh->m_started) || (!ph->phy_present) ||
540 (loop >= mii_get_loopmodes(mh, NULL))) {
545 rv = _mii_loopback(mh);
547 mh->m_tstate = MII_STATE_LOOPBACK;
549 cv_broadcast(&mh->m_cv);
550 mutex_exit(&mh->m_lock);
556 mii_get_id(mii_handle_t mh)
558 phy_handle_t *ph = mh->m_phy;
564 mii_get_addr(mii_handle_t mh)
566 return (mh->m_addr);
572 mii_m_loop_ioctl(mii_handle_t mh, queue_t *wq, mblk_t *mp)
603 cnt = mii_get_loopmodes(mh, modes);
613 cnt = mii_get_loopmodes(mh, modes);
625 mode = mii_get_loopback(mh);
639 rv = mii_set_loopback(mh, mode);
652 mii_m_getprop(mii_handle_t mh, const char *name, mac_prop_id_t num,
663 mutex_enter(&mh->m_lock);
665 ph = mh->m_phy;
711 mutex_exit(&mh->m_lock);
717 mii_m_propinfo(mii_handle_t mh, const char *name, mac_prop_id_t num,
724 mutex_enter(&mh->m_lock);
726 ph = mh->m_phy;
759 mutex_exit(&mh->m_lock);
763 mii_m_setprop(mii_handle_t mh, const char *name, mac_prop_id_t num,
777 mutex_enter(&mh->m_lock);
779 ph = mh->m_phy;
801 macpp = &mh->m_en_1000_fdx;
806 macpp = &mh->m_en_1000_hdx;
811 macpp = &mh->m_en_100_fdx;
816 macpp = &mh->m_en_100_hdx;
821 macpp = &mh->m_en_100_t4;
826 macpp = &mh->m_en_10_fdx;
831 macpp = &mh->m_en_10_hdx;
836 macpp = &mh->m_en_aneg;
888 mh->m_en_flowctrl = fc;
889 mh->m_tstate = MII_STATE_RESET;
890 cv_broadcast(&mh->m_cv);
908 mh->m_tstate = MII_STATE_RESET;
909 cv_broadcast(&mh->m_cv);
915 mutex_exit(&mh->m_lock);
920 mii_m_getstat(mii_handle_t mh, uint_t stat, uint64_t *val)
925 mutex_enter(&mh->m_lock);
927 ph = mh->m_phy;
1053 mutex_exit(&mh->m_lock);
1065 mii_handle_t mh = ph->phy_mii;
1067 return ((*mh->m_ops.mii_read)(mh->m_private, ph->phy_addr, reg));
1073 mii_handle_t mh = ph->phy_mii;
1075 (*mh->m_ops.mii_write)(mh->m_private, ph->phy_addr, reg, val);
1600 mii_handle_t mh = ph->phy_mii;
1602 return (ddi_prop_get_int(DDI_DEV_T_ANY, mh->m_dip, 0, prop, dflt));
1608 mii_handle_t mh = ph->phy_mii;
1610 return (mh->m_name);
1616 mii_handle_t mh = ph->phy_mii;
1618 return (ddi_driver_name(mh->m_dip));
1639 _mii_notify(mii_handle_t mh)
1641 if (mh->m_ops.mii_notify != NULL) {
1642 mh->m_ops.mii_notify(mh->m_private, mh->m_link);
1651 mii_handle_t mh = ph->phy_mii;
1706 ph->phy_cap_pause = mh->m_cap_pause;
1707 ph->phy_cap_asmpause = mh->m_cap_asmpause;
1761 ph->phy_en_##CAP = (mh->m_en_##CAP > 0) ? \
1762 mh->m_en_##CAP : ph->phy_cap_##CAP
1774 ph->phy_en_flowctrl = mh->m_en_flowctrl;
1793 _mii_probe(mii_handle_t mh)
1803 user_addr = ddi_prop_get_int(DDI_DEV_T_ANY, mh->m_dip, 0,
1805 old_addr = mh->m_addr;
1821 first = ddi_prop_get_int(DDI_DEV_T_ANY, mh->m_dip, 0, "first-phy", 1);
1834 ph = &mh->m_phys[curr_addr];
1838 ph->phy_mii = mh;
1883 mh->m_addr = -1;
1884 mh->m_phy = &mh->m_bogus_phy;
1885 _mii_error(mh, MII_ENOPHY);
1887 mh->m_addr = new_addr;
1888 mh->m_phy = &mh->m_phys[new_addr];
1889 mh->m_tstate = MII_STATE_RESET;
1893 mh->m_name, mii_xcvr_types[mh->m_phy->phy_type],
1894 mh->m_addr, mh->m_phy->phy_vendor,
1895 mh->m_phy->phy_model);
1896 mh->m_link = LINK_STATE_UNKNOWN;
1902 _mii_reset(mii_handle_t mh)
1907 ASSERT(mutex_owned(&mh->m_lock));
1914 ph = &mh->m_phys[i];
1920 if (ph == mh->m_phy)
1926 ph = mh->m_phy;
1931 notify = (mh->m_link != LINK_STATE_DOWN);
1932 mh->m_link = LINK_STATE_DOWN;
1938 _mii_error(mh, MII_ERESET);
1943 if (mh->m_ops.mii_reset != NULL) {
1944 mh->m_ops.mii_reset(mh->m_private);
1949 _mii_notify(mh);
1955 _mii_loopback(mii_handle_t mh)
1959 ASSERT(mutex_owned(&mh->m_lock));
1961 ph = mh->m_phy;
1963 if (_mii_reset(mh) != DDI_SUCCESS) {
1967 mh->m_tstate = MII_STATE_START;
1971 _mii_error(mh, MII_ELOOP);
1976 mh->m_link = ph->phy_link = LINK_STATE_UP;
1977 _mii_notify(mh);
1983 _mii_start(mii_handle_t mh)
1987 ph = mh->m_phy;
1989 ASSERT(mutex_owned(&mh->m_lock));
1994 _mii_error(mh, MII_ESTART);
1998 mh->m_error = MII_EOK;
2003 _mii_check(mii_handle_t mh)
2011 ph = mh->m_phy;
2013 olink = mh->m_link;
2021 _mii_error(mh, MII_ECHECK);
2022 mh->m_link = LINK_STATE_UNKNOWN;
2023 _mii_notify(mh);
2027 mh->m_link = ph->phy_link;
2030 if ((mh->m_link != olink) ||
2034 _mii_notify(mh);
2043 mii_handle_t mh = _mh;
2048 mutex_enter(&mh->m_lock);
2053 if (!mh->m_started) {
2057 ph = mh->m_phy;
2069 if (mh->m_suspending) {
2070 mh->m_suspended = B_TRUE;
2071 cv_broadcast(&mh->m_cv);
2073 if (mh->m_suspended) {
2074 mh->m_suspending = B_FALSE;
2075 cv_wait(&mh->m_cv, &mh->m_lock);
2079 switch (mh->m_tstate) {
2081 _mii_probe(mh);
2082 ph = mh->m_phy;
2096 if (_mii_reset(mh) == DDI_SUCCESS) {
2097 mh->m_tstate = MII_STATE_START;
2117 if (_mii_start(mh) == DDI_SUCCESS) {
2120 mh->m_tstate = MII_STATE_RUN;
2122 mh->m_tstate = MII_STATE_PROBE;
2137 if (_mii_check(mh) == DDI_FAILURE) {
2144 mh->m_tstate = MII_STATE_PROBE;
2146 } else if (mh->m_link == LINK_STATE_UP) {
2159 mh->m_tstate = MII_STATE_RESET;
2179 cv_wait(&mh->m_cv, &mh->m_lock);
2183 (void) cv_reltimedwait(&mh->m_cv, &mh->m_lock,
2188 mutex_exit(&mh->m_lock);