Lines Matching defs:sc
273 static int iwk_eep_load(iwk_sc_t *sc);
274 static void iwk_get_mac_from_eep(iwk_sc_t *sc);
275 static int iwk_eep_sem_down(iwk_sc_t *sc);
276 static void iwk_eep_sem_up(iwk_sc_t *sc);
292 static int32_t iwk_curr_tempera(iwk_sc_t *sc);
293 static int iwk_tx_power_calibration(iwk_sc_t *sc);
294 static inline int iwk_is_24G_band(iwk_sc_t *sc);
295 static inline int iwk_is_fat_channel(iwk_sc_t *sc);
297 static struct iwk_eep_channel *iwk_get_eep_channel(iwk_sc_t *sc,
300 static int32_t iwk_band_number(iwk_sc_t *sc, uint16_t channel);
304 static int iwk_channel_interpolate(iwk_sc_t *sc, uint16_t channel,
309 static int iwk_txpower_table_cmd_init(iwk_sc_t *sc,
311 static void iwk_statistics_notify(iwk_sc_t *sc, iwk_rx_desc_t *desc);
312 static int iwk_is_associated(iwk_sc_t *sc);
313 static int iwk_rxgain_diff_init(iwk_sc_t *sc);
314 static int iwk_rxgain_diff(iwk_sc_t *sc);
315 static int iwk_rx_sens_init(iwk_sc_t *sc);
316 static int iwk_rx_sens(iwk_sc_t *sc);
317 static int iwk_cck_sens(iwk_sc_t *sc, uint32_t actual_rx_time);
318 static int iwk_ofdm_sens(iwk_sc_t *sc, uint32_t actual_rx_time);
346 static void iwk_destroy_locks(iwk_sc_t *sc);
348 static void iwk_thread(iwk_sc_t *sc);
352 static int iwk_fast_recover(iwk_sc_t *sc);
474 iwk_sc_t *sc;
489 sc = ddi_get_soft_state(iwk_soft_state_p,
491 ASSERT(sc != NULL);
493 mutex_enter(&sc->sc_glock);
494 sc->sc_flags &= ~IWK_F_SUSPEND;
495 mutex_exit(&sc->sc_glock);
497 if (sc->sc_flags & IWK_F_RUNNING)
498 (void) iwk_init(sc);
500 mutex_enter(&sc->sc_glock);
501 sc->sc_flags |= IWK_F_LAZY_RESUME;
502 mutex_exit(&sc->sc_glock);
518 sc = ddi_get_soft_state(iwk_soft_state_p, instance);
519 sc->sc_dip = dip;
521 err = ddi_regs_map_setup(dip, 0, &sc->sc_cfg_base, 0, 0,
522 &iwk_reg_accattr, &sc->sc_cfg_handle);
528 sc->sc_rev = ddi_get8(sc->sc_cfg_handle,
529 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_REVID));
530 ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base + 0x41), 0);
531 sc->sc_clsz = ddi_get16(sc->sc_cfg_handle,
532 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ));
533 if (!sc->sc_clsz)
534 sc->sc_clsz = 16;
535 sc->sc_clsz = (sc->sc_clsz << 2);
536 sc->sc_dmabuf_sz = roundup(0x1000 + sizeof (struct ieee80211_frame) +
539 IEEE80211_WEP_CRCLEN), sc->sc_clsz);
543 err = ddi_regs_map_setup(dip, 1, &sc->sc_base,
544 0, 0, &iwk_reg_accattr, &sc->sc_handle);
565 sc->sc_intr_htable = kmem_zalloc(sizeof (ddi_intr_handle_t), KM_SLEEP);
567 err = ddi_intr_alloc(dip, sc->sc_intr_htable, DDI_INTR_TYPE_FIXED, 0,
575 err = ddi_intr_get_pri(sc->sc_intr_htable[0], &sc->sc_intr_pri);
582 mutex_init(&sc->sc_glock, NULL, MUTEX_DRIVER,
583 DDI_INTR_PRI(sc->sc_intr_pri));
584 mutex_init(&sc->sc_tx_lock, NULL, MUTEX_DRIVER,
585 DDI_INTR_PRI(sc->sc_intr_pri));
586 mutex_init(&sc->sc_mt_lock, NULL, MUTEX_DRIVER,
587 DDI_INTR_PRI(sc->sc_intr_pri));
588 mutex_init(&sc->sc_ibss.node_tb_lock, NULL, MUTEX_DRIVER,
589 DDI_INTR_PRI(sc->sc_intr_pri));
591 cv_init(&sc->sc_fw_cv, NULL, CV_DRIVER, NULL);
592 cv_init(&sc->sc_cmd_cv, NULL, CV_DRIVER, NULL);
593 cv_init(&sc->sc_tx_cv, "tx-ring", CV_DRIVER, NULL);
597 cv_init(&sc->sc_mt_cv, NULL, CV_DRIVER, NULL);
598 sc->sc_mf_thread = NULL;
599 sc->sc_mf_thread_switch = 0;
604 err = iwk_alloc_shared(sc);
614 err = iwk_alloc_kw(sc);
624 err = iwk_preinit(sc);
632 err = iwk_eep_load(sc); /* get hardware configurations from eeprom */
638 if (LE_16(sc->sc_eep_map.calib_version) < EEP_TX_POWER_VERSION_NEW) {
643 iwk_get_mac_from_eep(sc);
645 err = iwk_ring_init(sc);
652 sc->sc_hdr = (iwk_firmware_hdr_t *)iwk_fw_bin;
654 err = iwk_alloc_fw_dma(sc);
665 ic = &sc->sc_ic;
716 sc->sc_newstate = ic->ic_newstate;
719 sc->sc_recv_mgmt = ic->ic_recv_mgmt;
729 err = ddi_intr_add_softint(dip, &sc->sc_soft_hdl, DDI_INTR_SOFTPRI_MAX,
730 iwk_rx_softintr, (caddr_t)sc);
740 err = ddi_intr_add_handler(sc->sc_intr_htable[0], iwk_intr,
741 (caddr_t)sc, NULL);
748 err = ddi_intr_enable(sc->sc_intr_htable[0]);
770 macp->m_driver = sc;
809 sc->sc_mf_thread_switch = 1;
810 if (sc->sc_mf_thread == NULL)
811 sc->sc_mf_thread = thread_create((caddr_t)NULL, 0,
812 iwk_thread, sc, 0, &p0, TS_RUN, minclsyspri);
814 sc->sc_flags |= IWK_F_ATTACHED;
818 (void) ddi_intr_disable(sc->sc_intr_htable[0]);
820 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]);
823 (void) ddi_intr_remove_softint(sc->sc_soft_hdl);
824 sc->sc_soft_hdl = NULL;
828 iwk_free_fw_dma(sc);
830 iwk_ring_free(sc);
832 iwk_free_kw(sc);
834 iwk_free_shared(sc);
836 iwk_destroy_locks(sc);
838 (void) ddi_intr_free(sc->sc_intr_htable[0]);
840 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t));
842 ddi_regs_map_free(&sc->sc_handle);
844 ddi_regs_map_free(&sc->sc_cfg_handle);
854 iwk_sc_t *sc;
857 sc = ddi_get_soft_state(iwk_soft_state_p, ddi_get_instance(dip));
858 ASSERT(sc != NULL);
864 mutex_enter(&sc->sc_glock);
865 sc->sc_flags |= IWK_F_SUSPEND;
866 mutex_exit(&sc->sc_glock);
867 if (sc->sc_flags & IWK_F_RUNNING) {
868 iwk_stop(sc);
877 if (!(sc->sc_flags & IWK_F_ATTACHED))
880 err = mac_disable(sc->sc_ic.ic_mach);
887 mutex_enter(&sc->sc_mt_lock);
888 sc->sc_mf_thread_switch = 0;
889 while (sc->sc_mf_thread != NULL) {
890 if (cv_wait_sig(&sc->sc_mt_cv, &sc->sc_mt_lock) == 0)
893 mutex_exit(&sc->sc_mt_lock);
895 iwk_stop(sc);
901 (void) mac_unregister(sc->sc_ic.ic_mach);
903 mutex_enter(&sc->sc_glock);
904 iwk_free_fw_dma(sc);
905 iwk_ring_free(sc);
906 iwk_free_kw(sc);
907 iwk_free_shared(sc);
908 mutex_exit(&sc->sc_glock);
910 (void) ddi_intr_disable(sc->sc_intr_htable[0]);
911 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]);
912 (void) ddi_intr_free(sc->sc_intr_htable[0]);
913 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t));
915 (void) ddi_intr_remove_softint(sc->sc_soft_hdl);
916 sc->sc_soft_hdl = NULL;
921 ieee80211_detach(&sc->sc_ic);
923 iwk_destroy_locks(sc);
925 ddi_regs_map_free(&sc->sc_handle);
926 ddi_regs_map_free(&sc->sc_cfg_handle);
946 iwk_sc_t *sc;
948 sc = ddi_get_soft_state(iwk_soft_state_p, ddi_get_instance(dip));
949 ASSERT(sc != NULL);
955 sc->sc_flags |= IWK_F_QUIESCED;
957 iwk_stop(sc);
963 iwk_destroy_locks(iwk_sc_t *sc)
965 cv_destroy(&sc->sc_mt_cv);
966 mutex_destroy(&sc->sc_mt_lock);
967 cv_destroy(&sc->sc_tx_cv);
968 cv_destroy(&sc->sc_cmd_cv);
969 cv_destroy(&sc->sc_fw_cv);
970 mutex_destroy(&sc->sc_tx_lock);
971 mutex_destroy(&sc->sc_glock);
978 iwk_alloc_dma_mem(iwk_sc_t *sc, size_t memsize,
988 err = ddi_dma_alloc_handle(sc->sc_dip, dma_attr_p,
1055 iwk_alloc_fw_dma(iwk_sc_t *sc)
1065 t = (char *)(sc->sc_hdr + 1);
1066 err = iwk_alloc_dma_mem(sc, LE_32(sc->sc_hdr->textsz),
1069 &sc->sc_dma_fw_text);
1070 dma_p = &sc->sc_dma_fw_text;
1079 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->textsz));
1081 t += LE_32(sc->sc_hdr->textsz);
1082 err = iwk_alloc_dma_mem(sc, LE_32(sc->sc_hdr->datasz),
1085 &sc->sc_dma_fw_data);
1086 dma_p = &sc->sc_dma_fw_data;
1095 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->datasz));
1097 err = iwk_alloc_dma_mem(sc, LE_32(sc->sc_hdr->datasz),
1100 &sc->sc_dma_fw_data_bak);
1101 dma_p = &sc->sc_dma_fw_data_bak;
1111 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->datasz));
1113 t += LE_32(sc->sc_hdr->datasz);
1114 err = iwk_alloc_dma_mem(sc, LE_32(sc->sc_hdr->init_textsz),
1117 &sc->sc_dma_fw_init_text);
1118 dma_p = &sc->sc_dma_fw_init_text;
1128 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->init_textsz));
1130 t += LE_32(sc->sc_hdr->init_textsz);
1131 err = iwk_alloc_dma_mem(sc, LE_32(sc->sc_hdr->init_datasz),
1134 &sc->sc_dma_fw_init_data);
1135 dma_p = &sc->sc_dma_fw_init_data;
1145 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->init_datasz));
1147 sc->sc_boot = t + LE_32(sc->sc_hdr->init_datasz);
1153 iwk_free_fw_dma(iwk_sc_t *sc)
1155 iwk_free_dma_mem(&sc->sc_dma_fw_text);
1156 iwk_free_dma_mem(&sc->sc_dma_fw_data);
1157 iwk_free_dma_mem(&sc->sc_dma_fw_data_bak);
1158 iwk_free_dma_mem(&sc->sc_dma_fw_init_text);
1159 iwk_free_dma_mem(&sc->sc_dma_fw_init_data);
1166 iwk_alloc_shared(iwk_sc_t *sc)
1172 err = iwk_alloc_dma_mem(sc, sizeof (iwk_shared_t),
1175 &sc->sc_dma_sh);
1178 sc->sc_shared = (iwk_shared_t *)sc->sc_dma_sh.mem_va;
1180 dma_p = &sc->sc_dma_sh;
1187 iwk_free_shared(sc);
1192 iwk_free_shared(iwk_sc_t *sc)
1194 iwk_free_dma_mem(&sc->sc_dma_sh);
1201 iwk_alloc_kw(iwk_sc_t *sc)
1207 err = iwk_alloc_dma_mem(sc, IWK_KW_SIZE,
1210 &sc->sc_dma_kw);
1214 dma_p = &sc->sc_dma_kw;
1221 iwk_free_kw(sc);
1226 iwk_free_kw(iwk_sc_t *sc)
1228 iwk_free_dma_mem(&sc->sc_dma_kw);
1232 iwk_alloc_rx_ring(iwk_sc_t *sc)
1239 ring = &sc->sc_rxq;
1242 err = iwk_alloc_dma_mem(sc, RX_QUEUE_SIZE * sizeof (uint32_t),
1261 err = iwk_alloc_dma_mem(sc, sc->sc_dmabuf_sz,
1288 iwk_free_rx_ring(sc);
1293 iwk_reset_rx_ring(iwk_sc_t *sc)
1297 iwk_mac_access_enter(sc);
1298 IWK_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
1300 if (IWK_READ(sc, FH_MEM_RSSR_RX_STATUS_REG) & (1 << 24))
1308 iwk_mac_access_exit(sc);
1310 sc->sc_rxq.cur = 0;
1314 iwk_free_rx_ring(iwk_sc_t *sc)
1319 if (sc->sc_rxq.data[i].dma_data.dma_hdl)
1320 IWK_DMA_SYNC(sc->sc_rxq.data[i].dma_data,
1322 iwk_free_dma_mem(&sc->sc_rxq.data[i].dma_data);
1325 if (sc->sc_rxq.dma_desc.dma_hdl)
1326 IWK_DMA_SYNC(sc->sc_rxq.dma_desc, DDI_DMA_SYNC_FORDEV);
1327 iwk_free_dma_mem(&sc->sc_rxq.dma_desc);
1331 iwk_alloc_tx_ring(iwk_sc_t *sc, iwk_tx_ring_t *ring,
1348 err = iwk_alloc_dma_mem(sc,
1366 err = iwk_alloc_dma_mem(sc,
1396 err = iwk_alloc_dma_mem(sc, sc->sc_dmabuf_sz,
1426 iwk_free_tx_ring(sc, ring);
1431 iwk_reset_tx_ring(iwk_sc_t *sc, iwk_tx_ring_t *ring)
1436 iwk_mac_access_enter(sc);
1438 IWK_WRITE(sc, IWK_FH_TCSR_CHNL_TX_CONFIG_REG(ring->qid), 0);
1440 if (IWK_READ(sc, IWK_FH_TSSR_TX_STATUS_REG) &
1449 iwk_mac_access_exit(sc);
1462 iwk_free_tx_ring(iwk_sc_t *sc, iwk_tx_ring_t *ring)
1486 iwk_ring_init(iwk_sc_t *sc)
1493 err = iwk_alloc_tx_ring(sc, &sc->sc_txq[i], TFD_TX_CMD_SLOTS,
1498 err = iwk_alloc_tx_ring(sc, &sc->sc_txq[IWK_CMD_QUEUE_NUM],
1502 err = iwk_alloc_rx_ring(sc);
1512 iwk_ring_free(iwk_sc_t *sc)
1516 iwk_free_rx_ring(sc);
1518 iwk_free_tx_ring(sc, &sc->sc_txq[i]);
1549 iwk_sc_t *sc = (iwk_sc_t *)ic;
1554 mutex_enter(&sc->sc_glock);
1562 sc->sc_flags |= IWK_F_SCANNING;
1563 sc->sc_scan_pending = 0;
1564 iwk_set_led(sc, 2, 10, 2);
1570 sc->sc_config.assoc_id = 0;
1571 sc->sc_config.filter_flags &=
1575 "flags %x filter_flags %x\n", sc->sc_config.chan,
1576 sc->sc_config.flags, sc->sc_config.filter_flags));
1578 err = iwk_cmd(sc, REPLY_RXON, &sc->sc_config,
1583 sc->sc_flags &= ~IWK_F_SCANNING;
1584 mutex_exit(&sc->sc_glock);
1592 err = iwk_cmd(sc, REPLY_ADD_STA, &node,
1597 sc->sc_flags &= ~IWK_F_SCANNING;
1598 mutex_exit(&sc->sc_glock);
1607 sc->sc_flags |= IWK_F_SCANNING;
1608 sc->sc_scan_pending = 0;
1610 iwk_set_led(sc, 2, 10, 2);
1613 mutex_exit(&sc->sc_glock);
1615 err = sc->sc_newstate(ic, nstate, arg);
1616 mutex_enter(&sc->sc_glock);
1617 if ((err != 0) || ((err = iwk_scan(sc)) != 0)) {
1620 sc->sc_flags &= ~IWK_F_SCANNING;
1623 mutex_exit(&sc->sc_glock);
1629 sc->sc_clk = 0;
1634 sc->sc_flags &= ~IWK_F_SCANNING;
1638 sc->sc_config.assoc_id = 0;
1639 sc->sc_config.filter_flags &= ~LE_32(RXON_FILTER_ASSOC_MSK);
1646 if ((err = iwk_hw_set_before_auth(sc)) != 0) {
1649 mutex_exit(&sc->sc_glock);
1656 sc->sc_flags &= ~IWK_F_SCANNING;
1661 iwk_set_led(sc, 2, 10, 10);
1677 mutex_exit(&sc->sc_glock);
1690 mutex_exit(&sc->sc_glock);
1696 sc->sc_tempera = iwk_curr_tempera(sc);
1702 err = iwk_tx_power_calibration(sc);
1706 mutex_exit(&sc->sc_glock);
1719 mutex_exit(&sc->sc_glock);
1725 mutex_enter(&sc->sc_mt_lock);
1727 sc->sc_flags |= IWK_F_RATE_AUTO_CTL;
1734 sc->sc_flags &= ~IWK_F_RATE_AUTO_CTL;
1736 mutex_exit(&sc->sc_mt_lock);
1739 iwk_set_led(sc, 2, 0, 1);
1744 sc->sc_flags &= ~IWK_F_SCANNING;
1748 iwk_set_led(sc, 2, 1, 0);
1752 sc->sc_flags &= ~IWK_F_SCANNING;
1758 mutex_exit(&sc->sc_glock);
1760 err = sc->sc_newstate(ic, nstate, arg);
1764 mutex_enter(&sc->sc_glock);
1770 err = iwk_rx_sens_init(sc);
1774 mutex_exit(&sc->sc_glock);
1779 err = iwk_rxgain_diff_init(sc);
1783 mutex_exit(&sc->sc_glock);
1787 mutex_exit(&sc->sc_glock);
1797 iwk_sc_t *sc = arg;
1798 struct ieee80211com *ic = &sc->sc_ic;
1825 iwk_sc_t *sc = (iwk_sc_t *)ic;
1839 sc->sc_config.filter_flags &= ~LE_32(RXON_FILTER_DIS_DECRYPT_MSK |
1842 mutex_enter(&sc->sc_glock);
1850 mutex_exit(&sc->sc_glock);
1851 mutex_enter(&sc->sc_ibss.node_tb_lock);
1858 if (sc->sc_ibss.ibss_node_tb[index1].used &&
1859 IEEE80211_ADDR_EQ(sc->sc_ibss.
1868 mutex_exit(&sc->sc_ibss.node_tb_lock);
1875 sc->sc_ibss.ibss_node_tb[index1].
1877 sc->sc_ibss.ibss_node_tb[index1].
1880 sc->sc_ibss.ibss_node_tb[index1].
1882 sc->sc_ibss.ibss_node_tb[index1].
1886 (void) memcpy(sc->sc_ibss.ibss_node_tb[index1].node.key,
1888 sc->sc_ibss.ibss_node_tb[index1].node.key_flags |=
1890 sc->sc_ibss.ibss_node_tb[index1].node.key_flags =
1891 LE_16(sc->sc_ibss.ibss_node_tb[index1].
1893 sc->sc_ibss.ibss_node_tb[index1].node.sta_mask =
1895 sc->sc_ibss.ibss_node_tb[index1].node.control = 1;
1897 mutex_enter(&sc->sc_glock);
1898 err = iwk_cmd(sc, REPLY_ADD_STA,
1899 &sc->sc_ibss.ibss_node_tb[index1].node,
1904 mutex_exit(&sc->sc_glock);
1905 mutex_exit(&sc->sc_ibss.node_tb_lock);
1908 mutex_exit(&sc->sc_glock);
1910 mutex_exit(&sc->sc_ibss.node_tb_lock);
1928 err = iwk_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 1);
1932 mutex_exit(&sc->sc_glock);
1935 mutex_exit(&sc->sc_glock);
1943 iwk_mac_access_enter(iwk_sc_t *sc)
1948 tmp = IWK_READ(sc, CSR_GP_CNTRL);
1949 IWK_WRITE(sc, CSR_GP_CNTRL,
1954 if ((IWK_READ(sc, CSR_GP_CNTRL) &
1969 iwk_mac_access_exit(iwk_sc_t *sc)
1971 uint32_t tmp = IWK_READ(sc, CSR_GP_CNTRL);
1972 IWK_WRITE(sc, CSR_GP_CNTRL,
1977 iwk_mem_read(iwk_sc_t *sc, uint32_t addr)
1979 IWK_WRITE(sc, HBUS_TARG_MEM_RADDR, addr);
1980 return (IWK_READ(sc, HBUS_TARG_MEM_RDAT));
1984 iwk_mem_write(iwk_sc_t *sc, uint32_t addr, uint32_t data)
1986 IWK_WRITE(sc, HBUS_TARG_MEM_WADDR, addr);
1987 IWK_WRITE(sc, HBUS_TARG_MEM_WDAT, data);
1991 iwk_reg_read(iwk_sc_t *sc, uint32_t addr)
1993 IWK_WRITE(sc, HBUS_TARG_PRPH_RADDR, addr | (3 << 24));
1994 return (IWK_READ(sc, HBUS_TARG_PRPH_RDAT));
1998 iwk_reg_write(iwk_sc_t *sc, uint32_t addr, uint32_t data)
2000 IWK_WRITE(sc, HBUS_TARG_PRPH_WADDR, addr | (3 << 24));
2001 IWK_WRITE(sc, HBUS_TARG_PRPH_WDAT, data);
2005 iwk_reg_write_region_4(iwk_sc_t *sc, uint32_t addr,
2009 iwk_reg_write(sc, addr, LE_32(*data));
2027 iwk_load_firmware(iwk_sc_t *sc)
2029 uint32_t *boot_fw = (uint32_t *)sc->sc_boot;
2030 uint32_t size = LE_32(sc->sc_hdr->bootsz);
2038 iwk_mac_access_enter(sc);
2040 iwk_reg_write(sc, BSM_DRAM_INST_PTR_REG,
2041 sc->sc_dma_fw_init_text.cookie.dmac_address >> 4);
2042 iwk_reg_write(sc, BSM_DRAM_DATA_PTR_REG,
2043 sc->sc_dma_fw_init_data.cookie.dmac_address >> 4);
2044 iwk_reg_write(sc, BSM_DRAM_INST_BYTECOUNT_REG,
2045 sc->sc_dma_fw_init_text.cookie.dmac_size);
2046 iwk_reg_write(sc, BSM_DRAM_DATA_BYTECOUNT_REG,
2047 sc->sc_dma_fw_init_data.cookie.dmac_size);
2050 iwk_reg_write_region_4(sc, BSM_SRAM_LOWER_BOUND, boot_fw,
2053 iwk_reg_write(sc, BSM_WR_MEM_SRC_REG, 0);
2054 iwk_reg_write(sc, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
2055 iwk_reg_write(sc, BSM_WR_DWCOUNT_REG, size / sizeof (uint32_t));
2060 iwk_reg_write(sc, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
2064 if (!(iwk_reg_read(sc, BSM_WR_CTRL_REG) &
2076 iwk_reg_write(sc, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
2078 iwk_mac_access_exit(sc);
2085 iwk_rx_intr(iwk_sc_t *sc, iwk_rx_desc_t *desc, iwk_rx_data_t *data)
2087 ieee80211com_t *ic = &sc->sc_ic;
2088 iwk_rx_ring_t *ring = &sc->sc_rxq;
2139 if ((len < 16) || (len > sc->sc_dmabuf_sz)) {
2152 sc->sc_rx_err++;
2159 sc->sc_assoc_id = *((uint16_t *)(wh + 1) + 2);
2161 sc->sc_assoc_id));
2176 sc->sc_rx_nobuf++;
2186 iwk_tx_intr(iwk_sc_t *sc, iwk_rx_desc_t *desc, iwk_rx_data_t *data)
2188 ieee80211com_t *ic = &sc->sc_ic;
2189 iwk_tx_ring_t *ring = &sc->sc_txq[desc->hdr.qid & 0x3];
2204 sc->sc_tx_retries++;
2206 sc->sc_tx_retries));
2209 sc->sc_tx_timer = 0;
2211 mutex_enter(&sc->sc_tx_lock);
2215 if ((sc->sc_need_reschedule) && (ring->queued <= (ring->count << 3))) {
2216 sc->sc_need_reschedule = 0;
2217 mutex_exit(&sc->sc_tx_lock);
2219 mutex_enter(&sc->sc_tx_lock);
2221 mutex_exit(&sc->sc_tx_lock);
2225 iwk_cmd_intr(iwk_sc_t *sc, iwk_rx_desc_t *desc)
2230 mutex_enter(&sc->sc_glock);
2231 sc->sc_flags |= IWK_F_CMD_DONE;
2232 cv_signal(&sc->sc_cmd_cv);
2233 mutex_exit(&sc->sc_glock);
2241 iwk_ucode_alive(iwk_sc_t *sc, iwk_rx_desc_t *desc)
2260 (void) memcpy(&sc->sc_card_alive_init, ar,
2263 iwk_mac_access_enter(sc);
2264 iwk_reg_write(sc, BSM_DRAM_INST_PTR_REG,
2265 sc->sc_dma_fw_text.cookie.dmac_address >> 4);
2266 iwk_reg_write(sc, BSM_DRAM_DATA_PTR_REG,
2267 sc->sc_dma_fw_data_bak.cookie.dmac_address >> 4);
2268 iwk_reg_write(sc, BSM_DRAM_DATA_BYTECOUNT_REG,
2269 sc->sc_dma_fw_data.cookie.dmac_size);
2270 iwk_reg_write(sc, BSM_DRAM_INST_BYTECOUNT_REG,
2271 sc->sc_dma_fw_text.cookie.dmac_size | 0x80000000);
2272 iwk_mac_access_exit(sc);
2275 (void) memcpy(&sc->sc_card_alive_run, ar,
2281 iwk_mac_access_enter(sc);
2284 sc->sc_scd_base = iwk_reg_read(sc, SCD_SRAM_BASE_ADDR);
2287 for (base = sc->sc_scd_base + SCD_CONTEXT_DATA_OFFSET, i = 0;
2289 iwk_mem_write(sc, base + i, 0);
2292 for (base = sc->sc_scd_base + SCD_TX_STTS_BITMAP_OFFSET;
2294 iwk_mem_write(sc, base + i, 0);
2297 for (base = sc->sc_scd_base + SCD_TRANSLATE_TBL_OFFSET;
2299 iwk_mem_write(sc, base + i, 0);
2301 iwk_reg_write(sc, SCD_DRAM_BASE_ADDR,
2302 sc->sc_dma_sh.cookie.dmac_address >> 10);
2303 iwk_reg_write(sc, SCD_QUEUECHAIN_SEL, 0);
2307 iwk_reg_write(sc, SCD_QUEUE_RDPTR(i), 0);
2308 IWK_WRITE(sc, HBUS_TARG_WRPTR, (i << 8));
2309 iwk_mem_write(sc, sc->sc_scd_base +
2312 iwk_mem_write(sc, sc->sc_scd_base +
2317 iwk_reg_write(sc, SCD_INTERRUPT_MASK,
2320 iwk_reg_write(sc, SCD_TXFACT,
2327 iwk_reg_write(sc,
2333 iwk_mac_access_exit(sc);
2335 sc->sc_flags |= IWK_F_FW_INIT;
2336 cv_signal(&sc->sc_fw_cv);
2345 iwk_sc_t *sc = (iwk_sc_t *)arg;
2346 ieee80211com_t *ic = &sc->sc_ic;
2351 mutex_enter(&sc->sc_glock);
2352 if (sc->sc_rx_softint_pending != 1) {
2353 mutex_exit(&sc->sc_glock);
2357 IWK_WRITE(sc, CSR_INT_MASK, 0);
2358 mutex_exit(&sc->sc_glock);
2364 index = sc->sc_shared->val0 & 0xfff;
2366 while (sc->sc_rxq.cur != index) {
2367 data = &sc->sc_rxq.data[sc->sc_rxq.cur];
2372 index, sc->sc_rxq.cur, desc->hdr.qid, desc->hdr.idx,
2382 iwk_cmd_intr(sc, desc);
2386 iwk_rx_intr(sc, desc, data);
2390 iwk_tx_intr(sc, desc, data);
2394 iwk_ucode_alive(sc, desc);
2414 sc->sc_ostate = sc->sc_ic.ic_state;
2415 ieee80211_new_state(&sc->sc_ic,
2417 sc->sc_flags |=
2443 sc->sc_scan_pending++;
2448 iwk_statistics_notify(sc, desc);
2452 sc->sc_rxq.cur = (sc->sc_rxq.cur + 1) % RX_QUEUE_SIZE;
2460 IWK_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, index & (~7));
2462 mutex_enter(&sc->sc_glock);
2464 IWK_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);
2465 sc->sc_rx_softint_pending = 0;
2466 mutex_exit(&sc->sc_glock);
2475 iwk_sc_t *sc = (iwk_sc_t *)arg;
2478 mutex_enter(&sc->sc_glock);
2480 if (sc->sc_flags & IWK_F_SUSPEND) {
2481 mutex_exit(&sc->sc_glock);
2485 r = IWK_READ(sc, CSR_INT);
2487 mutex_exit(&sc->sc_glock);
2493 rfh = IWK_READ(sc, CSR_FH_INT_STATUS);
2496 IWK_WRITE(sc, CSR_INT_MASK, 0);
2498 IWK_WRITE(sc, CSR_INT, r);
2499 IWK_WRITE(sc, CSR_FH_INT_STATUS, rfh);
2501 if (sc->sc_soft_hdl == NULL) {
2502 mutex_exit(&sc->sc_glock);
2507 mutex_exit(&sc->sc_glock);
2510 iwk_write_error_log(sc);
2511 iwk_write_event_log(sc);
2513 iwk_stop(sc);
2514 sc->sc_ostate = sc->sc_ic.ic_state;
2517 if (!IWK_CHK_FAST_RECOVER(sc))
2518 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1);
2520 sc->sc_flags |= IWK_F_HW_ERR_RECOVER;
2525 uint32_t tmp = IWK_READ(sc, CSR_GP_CNTRL);
2532 sc->sc_rx_softint_pending = 1;
2533 (void) ddi_intr_trigger_softint(sc->sc_soft_hdl, NULL);
2541 IWK_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);
2542 mutex_exit(&sc->sc_glock);
2601 iwk_sc_t *sc = (iwk_sc_t *)arg;
2602 ieee80211com_t *ic = &sc->sc_ic;
2605 if (sc->sc_flags & IWK_F_SUSPEND) {
2615 if ((sc->sc_flags & IWK_F_HW_ERR_RECOVER) &&
2616 IWK_CHK_FAST_RECOVER(sc)) {
2637 iwk_sc_t *sc = (iwk_sc_t *)ic;
2651 ring = &sc->sc_txq[0];
2658 mutex_enter(&sc->sc_tx_lock);
2659 if (sc->sc_flags & IWK_F_SUSPEND) {
2660 mutex_exit(&sc->sc_tx_lock);
2671 sc->sc_need_reschedule = 1;
2672 mutex_exit(&sc->sc_tx_lock);
2677 sc->sc_tx_nobuf++;
2681 mutex_exit(&sc->sc_tx_lock);
2705 mutex_enter(&sc->sc_glock);
2706 mutex_enter(&sc->sc_ibss.node_tb_lock);
2713 if (sc->sc_ibss.ibss_node_tb[index1].used &&
2714 IEEE80211_ADDR_EQ(sc->sc_ibss.
2731 mutex_exit(&sc->sc_ibss.node_tb_lock);
2732 mutex_exit(&sc->sc_glock);
2734 sc->sc_tx_err++;
2742 mutex_exit(&sc->sc_ibss.node_tb_lock);
2743 mutex_exit(&sc->sc_glock);
2750 sc->sc_tx_err++;
2774 sc->sc_tx_err++;
2904 mutex_enter(&sc->sc_tx_lock);
2906 mutex_exit(&sc->sc_tx_lock);
2909 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
2912 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
2920 IWK_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
2928 if (sc->sc_tx_timer == 0)
2929 sc->sc_tx_timer = 4;
2938 iwk_sc_t *sc = (iwk_sc_t *)arg;
2939 ieee80211com_t *ic = &sc->sc_ic;
2958 (void) memset(&sc->sc_config, 0, sizeof (iwk_rxon_cmd_t));
2959 IEEE80211_ADDR_COPY(sc->sc_config.node_addr, ic->ic_macaddr);
2960 IEEE80211_ADDR_COPY(sc->sc_config.wlap_bssid, ic->ic_macaddr);
2961 sc->sc_config.chan =
2963 sc->sc_config.flags = LE_32(RXON_FLG_TSF2HOST_MSK |
2966 sc->sc_config.flags &= LE_32(~RXON_FLG_CCK_MSK);
2969 sc->sc_config.dev_type = RXON_DEV_TYPE_ESS;
2970 sc->sc_config.filter_flags |=
2977 sc->sc_config.dev_type = RXON_DEV_TYPE_IBSS;
2978 sc->sc_config.flags |=
2980 sc->sc_config.filter_flags =
2986 sc->sc_config.dev_type = RXON_DEV_TYPE_AP;
2989 sc->sc_config.dev_type = RXON_DEV_TYPE_SNIFFER;
2990 sc->sc_config.filter_flags |=
2996 sc->sc_config.cck_basic_rates = 0x0f;
2997 sc->sc_config.ofdm_basic_rates = 0xff;
2998 sc->sc_config.ofdm_ht_single_stream_basic_rates = 0xff;
2999 sc->sc_config.ofdm_ht_dual_stream_basic_rates = 0xff;
3001 mutex_enter(&sc->sc_glock);
3002 sc->sc_config.rx_chain = LE_16(RXON_RX_CHAIN_DRIVER_FORCE_MSK |
3006 err1 = iwk_cmd(sc, REPLY_RXON, &sc->sc_config,
3020 txpower.channel = sc->sc_config.chan;
3032 err1 = iwk_cmd(sc, REPLY_TX_PWR_TABLE_CMD, &txpower,
3043 err1 = iwk_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 1);
3063 err1 = iwk_cmd(sc, REPLY_TX_LINK_QUALITY_CMD, &link_quality,
3069 mutex_exit(&sc->sc_glock);
3083 if (sc->sc_flags & IWK_F_RUNNING) {
3084 iwk_m_stop(sc);
3085 (void) iwk_m_start(sc);
3102 iwk_sc_t *sc = (iwk_sc_t *)arg;
3104 err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num,
3115 iwk_sc_t *sc = (iwk_sc_t *)arg;
3116 ieee80211com_t *ic = &sc->sc_ic;
3123 if (sc->sc_flags & IWK_F_RUNNING) {
3124 iwk_m_stop(sc);
3125 (void) iwk_m_start(sc);
3140 iwk_sc_t *sc = (iwk_sc_t *)arg;
3141 ieee80211com_t *ic = &sc->sc_ic;
3150 iwk_sc_t *sc = (iwk_sc_t *)arg;
3151 ieee80211com_t *ic = &sc->sc_ic;
3154 mutex_enter(&sc->sc_glock);
3163 *val = sc->sc_tx_nobuf;
3166 *val = sc->sc_rx_nobuf;
3169 *val = sc->sc_rx_err;
3185 *val = sc->sc_tx_err;
3188 *val = sc->sc_tx_retries;
3200 mutex_exit(&sc->sc_glock);
3203 mutex_exit(&sc->sc_glock);
3206 mutex_exit(&sc->sc_glock);
3215 iwk_sc_t *sc = (iwk_sc_t *)arg;
3216 ieee80211com_t *ic = &sc->sc_ic;
3219 err = iwk_init(sc);
3227 mutex_enter(&sc->sc_glock);
3228 sc->sc_flags |= IWK_F_HW_ERR_RECOVER;
3229 mutex_exit(&sc->sc_glock);
3235 mutex_enter(&sc->sc_glock);
3236 sc->sc_flags |= IWK_F_RUNNING;
3237 mutex_exit(&sc->sc_glock);
3245 iwk_sc_t *sc = (iwk_sc_t *)arg;
3246 ieee80211com_t *ic = &sc->sc_ic;
3248 iwk_stop(sc);
3251 mutex_enter(&sc->sc_mt_lock);
3252 sc->sc_flags &= ~IWK_F_HW_ERR_RECOVER;
3253 sc->sc_flags &= ~IWK_F_RATE_AUTO_CTL;
3254 mutex_exit(&sc->sc_mt_lock);
3255 mutex_enter(&sc->sc_glock);
3256 sc->sc_flags &= ~IWK_F_RUNNING;
3257 mutex_exit(&sc->sc_glock);
3264 iwk_sc_t *sc = (iwk_sc_t *)arg;
3265 ieee80211com_t *ic = &sc->sc_ic;
3270 mutex_enter(&sc->sc_glock);
3271 err = iwk_config(sc);
3272 mutex_exit(&sc->sc_glock);
3300 iwk_thread(iwk_sc_t *sc)
3302 ieee80211com_t *ic = &sc->sc_ic;
3307 mutex_enter(&sc->sc_mt_lock);
3308 while (sc->sc_mf_thread_switch) {
3309 tmp = IWK_READ(sc, CSR_GP_CNTRL);
3311 sc->sc_flags &= ~IWK_F_RADIO_OFF;
3313 sc->sc_flags |= IWK_F_RADIO_OFF;
3318 if ((sc->sc_flags & IWK_F_SUSPEND) ||
3319 (sc->sc_flags & IWK_F_RADIO_OFF)) {
3320 mutex_exit(&sc->sc_mt_lock);
3322 mutex_enter(&sc->sc_mt_lock);
3330 (sc->sc_flags & IWK_F_HW_ERR_RECOVER)) {
3336 iwk_stop(sc);
3338 if (IWK_CHK_FAST_RECOVER(sc)) {
3340 bcopy(&sc->sc_config, &sc->sc_config_save,
3341 sizeof (sc->sc_config));
3343 mutex_exit(&sc->sc_mt_lock);
3346 mutex_enter(&sc->sc_mt_lock);
3349 err = iwk_init(sc);
3357 sc->sc_flags |= IWK_F_RUNNING;
3359 if (!IWK_CHK_FAST_RECOVER(sc) ||
3360 iwk_fast_recover(sc) != IWK_SUCCESS) {
3361 sc->sc_flags &= ~IWK_F_HW_ERR_RECOVER;
3363 mutex_exit(&sc->sc_mt_lock);
3365 if (sc->sc_ostate != IEEE80211_S_INIT)
3368 mutex_enter(&sc->sc_mt_lock);
3372 if (ic->ic_mach && (sc->sc_flags & IWK_F_LAZY_RESUME)) {
3376 sc->sc_flags &= ~IWK_F_LAZY_RESUME;
3377 mutex_exit(&sc->sc_mt_lock);
3384 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1);
3385 mutex_enter(&sc->sc_mt_lock);
3389 (sc->sc_flags & IWK_F_SCANNING) && sc->sc_scan_pending) {
3393 sc->sc_scan_pending--;
3394 mutex_exit(&sc->sc_mt_lock);
3396 if (sc->sc_flags & IWK_F_SCANNING)
3398 mutex_enter(&sc->sc_mt_lock);
3405 (sc->sc_flags & IWK_F_RATE_AUTO_CTL)) {
3407 if (clk > sc->sc_clk + drv_usectohz(500000)) {
3408 iwk_amrr_timeout(sc);
3419 mutex_exit(&sc->sc_mt_lock);
3421 mutex_enter(&sc->sc_mt_lock);
3423 if (sc->sc_tx_timer) {
3426 sc->sc_tx_timer--;
3427 if (sc->sc_tx_timer == 0) {
3428 sc->sc_flags |= IWK_F_HW_ERR_RECOVER;
3429 sc->sc_ostate = IEEE80211_S_RUN;
3439 sc->sc_mf_thread = NULL;
3440 cv_signal(&sc->sc_mt_cv);
3441 mutex_exit(&sc->sc_mt_lock);
3449 iwk_cmd(iwk_sc_t *sc, int code, const void *buf, int size, int async)
3451 iwk_tx_ring_t *ring = &sc->sc_txq[IWK_CMD_QUEUE_NUM];
3457 ASSERT(mutex_owned(&sc->sc_glock));
3476 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3479 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3483 IWK_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3488 sc->sc_flags &= ~IWK_F_CMD_DONE;
3490 while (!(sc->sc_flags & IWK_F_CMD_DONE)) {
3491 if (cv_timedwait(&sc->sc_cmd_cv, &sc->sc_glock, clk) <
3495 if (sc->sc_flags & IWK_F_CMD_DONE)
3503 iwk_set_led(iwk_sc_t *sc, uint8_t id, uint8_t off, uint8_t on)
3512 (void) iwk_cmd(sc, REPLY_LEDS_CMD, &led, sizeof (led), 1);
3516 iwk_hw_set_before_auth(iwk_sc_t *sc)
3518 ieee80211com_t *ic = &sc->sc_ic;
3534 IEEE80211_ADDR_COPY(sc->sc_config.bssid, in->in_bssid);
3535 sc->sc_config.chan = LE_16(ieee80211_chan2ieee(ic, in->in_chan));
3537 sc->sc_config.cck_basic_rates = 0x03;
3538 sc->sc_config.ofdm_basic_rates = 0;
3541 sc->sc_config.cck_basic_rates = 0;
3542 sc->sc_config.ofdm_basic_rates = 0x15;
3544 sc->sc_config.cck_basic_rates = 0x0f;
3545 sc->sc_config.ofdm_basic_rates = 0xff;
3548 sc->sc_config.flags &= ~LE_32(RXON_FLG_SHORT_PREAMBLE_MSK |
3552 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_SLOT_MSK);
3554 sc->sc_config.flags &= LE_32(~RXON_FLG_SHORT_SLOT_MSK);
3557 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_PREAMBLE_MSK);
3559 sc->sc_config.flags &= LE_32(~RXON_FLG_SHORT_PREAMBLE_MSK);
3564 LE_16(sc->sc_config.chan), LE_32(sc->sc_config.flags),
3565 LE_32(sc->sc_config.filter_flags),
3566 sc->sc_config.cck_basic_rates, sc->sc_config.ofdm_basic_rates,
3567 sc->sc_config.bssid[0], sc->sc_config.bssid[1],
3568 sc->sc_config.bssid[2], sc->sc_config.bssid[3],
3569 sc->sc_config.bssid[4], sc->sc_config.bssid[5]));
3570 err = iwk_cmd(sc, REPLY_RXON, &sc->sc_config,
3575 sc->sc_config.chan);
3580 sc->sc_tempera = iwk_curr_tempera(sc);
3583 err = iwk_tx_power_calibration(sc);
3594 err = iwk_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 1);
3622 err = iwk_cmd(sc, REPLY_TX_LINK_QUALITY_CMD, &link_quality,
3637 iwk_scan(iwk_sc_t *sc)
3639 ieee80211com_t *ic = &sc->sc_ic;
3640 iwk_tx_ring_t *ring = &sc->sc_txq[IWK_CMD_QUEUE_NUM];
3788 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3791 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3797 IWK_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3803 iwk_config(iwk_sc_t *sc)
3805 ieee80211com_t *ic = &sc->sc_ic;
3818 err = iwk_cmd(sc, POWER_TABLE_CMD, &powertable,
3830 err = iwk_cmd(sc, REPLY_BT_CONFIG, &bt,
3840 (void) memset(&sc->sc_config, 0, sizeof (iwk_rxon_cmd_t));
3841 IEEE80211_ADDR_COPY(sc->sc_config.node_addr, ic->ic_macaddr);
3842 IEEE80211_ADDR_COPY(sc->sc_config.wlap_bssid, ic->ic_macaddr);
3843 sc->sc_config.chan = LE_16(ieee80211_chan2ieee(ic, ic->ic_curchan));
3844 sc->sc_config.flags = LE_32(RXON_FLG_TSF2HOST_MSK |
3846 sc->sc_config.flags &= LE_32(~RXON_FLG_CCK_MSK);
3849 sc->sc_config.dev_type = RXON_DEV_TYPE_ESS;
3850 sc->sc_config.filter_flags |= LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
3856 sc->sc_config.dev_type = RXON_DEV_TYPE_IBSS;
3857 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_PREAMBLE_MSK);
3858 sc->sc_config.filter_flags = LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
3863 sc->sc_config.dev_type = RXON_DEV_TYPE_AP;
3866 sc->sc_config.dev_type = RXON_DEV_TYPE_SNIFFER;
3867 sc->sc_config.filter_flags |= LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
3871 sc->sc_config.cck_basic_rates = 0x0f;
3872 sc->sc_config.ofdm_basic_rates = 0xff;
3874 sc->sc_config.ofdm_ht_single_stream_basic_rates = 0xff;
3875 sc->sc_config.ofdm_ht_dual_stream_basic_rates = 0xff;
3879 sc->sc_config.rx_chain = LE_16(RXON_RX_CHAIN_DRIVER_FORCE_MSK |
3884 err = iwk_cmd(sc, REPLY_RXON, &sc->sc_config,
3892 sc->sc_tempera = iwk_curr_tempera(sc);
3895 err = iwk_tx_power_calibration(sc);
3906 err = iwk_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 0);
3928 err = iwk_cmd(sc, REPLY_TX_LINK_QUALITY_CMD, &link_quality,
3940 iwk_stop_master(iwk_sc_t *sc)
3945 tmp = IWK_READ(sc, CSR_RESET);
3946 IWK_WRITE(sc, CSR_RESET, tmp | CSR_RESET_REG_FLAG_STOP_MASTER);
3948 tmp = IWK_READ(sc, CSR_GP_CNTRL);
3954 if (IWK_READ(sc, CSR_RESET) &
3965 iwk_power_up(iwk_sc_t *sc)
3969 iwk_mac_access_enter(sc);
3970 tmp = iwk_reg_read(sc, ALM_APMG_PS_CTL);
3973 iwk_reg_write(sc, ALM_APMG_PS_CTL, tmp);
3974 iwk_mac_access_exit(sc);
3981 iwk_preinit(iwk_sc_t *sc)
3988 IWK_WRITE(sc, CSR_INT, 0xffffffff);
3990 tmp = IWK_READ(sc, CSR_GIO_CHICKEN_BITS);
3991 IWK_WRITE(sc, CSR_GIO_CHICKEN_BITS,
3994 tmp = IWK_READ(sc, CSR_GP_CNTRL);
3995 IWK_WRITE(sc, CSR_GP_CNTRL, tmp | CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
3999 if (IWK_READ(sc, CSR_GP_CNTRL) &
4009 iwk_mac_access_enter(sc);
4010 tmp = iwk_reg_read(sc, APMG_CLK_CTRL_REG);
4011 iwk_reg_write(sc, APMG_CLK_CTRL_REG, tmp |
4015 tmp = iwk_reg_read(sc, ALM_APMG_PCIDEV_STT);
4016 iwk_reg_write(sc, ALM_APMG_PCIDEV_STT, tmp |
4018 iwk_mac_access_exit(sc);
4020 IWK_WRITE(sc, CSR_INT_COALESCING, 512 / 32); /* ??? */
4022 (void) iwk_power_up(sc);
4024 if ((sc->sc_rev & 0x80) == 0x80 && (sc->sc_rev & 0x7f) < 8) {
4025 tmp = ddi_get32(sc->sc_cfg_handle,
4026 (uint32_t *)(sc->sc_cfg_base + 0xe8));
4027 ddi_put32(sc->sc_cfg_handle,
4028 (uint32_t *)(sc->sc_cfg_base + 0xe8),
4033 vlink = ddi_get8(sc->sc_cfg_handle,
4034 (uint8_t *)(sc->sc_cfg_base + 0xf0));
4035 ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base + 0xf0),
4038 tmp = IWK_READ(sc, CSR_SW_VER);
4042 IWK_WRITE(sc, CSR_SW_VER, tmp);
4045 iwk_mac_access_enter(sc);
4046 tmp = iwk_reg_read(sc, ALM_APMG_PS_CTL);
4048 iwk_reg_write(sc, ALM_APMG_PS_CTL, tmp);
4050 tmp = iwk_reg_read(sc, ALM_APMG_PS_CTL);
4052 iwk_reg_write(sc, ALM_APMG_PS_CTL, tmp);
4053 iwk_mac_access_exit(sc);
4060 static int iwk_eep_sem_down(iwk_sc_t *sc)
4066 tmp = IWK_READ(sc, CSR_HW_IF_CONFIG_REG);
4067 IWK_WRITE(sc, CSR_HW_IF_CONFIG_REG,
4071 if (IWK_READ(sc, CSR_HW_IF_CONFIG_REG) &
4083 static void iwk_eep_sem_up(iwk_sc_t *sc)
4087 tmp = IWK_READ(sc, CSR_HW_IF_CONFIG_REG);
4088 IWK_WRITE(sc, CSR_HW_IF_CONFIG_REG,
4096 static int iwk_eep_load(iwk_sc_t *sc)
4100 uint16_t addr, eep_sz = sizeof (sc->sc_eep_map);
4101 uint16_t *eep_p = (uint16_t *)&sc->sc_eep_map;
4104 eep_gp = IWK_READ(sc, CSR_EEPROM_GP);
4111 rr = iwk_eep_sem_down(sc);
4118 IWK_WRITE(sc, CSR_EEPROM_REG, addr<<1);
4119 tmp = IWK_READ(sc, CSR_EEPROM_REG);
4120 IWK_WRITE(sc, CSR_EEPROM_REG, tmp & ~(0x2));
4123 rv = IWK_READ(sc, CSR_EEPROM_REG);
4131 iwk_eep_sem_up(sc);
4138 iwk_eep_sem_up(sc);
4145 static void iwk_get_mac_from_eep(iwk_sc_t *sc)
4147 ieee80211com_t *ic = &sc->sc_ic;
4148 struct iwk_eep *ep = &sc->sc_eep_map;
4158 iwk_init(iwk_sc_t *sc)
4164 mutex_enter(&sc->sc_glock);
4165 sc->sc_flags &= ~IWK_F_FW_INIT;
4167 (void) iwk_preinit(sc);
4169 tmp = IWK_READ(sc, CSR_GP_CNTRL);
4176 iwk_mac_access_enter(sc);
4177 IWK_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
4179 IWK_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
4180 IWK_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
4181 sc->sc_rxq.dma_desc.cookie.dmac_address >> 8);
4183 IWK_WRITE(sc, FH_RSCSR_CHNL0_STTS_WPTR_REG,
4184 ((uint32_t)(sc->sc_dma_sh.cookie.dmac_address +
4187 IWK_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG,
4193 iwk_mac_access_exit(sc);
4194 IWK_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG,
4198 iwk_mac_access_enter(sc);
4199 iwk_reg_write(sc, SCD_TXFACT, 0);
4202 iwk_reg_write(sc, IWK_FH_KW_MEM_ADDR_REG,
4203 sc->sc_dma_kw.cookie.dmac_address >> 4);
4206 IWK_WRITE(sc, FH_MEM_CBBC_QUEUE(qid),
4207 sc->sc_txq[qid].dma_desc.cookie.dmac_address >> 8);
4208 IWK_WRITE(sc, IWK_FH_TCSR_CHNL_TX_CONFIG_REG(qid),
4212 iwk_mac_access_exit(sc);
4215 IWK_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
4216 IWK_WRITE(sc, CSR_UCODE_DRV_GP1_CLR,
4220 IWK_WRITE(sc, CSR_INT, 0xffffffff);
4223 IWK_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);
4225 IWK_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
4226 IWK_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
4231 (void) memcpy(sc->sc_dma_fw_data_bak.mem_va,
4232 sc->sc_dma_fw_data.mem_va,
4233 sc->sc_dma_fw_data.alength);
4237 err = iwk_load_firmware(sc);
4245 IWK_WRITE(sc, CSR_RESET, 0);
4254 while (!(sc->sc_flags & IWK_F_FW_INIT)) {
4255 if (cv_timedwait(&sc->sc_fw_cv, &sc->sc_glock, clk) < 0)
4258 if (!(sc->sc_flags & IWK_F_FW_INIT)) {
4268 err = iwk_config(sc);
4275 mutex_exit(&sc->sc_glock);
4280 mutex_exit(&sc->sc_glock);
4285 iwk_stop(iwk_sc_t *sc)
4290 if (!(sc->sc_flags & IWK_F_QUIESCED))
4291 mutex_enter(&sc->sc_glock);
4293 IWK_WRITE(sc, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4295 IWK_WRITE(sc, CSR_INT_MASK, 0);
4296 IWK_WRITE(sc, CSR_INT, CSR_INI_SET_MASK);
4297 IWK_WRITE(sc, CSR_FH_INT_STATUS, 0xffffffff);
4301 iwk_reset_tx_ring(sc, &sc->sc_txq[i]);
4304 iwk_reset_rx_ring(sc);
4306 iwk_mac_access_enter(sc);
4307 iwk_reg_write(sc, ALM_APMG_CLK_DIS, APMG_CLK_REG_VAL_DMA_CLK_RQT);
4308 iwk_mac_access_exit(sc);
4312 iwk_stop_master(sc);
4314 sc->sc_tx_timer = 0;
4315 sc->sc_flags &= ~IWK_F_SCANNING;
4316 sc->sc_scan_pending = 0;
4318 tmp = IWK_READ(sc, CSR_RESET);
4319 IWK_WRITE(sc, CSR_RESET, tmp | CSR_RESET_REG_FLAG_SW_RESET);
4321 if (!(sc->sc_flags & IWK_F_QUIESCED))
4322 mutex_exit(&sc->sc_glock);
4362 iwk_amrr_timeout(iwk_sc_t *sc)
4364 ieee80211com_t *ic = &sc->sc_ic;
4371 sc->sc_clk = ddi_get_lbolt();
4426 static int32_t iwk_curr_tempera(iwk_sc_t *sc)
4433 if (iwk_is_fat_channel(sc)) {
4434 r1 = (int32_t)LE_32(sc->sc_card_alive_init.therm_r1[1]);
4435 r2 = (int32_t)LE_32(sc->sc_card_alive_init.therm_r2[1]);
4436 r3 = (int32_t)LE_32(sc->sc_card_alive_init.therm_r3[1]);
4437 r4_u = LE_32(sc->sc_card_alive_init.therm_r4[1]);
4439 r1 = (int32_t)LE_32(sc->sc_card_alive_init.therm_r1[0]);
4440 r2 = (int32_t)LE_32(sc->sc_card_alive_init.therm_r2[0]);
4441 r3 = (int32_t)LE_32(sc->sc_card_alive_init.therm_r3[0]);
4442 r4_u = LE_32(sc->sc_card_alive_init.therm_r4[0]);
4445 if (sc->sc_flags & IWK_F_STATISTICS) {
4446 r4_s = (int32_t)(LE_32(sc->sc_statistics.general.temperature) <<
4473 static inline int iwk_is_24G_band(iwk_sc_t *sc)
4475 return (LE_32(sc->sc_config.flags) & RXON_FLG_BAND_24G_MSK);
4479 static inline int iwk_is_fat_channel(iwk_sc_t *sc)
4481 return ((LE_32(sc->sc_config.flags) &
4483 (LE_32(sc->sc_config.flags) & RXON_FLG_CHANNEL_MODE_MIXED_MSK));
4555 static struct iwk_eep_channel *iwk_get_eep_channel(iwk_sc_t *sc,
4572 return (&sc->sc_eep_map.band_24_channels[i]);
4577 return (&sc->sc_eep_map.band_52_channels[i]);
4583 return (&sc->sc_eep_map.band_1_channels[i]);
4589 return (&sc->sc_eep_map.band_2_channels[i]);
4594 return (&sc->sc_eep_map.band_3_channels[i]);
4599 return (&sc->sc_eep_map.band_4_channels[i]);
4604 return (&sc->sc_eep_map.band_5_channels[i]);
4616 static int32_t iwk_band_number(iwk_sc_t *sc, uint16_t channel)
4621 if (0 == sc->sc_eep_map.calib_info.band_info_tbl[b_n].ch_from) {
4626 (uint16_t)sc->sc_eep_map.calib_info.
4629 (uint16_t)sc->sc_eep_map.calib_info.
4673 static int iwk_channel_interpolate(iwk_sc_t *sc, uint16_t channel,
4682 ban_n = iwk_band_number(sc, channel);
4688 (uint32_t)sc->sc_eep_map.calib_info.band_info_tbl[ban_n].ch1.ch_num;
4690 (uint32_t)sc->sc_eep_map.calib_info.band_info_tbl[ban_n].ch2.ch_num;
4703 &(sc->sc_eep_map.calib_info.
4706 &(sc->sc_eep_map.calib_info.band_info_tbl[ban_n].
4809 static int iwk_txpower_table_cmd_init(iwk_sc_t *sc,
4837 channel = LE_16(sc->sc_config.chan);
4840 is_24G = iwk_is_24G_band(sc);
4843 is_fat = iwk_is_fat_channel(sc);
4849 if (is_fat && (LE_32(sc->sc_config.flags) &
4856 eep_chan_p = iwk_get_eep_channel(sc, channel, is_24G,
4872 sc->sc_user_txpower = (int32_t)eep_chan_p->max_power_avg;
4873 if (sc->sc_user_txpower < IWK_TX_POWER_TARGET_POWER_MIN) {
4877 } else if (sc->sc_user_txpower > IWK_TX_POWER_TARGET_POWER_MAX) {
4883 target_power = 2 * sc->sc_user_txpower;
4903 sc->sc_eep_map.calib_info.saturation_power24;
4906 sc->sc_eep_map.calib_info.saturation_power52;
4933 (void) iwk_channel_interpolate(sc, channel, &eep_chan_calib);
4935 eep_voltage = (int32_t)LE_16(sc->sc_eep_map.calib_info.voltage);
4936 init_voltage = (int32_t)LE_32(sc->sc_card_alive_init.voltage);
4942 if (sc->sc_tempera >= IWK_TX_POWER_TEMPERATURE_MIN) {
4943 temperature = sc->sc_tempera;
4947 if (sc->sc_tempera <= IWK_TX_POWER_TEMPERATURE_MAX) {
4948 temperature = sc->sc_tempera;
4999 LE_32(sc->sc_card_alive_init.
5067 static int iwk_tx_power_calibration(iwk_sc_t *sc)
5072 if (sc->sc_flags & IWK_F_SCANNING) {
5077 cmd.band = (uint8_t)iwk_is_24G_band(sc);
5078 cmd.channel = sc->sc_config.chan;
5082 rv = iwk_txpower_table_cmd_init(sc, &cmd.tx_power);
5089 rv = iwk_cmd(sc, REPLY_TX_PWR_TABLE_CMD, &cmd, sizeof (cmd), 1);
5095 sc->sc_last_tempera = sc->sc_tempera;
5101 static void iwk_statistics_notify(iwk_sc_t *sc, iwk_rx_desc_t *desc)
5107 mutex_enter(&sc->sc_glock);
5109 is_diff = (sc->sc_statistics.general.temperature !=
5111 (LE_32(sc->sc_statistics.flag) &
5116 (void) memcpy(&sc->sc_statistics, statistics_p,
5119 sc->sc_flags |= IWK_F_STATISTICS;
5121 if (!(sc->sc_flags & IWK_F_SCANNING)) {
5123 (void) iwk_rxgain_diff(sc);
5126 (void) iwk_rx_sens(sc);
5131 mutex_exit(&sc->sc_glock);
5136 sc->sc_tempera = iwk_curr_tempera(sc);
5139 if (((sc->sc_tempera - sc->sc_last_tempera) >= 3) ||
5140 ((sc->sc_last_tempera - sc->sc_tempera) >= 3)) {
5142 (void) iwk_tx_power_calibration(sc);
5145 mutex_exit(&sc->sc_glock);
5149 static int iwk_is_associated(iwk_sc_t *sc)
5151 return (LE_32(sc->sc_config.filter_flags) & RXON_FILTER_ASSOC_MSK);
5155 static int iwk_rxgain_diff_init(iwk_sc_t *sc)
5161 gain_diff_p = &sc->sc_rxgain_diff;
5170 if (iwk_is_associated(sc)) {
5177 rv = iwk_cmd(sc, REPLY_PHY_CALIBRATION_CMD, &cmd,
5193 static int iwk_rxgain_diff(iwk_sc_t *sc)
5207 &sc->sc_statistics.rx.general;
5208 struct iwk_rx_gain_diff *gain_diff_p = &sc->sc_rxgain_diff;
5219 is_24G = iwk_is_24G_band(sc);
5220 channel_n = sc->sc_config.chan; /* channel number */
5222 if ((channel_n != (LE_32(sc->sc_statistics.flag) >> 16)) ||
5224 (LE_32(sc->sc_statistics.flag) &
5366 rv = iwk_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
5388 static int iwk_rx_sens_init(iwk_sc_t *sc)
5392 struct iwk_rx_sensitivity *rx_sens_p = &sc->sc_rx_sens;
5458 rv = iwk_cmd(sc, SENSITIVITY_CMD, &cmd, sizeof (cmd), 1);
5475 static int iwk_rx_sens(iwk_sc_t *sc)
5480 &sc->sc_statistics.rx.general;
5481 struct iwk_rx_sensitivity *rx_sens_p = &sc->sc_rx_sens;
5507 rv = iwk_ofdm_sens(sc, actual_rx_time);
5513 rv = iwk_cck_sens(sc, actual_rx_time);
5552 rv = iwk_cmd(sc, SENSITIVITY_CMD, &cmd, sizeof (cmd), 1);
5567 static int iwk_cck_sens(iwk_sc_t *sc, uint32_t actual_rx_time)
5578 &sc->sc_statistics.rx.general;
5579 struct iwk_rx_sensitivity *rx_sens_p = &sc->sc_rx_sens;
5581 cck_fa = LE_32(sc->sc_statistics.rx.cck.false_alarm_cnt);
5582 cck_bp = LE_32(sc->sc_statistics.rx.cck.plcp_err);
5772 static int iwk_ofdm_sens(iwk_sc_t *sc, uint32_t actual_rx_time)
5778 struct iwk_rx_sensitivity *rx_sens_p = &sc->sc_rx_sens;
5780 ofdm_fa = LE_32(sc->sc_statistics.rx.ofdm.false_alarm_cnt);
5781 ofdm_bp = LE_32(sc->sc_statistics.rx.ofdm.plcp_err);
5856 iwk_sc_t *sc = (iwk_sc_t *)ic;
5861 sc->sc_recv_mgmt(ic, mp, in, subtype, rssi, rstamp);
5863 mutex_enter(&sc->sc_glock);
5866 if (sc->sc_ibss.ibss_beacon.syncbeacon && in == ic->ic_bss &&
5869 &sc->sc_ibss.ibss_beacon.iwk_boff,
5870 sc->sc_ibss.ibss_beacon.mp, 0)) {
5871 bcopy(sc->sc_ibss.ibss_beacon.mp->b_rptr,
5872 sc->sc_ibss.ibss_beacon.beacon_cmd.
5874 MBLKL(sc->sc_ibss.ibss_beacon.mp));
5876 err = iwk_cmd(sc, REPLY_TX_BEACON,
5877 &sc->sc_ibss.ibss_beacon.beacon_cmd,
5878 sc->sc_ibss.ibss_beacon.beacon_cmd_len, 1);
5883 sc->sc_ibss.ibss_beacon.syncbeacon = 0;
5888 mutex_enter(&sc->sc_ibss.node_tb_lock);
5894 if (sc->sc_ibss.ibss_node_tb[index1].used &&
5895 IEEE80211_ADDR_EQ(sc->sc_ibss.
5913 mutex_exit(&sc->sc_ibss.node_tb_lock);
5919 mutex_exit(&sc->sc_glock);
5945 static void iwk_write_event_log(iwk_sc_t *sc)
5959 log_event_table_ptr = LE_32(sc->sc_card_alive_run.log_event_table_ptr);
5965 iwk_mac_access_enter(sc);
5968 log_size = iwk_mem_read(sc, log_event_table_ptr);
5970 type = iwk_mem_read(sc, log_event_table_ptr);
5972 wraps = iwk_mem_read(sc, log_event_table_ptr);
5974 idx = iwk_mem_read(sc, log_event_table_ptr);
5979 iwk_mac_access_exit(sc);
5993 event_id = iwk_mem_read(sc, logptr);
5995 data1 = iwk_mem_read(sc, logptr);
6001 data2 = iwk_mem_read(sc, logptr);
6015 event_id = iwk_mem_read(sc, logptr);
6017 data1 = iwk_mem_read(sc, logptr);
6023 data2 = iwk_mem_read(sc, logptr);
6032 iwk_mac_access_exit(sc);
6056 static void iwk_write_error_log(iwk_sc_t *sc)
6061 err_ptr = LE_32(sc->sc_card_alive_run.error_event_table_ptr);
6067 iwk_mac_access_enter(sc);
6069 valid = iwk_mem_read(sc, err_ptr);
6072 iwk_mac_access_exit(sc);
6076 IWK_DBG((IWK_DEBUG_EEPROM, "err=%d ", iwk_mem_read(sc, err_ptr)));
6078 IWK_DBG((IWK_DEBUG_EEPROM, "pc=0x%X ", iwk_mem_read(sc, err_ptr)));
6081 "branch link1=0x%X ", iwk_mem_read(sc, err_ptr)));
6084 "branch link2=0x%X ", iwk_mem_read(sc, err_ptr)));
6087 "interrupt link1=0x%X ", iwk_mem_read(sc, err_ptr)));
6090 "interrupt link2=0x%X ", iwk_mem_read(sc, err_ptr)));
6092 IWK_DBG((IWK_DEBUG_EEPROM, "data1=0x%X ", iwk_mem_read(sc, err_ptr)));
6094 IWK_DBG((IWK_DEBUG_EEPROM, "data2=0x%X ", iwk_mem_read(sc, err_ptr)));
6096 IWK_DBG((IWK_DEBUG_EEPROM, "line=%d ", iwk_mem_read(sc, err_ptr)));
6098 IWK_DBG((IWK_DEBUG_EEPROM, "bcon_time=%d ", iwk_mem_read(sc, err_ptr)));
6100 IWK_DBG((IWK_DEBUG_EEPROM, "tsf_low=%d ", iwk_mem_read(sc, err_ptr)));
6102 IWK_DBG((IWK_DEBUG_EEPROM, "tsf_hi=%d\n", iwk_mem_read(sc, err_ptr)));
6104 iwk_mac_access_exit(sc);
6110 iwk_sc_t *sc = (iwk_sc_t *)ic;
6114 mutex_enter(&sc->sc_ibss.node_tb_lock);
6121 sc->sc_ibss.ibss_node_tb[i].used = 0;
6122 (void) memset(&sc->sc_ibss.ibss_node_tb[i].node,
6127 sc->sc_ibss.node_number = 0;
6129 mutex_exit(&sc->sc_ibss.node_tb_lock);
6134 sc->sc_config.dev_type = RXON_DEV_TYPE_IBSS;
6136 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_PREAMBLE_MSK);
6137 sc->sc_config.filter_flags =
6142 sc->sc_config.assoc_id = 0;
6144 IEEE80211_ADDR_COPY(sc->sc_config.bssid, in->in_bssid);
6145 sc->sc_config.chan = LE_16(ieee80211_chan2ieee(ic,
6149 sc->sc_config.cck_basic_rates = 0x03;
6150 sc->sc_config.ofdm_basic_rates = 0;
6153 sc->sc_config.cck_basic_rates = 0;
6154 sc->sc_config.ofdm_basic_rates = 0x15;
6157 sc->sc_config.cck_basic_rates = 0x0f;
6158 sc->sc_config.ofdm_basic_rates = 0xff;
6161 sc->sc_config.flags &=
6166 sc->sc_config.flags |=
6171 sc->sc_config.flags |=
6175 sc->sc_config.filter_flags |=
6178 err = iwk_cmd(sc, REPLY_RXON, &sc->sc_config,
6193 iwk_sc_t *sc = (iwk_sc_t *)ic;
6198 if (sc->sc_assoc_id != in->in_associd) {
6202 in->in_associd, sc->sc_assoc_id);
6204 sc->sc_config.assoc_id = LE_16(in->in_associd & 0x3fff);
6210 sc->sc_config.flags &=
6215 sc->sc_config.flags |=
6219 sc->sc_config.flags |=
6222 sc->sc_config.filter_flags |=
6226 sc->sc_config.filter_flags |=
6231 sc->sc_config.chan, sc->sc_config.flags,
6232 sc->sc_config.filter_flags));
6234 err = iwk_cmd(sc, REPLY_RXON, &sc->sc_config,
6246 iwk_fast_recover(iwk_sc_t *sc)
6248 ieee80211com_t *ic = &sc->sc_ic;
6251 mutex_enter(&sc->sc_glock);
6254 bcopy(&sc->sc_config_save, &sc->sc_config,
6255 sizeof (sc->sc_config));
6258 sc->sc_config.assoc_id = 0;
6259 sc->sc_config.filter_flags &=
6262 if ((err = iwk_hw_set_before_auth(sc)) != 0) {
6265 mutex_exit(&sc->sc_glock);
6269 bcopy(&sc->sc_config_save, &sc->sc_config,
6270 sizeof (sc->sc_config));
6277 mutex_exit(&sc->sc_glock);
6282 sc->sc_tempera = iwk_curr_tempera(sc);
6288 err = iwk_tx_power_calibration(sc);
6292 mutex_exit(&sc->sc_glock);
6300 err = iwk_rx_sens_init(sc);
6304 mutex_exit(&sc->sc_glock);
6309 err = iwk_rxgain_diff_init(sc);
6313 mutex_exit(&sc->sc_glock);
6318 iwk_set_led(sc, 2, 0, 1);
6320 mutex_exit(&sc->sc_glock);
6338 sc->sc_flags &= ~IWK_F_HW_ERR_RECOVER;
6351 iwk_sc_t *sc = (iwk_sc_t *)ic;
6362 tx_beacon_p = &sc->sc_ibss.ibss_beacon.beacon_cmd;
6373 if (sc->sc_ibss.ibss_beacon.mp != NULL) {
6374 freemsg(sc->sc_ibss.ibss_beacon.mp);
6375 sc->sc_ibss.ibss_beacon.mp = NULL;
6378 sc->sc_ibss.ibss_beacon.mp =
6380 &sc->sc_ibss.ibss_beacon.iwk_boff);
6381 if (sc->sc_ibss.ibss_beacon.mp == NULL) {
6387 mp = sc->sc_ibss.ibss_beacon.mp;
6394 sc->sc_ibss.ibss_beacon.beacon_cmd_len =
6419 sc->sc_ibss.ibss_beacon.syncbeacon = 1;
6422 &sc->sc_ibss.ibss_beacon.iwk_boff,
6429 err = iwk_cmd(sc, REPLY_TX_BEACON,
6431 sc->sc_ibss.ibss_beacon.beacon_cmd_len,
6439 sc->sc_ibss.ibss_beacon.syncbeacon = 0;
6449 iwk_sc_t *sc = (iwk_sc_t *)ic;
6467 if (!sc->sc_ibss.ibss_node_tb[index].used) {
6476 sc->sc_ibss.node_number >= 25) {
6477 if (iwk_cmd(sc, REPLY_REMOVE_ALL_STA,
6485 sc->sc_ibss.ibss_node_tb[i].used = 0;
6486 (void) memset(&sc->sc_ibss.ibss_node_tb[i].node,
6490 sc->sc_ibss.node_number = 0;
6500 err = iwk_cmd(sc, REPLY_ADD_STA, &bc_node, sizeof (bc_node), 1);
6523 err = iwk_cmd(sc, REPLY_TX_LINK_QUALITY_CMD,
6541 ibss_node_p = &sc->sc_ibss.ibss_node_tb[index];
6553 err = iwk_cmd(sc, REPLY_ADD_STA, &ibss_node_p->node,
6564 sc->sc_ibss.node_number++;
6597 err = iwk_cmd(sc, REPLY_TX_LINK_QUALITY_CMD,