Lines Matching defs:sc
509 iwh_sc_t *sc;
526 sc = ddi_get_soft_state(iwh_soft_state_p,
528 ASSERT(sc != NULL);
530 if (sc->sc_flags & IWH_F_RUNNING) {
531 (void) iwh_init(sc);
534 atomic_and_32(&sc->sc_flags, ~IWH_F_SUSPEND);
552 sc = ddi_get_soft_state(iwh_soft_state_p, instance);
553 ASSERT(sc != NULL);
555 sc->sc_dip = dip;
560 err = ddi_regs_map_setup(dip, 0, &sc->sc_cfg_base, 0, 0,
561 &iwh_reg_accattr, &sc->sc_cfg_handle);
568 sc->sc_dev_id = ddi_get16(sc->sc_cfg_handle,
569 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_DEVID));
570 if ((sc->sc_dev_id != 0x4232) &&
571 (sc->sc_dev_id != 0x4235) &&
572 (sc->sc_dev_id != 0x4236) &&
573 (sc->sc_dev_id != 0x4237) &&
574 (sc->sc_dev_id != 0x423a) &&
575 (sc->sc_dev_id != 0x423b) &&
576 (sc->sc_dev_id != 0x423c) &&
577 (sc->sc_dev_id != 0x423d)) {
583 iwh_init_ht_conf(sc);
584 iwh_overwrite_11n_rateset(sc);
586 sc->sc_rev = ddi_get8(sc->sc_cfg_handle,
587 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_REVID));
592 ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base +
598 sc->sc_clsz = ddi_get16(sc->sc_cfg_handle,
599 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ));
600 if (!sc->sc_clsz) {
601 sc->sc_clsz = 16;
603 sc->sc_clsz = (sc->sc_clsz << 2);
605 sc->sc_dmabuf_sz = roundup(0x2000 + sizeof (struct ieee80211_frame) +
608 IEEE80211_WEP_CRCLEN), sc->sc_clsz);
613 err = ddi_regs_map_setup(dip, 1, &sc->sc_base,
614 0, 0, &iwh_reg_accattr, &sc->sc_handle);
624 sc->sc_hw_rev = IWH_READ(sc, CSR_HW_REV);
640 sc->sc_intr_htable = kmem_zalloc(sizeof (ddi_intr_handle_t), KM_SLEEP);
642 err = ddi_intr_alloc(dip, sc->sc_intr_htable, DDI_INTR_TYPE_FIXED, 0,
650 err = ddi_intr_get_pri(sc->sc_intr_htable[0], &sc->sc_intr_pri);
657 mutex_init(&sc->sc_glock, NULL, MUTEX_DRIVER,
658 DDI_INTR_PRI(sc->sc_intr_pri));
659 mutex_init(&sc->sc_tx_lock, NULL, MUTEX_DRIVER,
660 DDI_INTR_PRI(sc->sc_intr_pri));
661 mutex_init(&sc->sc_mt_lock, NULL, MUTEX_DRIVER,
662 DDI_INTR_PRI(sc->sc_intr_pri));
664 cv_init(&sc->sc_cmd_cv, NULL, CV_DRIVER, NULL);
665 cv_init(&sc->sc_put_seg_cv, NULL, CV_DRIVER, NULL);
666 cv_init(&sc->sc_ucode_cv, NULL, CV_DRIVER, NULL);
671 cv_init(&sc->sc_mt_cv, NULL, CV_DRIVER, NULL);
672 sc->sc_mf_thread = NULL;
673 sc->sc_mf_thread_switch = 0;
678 err = iwh_alloc_shared(sc);
685 (void) memset(sc->sc_shared, 0, sizeof (iwh_shared_t));
690 err = iwh_alloc_kw(sc);
697 err = iwh_reset_hw(sc);
707 err = iwh_preinit(sc);
717 err = iwh_eep_load(sc);
724 if (IWH_READ_EEP_SHORT(sc, EEP_VERSION) < 0x011a) {
733 iwh_get_mac_from_eep(sc);
738 sc->sc_eep_calib = (struct iwh_eep_calibration *)
739 iwh_eep_addr_trans(sc, EEP_CALIBRATION);
744 err = iwh_ring_init(sc);
751 if ((0x423c == sc->sc_dev_id) || (0x423d == sc->sc_dev_id)) {
752 sc->sc_hdr = (iwh_firmware_hdr_t *)iwh_fw_5150_bin;
754 sc->sc_hdr = (iwh_firmware_hdr_t *)iwh_fw_5000_bin;
760 err = iwh_alloc_fw_dma(sc);
771 ic = &sc->sc_ic;
793 if (sc->sc_ht_conf.ht_support) {
816 if (sc->sc_ht_conf.cap & HT_CAP_SUP_WIDTH) {
843 iwh_overwrite_ic_default(sc);
855 err = ddi_intr_add_softint(dip, &sc->sc_soft_hdl, DDI_INTR_SOFTPRI_MAX,
856 iwh_rx_softintr, (caddr_t)sc);
863 err = ddi_intr_add_handler(sc->sc_intr_htable[0], iwh_intr,
864 (caddr_t)sc, NULL);
871 err = ddi_intr_enable(sc->sc_intr_htable[0]);
896 macp->m_driver = sc;
936 sc->sc_mf_thread_switch = 1;
937 if (NULL == sc->sc_mf_thread) {
938 sc->sc_mf_thread = thread_create((caddr_t)NULL, 0,
939 iwh_thread, sc, 0, &p0, TS_RUN, minclsyspri);
942 atomic_or_32(&sc->sc_flags, IWH_F_ATTACHED);
947 (void) ddi_intr_disable(sc->sc_intr_htable[0]);
950 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]);
953 (void) ddi_intr_remove_softint(sc->sc_soft_hdl);
954 sc->sc_soft_hdl = NULL;
960 iwh_free_fw_dma(sc);
963 iwh_ring_free(sc);
966 iwh_free_kw(sc);
969 iwh_free_shared(sc);
972 iwh_destroy_locks(sc);
975 (void) ddi_intr_free(sc->sc_intr_htable[0]);
978 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t));
981 ddi_regs_map_free(&sc->sc_handle);
984 ddi_regs_map_free(&sc->sc_cfg_handle);
996 iwh_sc_t *sc;
1000 sc = ddi_get_soft_state(iwh_soft_state_p, ddi_get_instance(dip));
1001 ASSERT(sc != NULL);
1002 ic = &sc->sc_ic;
1009 atomic_and_32(&sc->sc_flags, ~IWH_F_HW_ERR_RECOVER);
1010 atomic_and_32(&sc->sc_flags, ~IWH_F_RATE_AUTO_CTL);
1012 atomic_or_32(&sc->sc_flags, IWH_F_SUSPEND);
1014 if (sc->sc_flags & IWH_F_RUNNING) {
1016 iwh_stop(sc);
1027 if (!(sc->sc_flags & IWH_F_ATTACHED)) {
1034 sc->sc_mf_thread_switch = 0;
1036 mutex_enter(&sc->sc_mt_lock);
1037 while (sc->sc_mf_thread != NULL) {
1038 if (cv_wait_sig(&sc->sc_mt_cv, &sc->sc_mt_lock) == 0) {
1042 mutex_exit(&sc->sc_mt_lock);
1044 err = mac_disable(sc->sc_ic.ic_mach);
1052 iwh_stop(sc);
1059 iwh_release_calib_buffer(sc);
1064 (void) mac_unregister(sc->sc_ic.ic_mach);
1066 mutex_enter(&sc->sc_glock);
1067 iwh_free_fw_dma(sc);
1068 iwh_ring_free(sc);
1069 iwh_free_kw(sc);
1070 iwh_free_shared(sc);
1071 mutex_exit(&sc->sc_glock);
1073 (void) ddi_intr_disable(sc->sc_intr_htable[0]);
1074 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]);
1075 (void) ddi_intr_free(sc->sc_intr_htable[0]);
1076 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t));
1078 (void) ddi_intr_remove_softint(sc->sc_soft_hdl);
1079 sc->sc_soft_hdl = NULL;
1084 ieee80211_detach(&sc->sc_ic);
1086 iwh_destroy_locks(sc);
1088 ddi_regs_map_free(&sc->sc_handle);
1089 ddi_regs_map_free(&sc->sc_cfg_handle);
1100 iwh_destroy_locks(iwh_sc_t *sc)
1102 cv_destroy(&sc->sc_mt_cv);
1103 cv_destroy(&sc->sc_cmd_cv);
1104 cv_destroy(&sc->sc_put_seg_cv);
1105 cv_destroy(&sc->sc_ucode_cv);
1106 mutex_destroy(&sc->sc_mt_lock);
1107 mutex_destroy(&sc->sc_tx_lock);
1108 mutex_destroy(&sc->sc_glock);
1115 iwh_alloc_dma_mem(iwh_sc_t *sc, size_t memsize,
1125 err = ddi_dma_alloc_handle(sc->sc_dip, dma_attr_p,
1192 iwh_alloc_fw_dma(iwh_sc_t *sc)
1206 t = (char *)(sc->sc_hdr + 1);
1207 err = iwh_alloc_dma_mem(sc, LE_32(sc->sc_hdr->textsz),
1210 &sc->sc_dma_fw_text);
1217 dma_p = &sc->sc_dma_fw_text;
1224 bcopy(t, dma_p->mem_va, LE_32(sc->sc_hdr->textsz));
1229 t += LE_32(sc->sc_hdr->textsz);
1230 err = iwh_alloc_dma_mem(sc, LE_32(sc->sc_hdr->datasz),
1233 &sc->sc_dma_fw_data);
1240 dma_p = &sc->sc_dma_fw_data;
1247 bcopy(t, dma_p->mem_va, LE_32(sc->sc_hdr->datasz));
1249 err = iwh_alloc_dma_mem(sc, LE_32(sc->sc_hdr->datasz),
1252 &sc->sc_dma_fw_data_bak);
1259 dma_p = &sc->sc_dma_fw_data_bak;
1267 bcopy(t, dma_p->mem_va, LE_32(sc->sc_hdr->datasz));
1272 t += LE_32(sc->sc_hdr->datasz);
1273 err = iwh_alloc_dma_mem(sc, LE_32(sc->sc_hdr->init_textsz),
1276 &sc->sc_dma_fw_init_text);
1283 dma_p = &sc->sc_dma_fw_init_text;
1291 bcopy(t, dma_p->mem_va, LE_32(sc->sc_hdr->init_textsz));
1296 t += LE_32(sc->sc_hdr->init_textsz);
1297 err = iwh_alloc_dma_mem(sc, LE_32(sc->sc_hdr->init_datasz),
1300 &sc->sc_dma_fw_init_data);
1307 dma_p = &sc->sc_dma_fw_init_data;
1315 bcopy(t, dma_p->mem_va, LE_32(sc->sc_hdr->init_datasz));
1317 sc->sc_boot = t + LE_32(sc->sc_hdr->init_datasz);
1324 iwh_free_fw_dma(iwh_sc_t *sc)
1326 iwh_free_dma_mem(&sc->sc_dma_fw_text);
1327 iwh_free_dma_mem(&sc->sc_dma_fw_data);
1328 iwh_free_dma_mem(&sc->sc_dma_fw_data_bak);
1329 iwh_free_dma_mem(&sc->sc_dma_fw_init_text);
1330 iwh_free_dma_mem(&sc->sc_dma_fw_init_data);
1337 iwh_alloc_shared(iwh_sc_t *sc)
1347 err = iwh_alloc_dma_mem(sc, sizeof (iwh_shared_t),
1350 &sc->sc_dma_sh);
1355 sc->sc_shared = (iwh_shared_t *)sc->sc_dma_sh.mem_va;
1358 dma_p = &sc->sc_dma_sh;
1368 iwh_free_shared(sc);
1373 iwh_free_shared(iwh_sc_t *sc)
1375 iwh_free_dma_mem(&sc->sc_dma_sh);
1382 iwh_alloc_kw(iwh_sc_t *sc)
1392 err = iwh_alloc_dma_mem(sc, IWH_KW_SIZE,
1395 &sc->sc_dma_kw);
1401 dma_p = &sc->sc_dma_kw;
1411 iwh_free_kw(sc);
1416 iwh_free_kw(iwh_sc_t *sc)
1418 iwh_free_dma_mem(&sc->sc_dma_kw);
1425 iwh_alloc_rx_ring(iwh_sc_t *sc)
1434 ring = &sc->sc_rxq;
1440 err = iwh_alloc_dma_mem(sc, RX_QUEUE_SIZE * sizeof (uint32_t),
1465 err = iwh_alloc_dma_mem(sc, sc->sc_dmabuf_sz,
1497 iwh_free_rx_ring(sc);
1505 iwh_reset_rx_ring(iwh_sc_t *sc)
1509 iwh_mac_access_enter(sc);
1510 IWH_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
1512 if (IWH_READ(sc, FH_MEM_RSSR_RX_STATUS_REG) & (1 << 24)) {
1523 iwh_mac_access_exit(sc);
1525 sc->sc_rxq.cur = 0;
1529 iwh_free_rx_ring(iwh_sc_t *sc)
1534 if (sc->sc_rxq.data[i].dma_data.dma_hdl) {
1535 IWH_DMA_SYNC(sc->sc_rxq.data[i].dma_data,
1539 iwh_free_dma_mem(&sc->sc_rxq.data[i].dma_data);
1542 if (sc->sc_rxq.dma_desc.dma_hdl) {
1543 IWH_DMA_SYNC(sc->sc_rxq.dma_desc, DDI_DMA_SYNC_FORDEV);
1546 iwh_free_dma_mem(&sc->sc_rxq.dma_desc);
1553 iwh_alloc_tx_ring(iwh_sc_t *sc, iwh_tx_ring_t *ring,
1576 err = iwh_alloc_dma_mem(sc,
1602 err = iwh_alloc_dma_mem(sc,
1639 err = iwh_alloc_dma_mem(sc, sc->sc_dmabuf_sz,
1678 iwh_reset_tx_ring(iwh_sc_t *sc, iwh_tx_ring_t *ring)
1683 iwh_mac_access_enter(sc);
1685 IWH_WRITE(sc, IWH_FH_TCSR_CHNL_TX_CONFIG_REG(ring->qid), 0);
1687 if (IWH_READ(sc, IWH_FH_TSSR_TX_STATUS_REG) &
1702 iwh_mac_access_exit(sc);
1707 if (!(sc->sc_flags & IWH_F_QUIESCED)) {
1750 iwh_ring_init(iwh_sc_t *sc)
1759 err = iwh_alloc_tx_ring(sc, &sc->sc_txq[i], TFD_TX_CMD_SLOTS,
1769 err = iwh_alloc_tx_ring(sc, &sc->sc_txq[IWH_CMD_QUEUE_NUM],
1775 err = iwh_alloc_rx_ring(sc);
1785 iwh_ring_free(iwh_sc_t *sc)
1789 iwh_free_rx_ring(sc);
1791 iwh_free_tx_ring(&sc->sc_txq[i]);
1852 iwh_sc_t *sc;
1863 sc = (iwh_sc_t *)ic;
1867 mutex_enter(&sc->sc_glock);
1873 atomic_or_32(&sc->sc_flags, IWH_F_SCANNING);
1874 iwh_set_led(sc, 2, 10, 2);
1880 sc->sc_config.assoc_id = 0;
1881 sc->sc_config.filter_flags &=
1887 LE_16(sc->sc_config.chan),
1888 LE_32(sc->sc_config.flags),
1889 LE_32(sc->sc_config.filter_flags)));
1891 err = iwh_cmd(sc, REPLY_RXON, &sc->sc_config,
1896 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
1897 mutex_exit(&sc->sc_glock);
1907 err = iwh_cmd(sc, REPLY_ADD_STA, &node,
1912 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
1913 mutex_exit(&sc->sc_glock);
1918 mutex_exit(&sc->sc_glock);
1920 err = sc->sc_newstate(ic, nstate, arg);
1921 mutex_enter(&sc->sc_glock);
1922 if ((err != 0) || ((err = iwh_scan(sc)) != 0)) {
1925 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
1928 mutex_exit(&sc->sc_glock);
1933 sc->sc_clk = 0;
1938 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
1944 sc->sc_config.assoc_id = 0;
1945 sc->sc_config.filter_flags &= ~LE_32(RXON_FILTER_ASSOC_MSK);
1952 if ((err = iwh_hw_set_before_auth(sc)) != 0) {
1955 mutex_exit(&sc->sc_glock);
1962 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
1969 iwh_set_led(sc, 2, 10, 10);
1976 err = iwh_run_state_config(sc);
1980 mutex_exit(&sc->sc_glock);
1988 (sc->sc_ht_conf.ht_support) &&
1998 (sc->sc_ht_conf.tx_support_mcs[r/8] &
2001 atomic_or_32(&sc->sc_flags,
2008 atomic_or_32(&sc->sc_flags,
2021 atomic_and_32(&sc->sc_flags,
2029 iwh_set_led(sc, 2, 0, 1);
2034 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
2039 iwh_set_led(sc, 2, 1, 0);
2044 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
2049 mutex_exit(&sc->sc_glock);
2051 return (sc->sc_newstate(ic, nstate, arg));
2058 iwh_mac_access_enter(iwh_sc_t *sc)
2063 tmp = IWH_READ(sc, CSR_GP_CNTRL);
2064 IWH_WRITE(sc, CSR_GP_CNTRL,
2071 if ((IWH_READ(sc, CSR_GP_CNTRL) &
2092 iwh_mac_access_exit(iwh_sc_t *sc)
2094 uint32_t tmp = IWH_READ(sc, CSR_GP_CNTRL);
2095 IWH_WRITE(sc, CSR_GP_CNTRL,
2102 * iwh_mem_read(iwh_sc_t *sc, uint32_t addr)
2104 * IWH_WRITE(sc, HBUS_TARG_MEM_RADDR, addr);
2105 * return (IWH_READ(sc, HBUS_TARG_MEM_RDAT));
2113 iwh_mem_write(iwh_sc_t *sc, uint32_t addr, uint32_t data)
2115 IWH_WRITE(sc, HBUS_TARG_MEM_WADDR, addr);
2116 IWH_WRITE(sc, HBUS_TARG_MEM_WDAT, data);
2123 iwh_reg_read(iwh_sc_t *sc, uint32_t addr)
2125 IWH_WRITE(sc, HBUS_TARG_PRPH_RADDR, addr | (3 << 24));
2126 return (IWH_READ(sc, HBUS_TARG_PRPH_RDAT));
2133 iwh_reg_write(iwh_sc_t *sc, uint32_t addr, uint32_t data)
2135 IWH_WRITE(sc, HBUS_TARG_PRPH_WADDR, addr | (3 << 24));
2136 IWH_WRITE(sc, HBUS_TARG_PRPH_WDAT, data);
2148 iwh_load_init_firmware(iwh_sc_t *sc)
2153 atomic_and_32(&sc->sc_flags, ~IWH_F_PUT_SEG);
2158 err = iwh_put_seg_fw(sc, sc->sc_dma_fw_init_text.cookie.dmac_address,
2159 RTC_INST_LOWER_BOUND, sc->sc_dma_fw_init_text.cookie.dmac_size);
2171 while (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2172 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2177 if (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2183 atomic_and_32(&sc->sc_flags, ~IWH_F_PUT_SEG);
2188 err = iwh_put_seg_fw(sc, sc->sc_dma_fw_init_data.cookie.dmac_address,
2189 RTC_DATA_LOWER_BOUND, sc->sc_dma_fw_init_data.cookie.dmac_size);
2201 while (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2202 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2207 if (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2213 atomic_and_32(&sc->sc_flags, ~IWH_F_PUT_SEG);
2219 iwh_load_run_firmware(iwh_sc_t *sc)
2224 atomic_and_32(&sc->sc_flags, ~IWH_F_PUT_SEG);
2229 err = iwh_put_seg_fw(sc, sc->sc_dma_fw_text.cookie.dmac_address,
2230 RTC_INST_LOWER_BOUND, sc->sc_dma_fw_text.cookie.dmac_size);
2242 while (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2243 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2248 if (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2254 atomic_and_32(&sc->sc_flags, ~IWH_F_PUT_SEG);
2259 err = iwh_put_seg_fw(sc, sc->sc_dma_fw_data_bak.cookie.dmac_address,
2260 RTC_DATA_LOWER_BOUND, sc->sc_dma_fw_data.cookie.dmac_size);
2272 while (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2273 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2278 if (!(sc->sc_flags & IWH_F_PUT_SEG)) {
2284 atomic_and_32(&sc->sc_flags, ~IWH_F_PUT_SEG);
2294 iwh_rx_phy_intr(iwh_sc_t *sc, iwh_rx_desc_t *desc)
2297 sc->sc_rx_phy_res.flag = 1;
2299 bcopy((uint8_t *)(desc + 1), sc->sc_rx_phy_res.buf,
2308 iwh_rx_mpdu_intr(iwh_sc_t *sc, iwh_rx_desc_t *desc)
2310 ieee80211com_t *ic = &sc->sc_ic;
2312 iwh_rx_ring_t *ring = &sc->sc_rxq;
2329 stat = (iwh_rx_phy_res_t *)sc->sc_rx_phy_res.buf;
2377 if ((len < 16) || (len > sc->sc_dmabuf_sz)) {
2392 sc->sc_rx_err++;
2400 sc->sc_assoc_id = *((uint16_t *)(wh + 1) + 2);
2403 sc->sc_assoc_id));
2423 sc->sc_rx_nobuf++;
2438 iwh_tx_intr(iwh_sc_t *sc, iwh_rx_desc_t *desc)
2440 ieee80211com_t *ic = &sc->sc_ic;
2441 iwh_tx_ring_t *ring = &sc->sc_txq[desc->hdr.qid & 0x3];
2457 sc->sc_tx_retries++;
2460 sc->sc_tx_retries));
2463 mutex_enter(&sc->sc_mt_lock);
2464 sc->sc_tx_timer = 0;
2465 mutex_exit(&sc->sc_mt_lock);
2467 mutex_enter(&sc->sc_tx_lock);
2474 if ((sc->sc_need_reschedule) && (ring->queued <= (ring->count >> 3))) {
2475 sc->sc_need_reschedule = 0;
2476 mutex_exit(&sc->sc_tx_lock);
2478 mutex_enter(&sc->sc_tx_lock);
2481 mutex_exit(&sc->sc_tx_lock);
2488 iwh_cmd_intr(iwh_sc_t *sc, iwh_rx_desc_t *desc)
2494 if (sc->sc_cmd_accum > 0) {
2495 sc->sc_cmd_accum--;
2499 mutex_enter(&sc->sc_glock);
2501 sc->sc_cmd_flag = SC_CMD_FLG_DONE;
2503 cv_signal(&sc->sc_cmd_cv);
2505 mutex_exit(&sc->sc_glock);
2517 iwh_ucode_alive(iwh_sc_t *sc, iwh_rx_desc_t *desc)
2523 struct iwh_calib_results *res_p = &sc->sc_calib_results;
2547 bcopy(ar, &sc->sc_card_alive_init,
2553 mutex_enter(&sc->sc_glock);
2555 rv = iwh_alive_common(sc);
2559 mutex_exit(&sc->sc_glock);
2573 rv = iwh_cmd(sc, CALIBRATION_CFG_CMD, &cmd, sizeof (cmd), 1);
2577 mutex_exit(&sc->sc_glock);
2581 mutex_exit(&sc->sc_glock);
2588 bcopy(ar, &sc->sc_card_alive_run,
2591 mutex_enter(&sc->sc_glock);
2596 rv = iwh_alive_common(sc);
2600 mutex_exit(&sc->sc_glock);
2608 rv = iwh_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
2614 mutex_exit(&sc->sc_glock);
2625 rv = iwh_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
2631 mutex_exit(&sc->sc_glock);
2642 rv = iwh_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
2649 mutex_exit(&sc->sc_glock);
2660 rv = iwh_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
2667 mutex_exit(&sc->sc_glock);
2678 rv = iwh_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
2685 mutex_exit(&sc->sc_glock);
2692 atomic_or_32(&sc->sc_flags, IWH_F_FW_INIT);
2693 cv_signal(&sc->sc_ucode_cv);
2695 mutex_exit(&sc->sc_glock);
2708 iwh_sc_t *sc;
2717 sc = (iwh_sc_t *)arg;
2718 ic = &sc->sc_ic;
2724 index = (sc->sc_shared->val0) & 0xfff;
2726 while (sc->sc_rxq.cur != index) {
2727 data = &sc->sc_rxq.data[sc->sc_rxq.cur];
2733 index, sc->sc_rxq.cur, desc->hdr.qid, desc->hdr.idx,
2742 iwh_cmd_intr(sc, desc);
2747 iwh_rx_phy_intr(sc, desc);
2751 iwh_rx_mpdu_intr(sc, desc);
2755 iwh_tx_intr(sc, desc);
2759 iwh_ucode_alive(sc, desc);
2779 sc->sc_ostate = sc->sc_ic.ic_state;
2780 ieee80211_new_state(&sc->sc_ic,
2782 atomic_or_32(&sc->sc_flags,
2813 sc->sc_scan_pending++;
2826 iwh_save_calib_result(sc, desc);
2830 mutex_enter(&sc->sc_glock);
2831 atomic_or_32(&sc->sc_flags, IWH_F_FW_INIT);
2832 cv_signal(&sc->sc_ucode_cv);
2833 mutex_exit(&sc->sc_glock);
2841 sc->sc_rxq.cur = (sc->sc_rxq.cur + 1) % RX_QUEUE_SIZE;
2849 IWH_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, index & (~7));
2854 IWH_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);
2866 iwh_sc_t *sc;
2872 sc = (iwh_sc_t *)arg;
2874 r = IWH_READ(sc, CSR_INT);
2882 rfh = IWH_READ(sc, CSR_FH_INT_STATUS);
2890 IWH_WRITE(sc, CSR_INT_MASK, 0);
2895 IWH_WRITE(sc, CSR_INT, r);
2896 IWH_WRITE(sc, CSR_FH_INT_STATUS, rfh);
2901 iwh_stop(sc);
2902 sc->sc_ostate = sc->sc_ic.ic_state;
2907 if (!IWH_CHK_FAST_RECOVER(sc)) {
2908 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1);
2911 atomic_or_32(&sc->sc_flags, IWH_F_HW_ERR_RECOVER);
2916 uint32_t tmp = IWH_READ(sc, CSR_GP_CNTRL);
2924 (void) ddi_intr_trigger_softint(sc->sc_soft_hdl, NULL);
2929 mutex_enter(&sc->sc_glock);
2930 atomic_or_32(&sc->sc_flags, IWH_F_PUT_SEG);
2931 cv_signal(&sc->sc_put_seg_cv);
2932 mutex_exit(&sc->sc_glock);
2945 IWH_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);
3024 iwh_sc_t *sc;
3031 sc = (iwh_sc_t *)arg;
3032 ic = &sc->sc_ic;
3034 if (sc->sc_flags & IWH_F_SUSPEND) {
3044 if ((sc->sc_flags & IWH_F_HW_ERR_RECOVER) &&
3045 IWH_CHK_FAST_RECOVER(sc)) {
3070 iwh_sc_t *sc;
3091 sc = (iwh_sc_t *)ic;
3093 if (sc->sc_flags & IWH_F_SUSPEND) {
3116 sc->sc_tx_err++;
3139 sc->sc_tx_err++;
3159 mutex_enter(&sc->sc_tx_lock);
3160 ring = &sc->sc_txq[txq_id];
3174 sc->sc_need_reschedule = 1;
3175 mutex_exit(&sc->sc_tx_lock);
3181 sc->sc_tx_nobuf++;
3188 mutex_exit(&sc->sc_tx_lock);
3198 mutex_enter(&sc->sc_tx_lock);
3200 if ((sc->sc_need_reschedule) && (ring->queued <= 0)) {
3201 sc->sc_need_reschedule = 0;
3202 mutex_exit(&sc->sc_tx_lock);
3204 mutex_enter(&sc->sc_tx_lock);
3206 mutex_exit(&sc->sc_tx_lock);
3250 sc->sc_tx_err++;
3252 mutex_enter(&sc->sc_tx_lock);
3254 if ((sc->sc_need_reschedule) && (ring->queued <= 0)) {
3255 sc->sc_need_reschedule = 0;
3256 mutex_exit(&sc->sc_tx_lock);
3258 mutex_enter(&sc->sc_tx_lock);
3260 mutex_exit(&sc->sc_tx_lock);
3335 (sc->sc_ht_conf.ht_support)) {
3377 (sc->sc_ht_conf.ht_support) &&
3426 mutex_enter(&sc->sc_tx_lock);
3449 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3453 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3462 IWH_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->desc_cur);
3464 mutex_exit(&sc->sc_tx_lock);
3475 mutex_enter(&sc->sc_mt_lock);
3476 if (0 == sc->sc_tx_timer) {
3477 sc->sc_tx_timer = 4;
3479 mutex_exit(&sc->sc_mt_lock);
3491 iwh_sc_t *sc;
3498 sc = (iwh_sc_t *)arg;
3499 ic = &sc->sc_ic;
3512 if (sc->sc_flags & IWH_F_RUNNING) {
3513 iwh_m_stop(sc);
3514 (void) iwh_m_start(sc);
3529 iwh_sc_t *sc;
3535 sc = (iwh_sc_t *)arg;
3537 err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num,
3547 iwh_sc_t *sc = (iwh_sc_t *)arg;
3549 ieee80211_propinfo(&sc->sc_ic, pr_name, wldp_pr_num, mph);
3556 iwh_sc_t *sc;
3563 sc = (iwh_sc_t *)arg;
3564 ic = &sc->sc_ic;
3571 if (sc->sc_flags & IWH_F_RUNNING) {
3572 iwh_m_stop(sc);
3573 (void) iwh_m_start(sc);
3589 iwh_sc_t *sc;
3596 sc = (iwh_sc_t *)arg;
3597 ic = &sc->sc_ic;
3599 mutex_enter(&sc->sc_glock);
3610 *val = sc->sc_tx_nobuf;
3614 *val = sc->sc_rx_nobuf;
3618 *val = sc->sc_rx_err;
3639 *val = sc->sc_tx_err;
3643 *val = sc->sc_tx_retries;
3656 mutex_exit(&sc->sc_glock);
3660 mutex_exit(&sc->sc_glock);
3664 mutex_exit(&sc->sc_glock);
3675 iwh_sc_t *sc;
3682 sc = (iwh_sc_t *)arg;
3683 ic = &sc->sc_ic;
3685 err = iwh_init(sc);
3692 atomic_or_32(&sc->sc_flags, IWH_F_HW_ERR_RECOVER);
3698 atomic_or_32(&sc->sc_flags, IWH_F_RUNNING);
3709 iwh_sc_t *sc;
3715 sc = (iwh_sc_t *)arg;
3716 ic = &sc->sc_ic;
3718 iwh_stop(sc);
3723 iwh_release_calib_buffer(sc);
3727 atomic_and_32(&sc->sc_flags, ~IWH_F_HW_ERR_RECOVER);
3728 atomic_and_32(&sc->sc_flags, ~IWH_F_RATE_AUTO_CTL);
3730 atomic_and_32(&sc->sc_flags, ~IWH_F_RUNNING);
3731 atomic_and_32(&sc->sc_flags, ~IWH_F_SCANNING);
3740 iwh_sc_t *sc;
3747 sc = (iwh_sc_t *)arg;
3748 ic = &sc->sc_ic;
3752 mutex_enter(&sc->sc_glock);
3753 err = iwh_config(sc);
3754 mutex_exit(&sc->sc_glock);
3784 iwh_thread(iwh_sc_t *sc)
3786 ieee80211com_t *ic = &sc->sc_ic;
3794 while (sc->sc_mf_thread_switch) {
3795 tmp = IWH_READ(sc, CSR_GP_CNTRL);
3797 atomic_and_32(&sc->sc_flags, ~IWH_F_RADIO_OFF);
3799 atomic_or_32(&sc->sc_flags, IWH_F_RADIO_OFF);
3805 if (sc->sc_flags & IWH_F_RADIO_OFF) {
3814 (sc->sc_flags & IWH_F_HW_ERR_RECOVER)) {
3819 iwh_stop(sc);
3821 if (IWH_CHK_FAST_RECOVER(sc)) {
3825 bcopy(&sc->sc_config, &sc->sc_config_save,
3826 sizeof (sc->sc_config));
3832 err = iwh_init(sc);
3842 atomic_or_32(&sc->sc_flags, IWH_F_RUNNING);
3846 if (!IWH_CHK_FAST_RECOVER(sc) ||
3847 iwh_fast_recover(sc) != IWH_SUCCESS) {
3848 atomic_and_32(&sc->sc_flags,
3852 if (sc->sc_ostate != IEEE80211_S_INIT) {
3860 (sc->sc_flags & IWH_F_SCANNING) && sc->sc_scan_pending) {
3864 sc->sc_scan_pending--;
3873 (sc->sc_flags & IWH_F_RATE_AUTO_CTL)) {
3875 if (clk > sc->sc_clk + drv_usectohz(1000000)) {
3876 iwh_amrr_timeout(sc);
3889 mutex_enter(&sc->sc_mt_lock);
3890 if (sc->sc_tx_timer) {
3893 sc->sc_tx_timer--;
3894 if (0 == sc->sc_tx_timer) {
3895 atomic_or_32(&sc->sc_flags,
3897 sc->sc_ostate = IEEE80211_S_RUN;
3905 mutex_exit(&sc->sc_mt_lock);
3908 mutex_enter(&sc->sc_mt_lock);
3909 sc->sc_mf_thread = NULL;
3910 cv_signal(&sc->sc_mt_cv);
3911 mutex_exit(&sc->sc_mt_lock);
3918 iwh_cmd(iwh_sc_t *sc, int code, const void *buf, int size, int async)
3920 iwh_tx_ring_t *ring = &sc->sc_txq[IWH_CMD_QUEUE_NUM];
3925 ASSERT(mutex_owned(&sc->sc_glock));
3945 sc->sc_cmd_accum++;
3951 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3954 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3958 IWH_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3966 while (sc->sc_cmd_flag != SC_CMD_FLG_DONE) {
3967 if (cv_timedwait(&sc->sc_cmd_cv,
3968 &sc->sc_glock, clk) < 0) {
3973 if (SC_CMD_FLG_DONE == sc->sc_cmd_flag) {
3974 sc->sc_cmd_flag = SC_CMD_FLG_NONE;
3977 sc->sc_cmd_flag = SC_CMD_FLG_NONE;
3987 iwh_set_led(iwh_sc_t *sc, uint8_t id, uint8_t off, uint8_t on)
3996 (void) iwh_cmd(sc, REPLY_LEDS_CMD, &led, sizeof (led), 1);
4003 iwh_hw_set_before_auth(iwh_sc_t *sc)
4005 ieee80211com_t *ic = &sc->sc_ic;
4013 IEEE80211_ADDR_COPY(sc->sc_config.bssid, in->in_bssid);
4014 sc->sc_config.chan = LE_16(ieee80211_chan2ieee(ic, in->in_chan));
4018 sc->sc_config.ofdm_ht_triple_stream_basic_rates = 0;
4019 sc->sc_config.ofdm_ht_dual_stream_basic_rates = 0;
4020 sc->sc_config.ofdm_ht_single_stream_basic_rates = 0;
4023 sc->sc_config.cck_basic_rates = 0x03;
4024 sc->sc_config.ofdm_basic_rates = 0;
4027 sc->sc_config.cck_basic_rates = 0;
4028 sc->sc_config.ofdm_basic_rates = 0x15;
4030 sc->sc_config.cck_basic_rates = 0x0f;
4031 sc->sc_config.ofdm_basic_rates = 0xff;
4035 sc->sc_config.flags &= ~LE_32(RXON_FLG_SHORT_PREAMBLE_MSK |
4039 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_SLOT_MSK);
4041 sc->sc_config.flags &= LE_32(~RXON_FLG_SHORT_SLOT_MSK);
4045 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_PREAMBLE_MSK);
4047 sc->sc_config.flags &= LE_32(~RXON_FLG_SHORT_PREAMBLE_MSK);
4054 LE_16(sc->sc_config.chan), LE_32(sc->sc_config.flags),
4055 LE_32(sc->sc_config.filter_flags),
4056 sc->sc_config.cck_basic_rates, sc->sc_config.ofdm_basic_rates,
4057 sc->sc_config.bssid[0], sc->sc_config.bssid[1],
4058 sc->sc_config.bssid[2], sc->sc_config.bssid[3],
4059 sc->sc_config.bssid[4], sc->sc_config.bssid[5]));
4061 err = iwh_cmd(sc, REPLY_RXON, &sc->sc_config,
4065 "failed to config chan%d\n", sc->sc_config.chan);
4069 if ((sc->sc_dev_id != 0x423c) &&
4070 (sc->sc_dev_id != 0x423d)) {
4071 err = iwh_tx_power_table(sc, 1);
4080 err = iwh_add_ap_sta(sc);
4085 if ((sc->sc_dev_id != 0x423c) &&
4086 (sc->sc_dev_id != 0x423d)) {
4090 err = iwh_ap_lq(sc);
4103 iwh_scan(iwh_sc_t *sc)
4105 ieee80211com_t *ic = &sc->sc_ic;
4106 iwh_tx_ring_t *ring = &sc->sc_txq[IWH_CMD_QUEUE_NUM];
4269 sc->sc_shared->queues_byte_cnt_tbls[ring->qid]
4272 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
4280 IWH_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
4289 iwh_config(iwh_sc_t *sc)
4291 ieee80211com_t *ic = &sc->sc_ic;
4306 err = iwh_cmd(sc, POWER_TABLE_CMD, &powertable,
4321 err = iwh_cmd(sc, REPLY_BT_CONFIG, &bt,
4332 (void) memset(&sc->sc_config, 0, sizeof (iwh_rxon_cmd_t));
4333 IEEE80211_ADDR_COPY(sc->sc_config.node_addr, ic->ic_macaddr);
4334 IEEE80211_ADDR_COPY(sc->sc_config.wlap_bssid, ic->ic_macaddr);
4335 sc->sc_config.chan = LE_16(ieee80211_chan2ieee(ic, ic->ic_curchan));
4336 sc->sc_config.flags = LE_32(RXON_FLG_BAND_24G_MSK);
4337 sc->sc_config.flags &= LE_32(~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
4342 sc->sc_config.dev_type = RXON_DEV_TYPE_ESS;
4343 sc->sc_config.filter_flags |= LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
4350 sc->sc_config.dev_type = RXON_DEV_TYPE_IBSS;
4352 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_PREAMBLE_MSK);
4353 sc->sc_config.filter_flags = LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
4359 sc->sc_config.dev_type = RXON_DEV_TYPE_AP;
4363 sc->sc_config.dev_type = RXON_DEV_TYPE_SNIFFER;
4364 sc->sc_config.filter_flags |= LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
4372 sc->sc_config.cck_basic_rates = 0x0f;
4377 sc->sc_config.ofdm_basic_rates = 0xff;
4382 switch (sc->sc_ht_conf.rx_stream_count) {
4384 sc->sc_config.ofdm_ht_triple_stream_basic_rates = 0xff;
4385 sc->sc_config.ofdm_ht_dual_stream_basic_rates = 0xff;
4386 sc->sc_config.ofdm_ht_single_stream_basic_rates = 0xff;
4389 sc->sc_config.ofdm_ht_dual_stream_basic_rates = 0xff;
4390 sc->sc_config.ofdm_ht_single_stream_basic_rates = 0xff;
4393 sc->sc_config.ofdm_ht_single_stream_basic_rates = 0xff;
4398 sc->sc_ht_conf.rx_stream_count);
4405 iwh_config_rxon_chain(sc);
4407 err = iwh_cmd(sc, REPLY_RXON, &sc->sc_config,
4422 err = iwh_cmd(sc, REPLY_REMOVE_STA, &rm_sta, sizeof (iwh_rem_sta_t), 0);
4429 if ((sc->sc_dev_id != 0x423c) &&
4430 (sc->sc_dev_id != 0x423d)) {
4434 err = iwh_tx_power_table(sc, 0);
4449 err = iwh_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 0);
4456 if ((sc->sc_dev_id != 0x423c) &&
4457 (sc->sc_dev_id != 0x423d)) {
4475 err = iwh_cmd(sc, REPLY_TX_LINK_QUALITY_CMD, &link_quality,
4498 iwh_sc_t *sc;
4500 sc = ddi_get_soft_state(iwh_soft_state_p, ddi_get_instance(dip));
4501 if (sc == NULL) {
4516 atomic_or_32(&sc->sc_flags, IWH_F_QUIESCED);
4521 iwh_stop(sc);
4527 iwh_stop_master(iwh_sc_t *sc)
4532 tmp = IWH_READ(sc, CSR_RESET);
4533 IWH_WRITE(sc, CSR_RESET, tmp | CSR_RESET_REG_FLAG_STOP_MASTER);
4535 tmp = IWH_READ(sc, CSR_GP_CNTRL);
4542 if (IWH_READ(sc, CSR_RESET) &
4558 iwh_power_up(iwh_sc_t *sc)
4562 iwh_mac_access_enter(sc);
4563 tmp = iwh_reg_read(sc, ALM_APMG_PS_CTL);
4566 iwh_reg_write(sc, ALM_APMG_PS_CTL, tmp);
4567 iwh_mac_access_exit(sc);
4577 iwh_preinit(iwh_sc_t *sc)
4587 IWH_WRITE(sc, CSR_INT, 0xffffffff);
4589 tmp = IWH_READ(sc, CSR_GIO_CHICKEN_BITS);
4590 IWH_WRITE(sc, CSR_GIO_CHICKEN_BITS,
4593 tmp = IWH_READ(sc, CSR_ANA_PLL_CFG);
4594 IWH_WRITE(sc, CSR_ANA_PLL_CFG, tmp | IWH_CSR_ANA_PLL_CFG);
4596 tmp = IWH_READ(sc, CSR_GP_CNTRL);
4597 IWH_WRITE(sc, CSR_GP_CNTRL, tmp | CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
4603 if (IWH_READ(sc, CSR_GP_CNTRL) &
4614 iwh_mac_access_enter(sc);
4616 iwh_reg_write(sc, ALM_APMG_CLK_EN, APMG_CLK_REG_VAL_DMA_CLK_RQT);
4619 tmp = iwh_reg_read(sc, ALM_APMG_PCIDEV_STT);
4620 iwh_reg_write(sc, ALM_APMG_PCIDEV_STT, tmp |
4622 iwh_mac_access_exit(sc);
4624 radio_cfg = IWH_READ_EEP_SHORT(sc, EEP_SP_RADIO_CONFIGURATION);
4626 tmp = IWH_READ(sc, CSR_HW_IF_CONFIG_REG);
4627 IWH_WRITE(sc, CSR_HW_IF_CONFIG_REG,
4638 IWH_WRITE(sc, CSR_INT_COALESCING, 512 / 32);
4640 (void) iwh_power_up(sc);
4642 if ((sc->sc_rev & 0x80) == 0x80 && (sc->sc_rev & 0x7f) < 8) {
4643 tmp = ddi_get32(sc->sc_cfg_handle,
4644 (uint32_t *)(sc->sc_cfg_base + 0xe8));
4645 ddi_put32(sc->sc_cfg_handle,
4646 (uint32_t *)(sc->sc_cfg_base + 0xe8),
4650 vlink = ddi_get8(sc->sc_cfg_handle,
4651 (uint8_t *)(sc->sc_cfg_base + 0xf0));
4652 ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base + 0xf0),
4655 tmp = IWH_READ(sc, CSR_HW_IF_CONFIG_REG);
4658 IWH_WRITE(sc, CSR_SW_VER, tmp);
4663 iwh_mac_access_enter(sc);
4664 tmp = iwh_reg_read(sc, ALM_APMG_PS_CTL);
4666 iwh_reg_write(sc, ALM_APMG_PS_CTL, tmp);
4669 tmp = iwh_reg_read(sc, ALM_APMG_PS_CTL);
4671 iwh_reg_write(sc, ALM_APMG_PS_CTL, tmp);
4672 iwh_mac_access_exit(sc);
4681 iwh_eep_sem_down(iwh_sc_t *sc)
4687 tmp = IWH_READ(sc, CSR_HW_IF_CONFIG_REG);
4688 IWH_WRITE(sc, CSR_HW_IF_CONFIG_REG,
4692 if (IWH_READ(sc, CSR_HW_IF_CONFIG_REG) &
4707 iwh_eep_sem_up(iwh_sc_t *sc)
4711 tmp = IWH_READ(sc, CSR_HW_IF_CONFIG_REG);
4712 IWH_WRITE(sc, CSR_HW_IF_CONFIG_REG,
4720 iwh_eep_load(iwh_sc_t *sc)
4724 uint16_t addr, eep_sz = sizeof (sc->sc_eep_map);
4725 uint16_t *eep_p = (uint16_t *)&sc->sc_eep_map;
4730 eep_gp = IWH_READ(sc, CSR_EEPROM_GP);
4738 rr = iwh_eep_sem_down(sc);
4746 IWH_WRITE(sc, CSR_EEPROM_REG, addr<<1);
4747 tmp = IWH_READ(sc, CSR_EEPROM_REG);
4748 IWH_WRITE(sc, CSR_EEPROM_REG, tmp & ~(0x2));
4751 rv = IWH_READ(sc, CSR_EEPROM_REG);
4761 iwh_eep_sem_up(sc);
4768 iwh_eep_sem_up(sc);
4776 iwh_get_mac_from_eep(iwh_sc_t *sc)
4778 ieee80211com_t *ic = &sc->sc_ic;
4780 IEEE80211_ADDR_COPY(ic->ic_macaddr, &sc->sc_eep_map[EEP_MAC_ADDRESS]);
4792 iwh_init(iwh_sc_t *sc)
4800 iwh_release_calib_buffer(sc);
4802 mutex_enter(&sc->sc_glock);
4803 atomic_and_32(&sc->sc_flags, ~IWH_F_FW_INIT);
4805 err = iwh_init_common(sc);
4807 mutex_exit(&sc->sc_glock);
4814 bcopy(sc->sc_dma_fw_data.mem_va,
4815 sc->sc_dma_fw_data_bak.mem_va,
4816 sc->sc_dma_fw_data.alength);
4819 err = iwh_load_init_firmware(sc);
4823 mutex_exit(&sc->sc_glock);
4830 IWH_WRITE(sc, CSR_RESET, 0);
4833 while (!(sc->sc_flags & IWH_F_FW_INIT)) {
4834 if (cv_timedwait(&sc->sc_ucode_cv,
4835 &sc->sc_glock, clk) < 0) {
4840 if (!(sc->sc_flags & IWH_F_FW_INIT)) {
4843 mutex_exit(&sc->sc_glock);
4847 mutex_exit(&sc->sc_glock);
4852 iwh_stop(sc);
4854 mutex_enter(&sc->sc_glock);
4855 atomic_and_32(&sc->sc_flags, ~IWH_F_FW_INIT);
4857 err = iwh_init_common(sc);
4859 mutex_exit(&sc->sc_glock);
4866 err = iwh_load_run_firmware(sc);
4870 mutex_exit(&sc->sc_glock);
4877 IWH_WRITE(sc, CSR_RESET, 0);
4880 while (!(sc->sc_flags & IWH_F_FW_INIT)) {
4881 if (cv_timedwait(&sc->sc_ucode_cv,
4882 &sc->sc_glock, clk) < 0) {
4887 if (!(sc->sc_flags & IWH_F_FW_INIT)) {
4890 mutex_exit(&sc->sc_glock);
4894 mutex_exit(&sc->sc_glock);
4898 mutex_enter(&sc->sc_glock);
4899 atomic_and_32(&sc->sc_flags, ~IWH_F_FW_INIT);
4905 err = iwh_config(sc);
4909 mutex_exit(&sc->sc_glock);
4916 mutex_exit(&sc->sc_glock);
4924 iwh_stop(iwh_sc_t *sc)
4932 if (!(sc->sc_flags & IWH_F_QUIESCED)) {
4933 mutex_enter(&sc->sc_glock);
4936 IWH_WRITE(sc, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4940 IWH_WRITE(sc, CSR_INT_MASK, 0);
4941 IWH_WRITE(sc, CSR_INT, CSR_INI_SET_MASK);
4942 IWH_WRITE(sc, CSR_FH_INT_STATUS, 0xffffffff);
4948 iwh_reset_tx_ring(sc, &sc->sc_txq[i]);
4954 iwh_reset_rx_ring(sc);
4956 iwh_mac_access_enter(sc);
4957 iwh_reg_write(sc, ALM_APMG_CLK_DIS, APMG_CLK_REG_VAL_DMA_CLK_RQT);
4958 iwh_mac_access_exit(sc);
4962 iwh_stop_master(sc);
4964 mutex_enter(&sc->sc_mt_lock);
4965 sc->sc_tx_timer = 0;
4966 mutex_exit(&sc->sc_mt_lock);
4968 tmp = IWH_READ(sc, CSR_RESET);
4969 IWH_WRITE(sc, CSR_RESET, tmp | CSR_RESET_REG_FLAG_SW_RESET);
4974 if (!(sc->sc_flags & IWH_F_QUIESCED)) {
4975 mutex_exit(&sc->sc_glock);
5019 iwh_amrr_timeout(iwh_sc_t *sc)
5021 ieee80211com_t *ic = &sc->sc_ic;
5032 sc->sc_clk = ddi_get_lbolt();
5042 iwh_sc_t *sc = (iwh_sc_t *)ic;
5048 if (sc->sc_ht_conf.tx_support_mcs[r/8] &
5067 iwh_sc_t *sc = (iwh_sc_t *)ic;
5073 if (sc->sc_ht_conf.tx_support_mcs[r/8] &
5092 iwh_sc_t *sc = (iwh_sc_t *)ic;
5102 (sc->sc_ht_conf.tx_support_mcs[r/8] &
5123 iwh_sc_t *sc = (iwh_sc_t *)ic;
5133 (sc->sc_ht_conf.tx_support_mcs[r/8] &
5206 iwh_eep_addr_trans(iwh_sc_t *sc, uint32_t indi_addr)
5213 return (&sc->sc_eep_map[di_addr]);
5218 temp = IWH_READ_EEP_SHORT(sc, EEP_LINK_GENERAL);
5222 temp = IWH_READ_EEP_SHORT(sc, EEP_LINK_HOST);
5226 temp = IWH_READ_EEP_SHORT(sc, EEP_LINK_REGULATORY);
5230 temp = IWH_READ_EEP_SHORT(sc, EEP_LINK_CALIBRATION);
5234 temp = IWH_READ_EEP_SHORT(sc, EEP_LINK_PROCESS_ADJST);
5238 temp = IWH_READ_EEP_SHORT(sc, EEP_LINK_OTHERS);
5250 return (&sc->sc_eep_map[di_addr]);
5257 iwh_put_seg_fw(iwh_sc_t *sc, uint32_t addr_s, uint32_t addr_d, uint32_t len)
5260 iwh_mac_access_enter(sc);
5262 IWH_WRITE(sc, IWH_FH_TCSR_CHNL_TX_CONFIG_REG(IWH_FH_SRVC_CHNL),
5265 IWH_WRITE(sc, IWH_FH_SRVC_CHNL_SRAM_ADDR_REG(IWH_FH_SRVC_CHNL), addr_d);
5267 IWH_WRITE(sc, IWH_FH_TFDIB_CTRL0_REG(IWH_FH_SRVC_CHNL),
5270 IWH_WRITE(sc, IWH_FH_TFDIB_CTRL1_REG(IWH_FH_SRVC_CHNL), len);
5272 IWH_WRITE(sc, IWH_FH_TCSR_CHNL_TX_BUF_STS_REG(IWH_FH_SRVC_CHNL),
5277 IWH_WRITE(sc, IWH_FH_TCSR_CHNL_TX_CONFIG_REG(IWH_FH_SRVC_CHNL),
5282 iwh_mac_access_exit(sc);
5291 iwh_alive_common(iwh_sc_t *sc)
5302 iwh_mac_access_enter(sc);
5307 sc->sc_scd_base = iwh_reg_read(sc, IWH_SCD_SRAM_BASE_ADDR);
5309 for (base = sc->sc_scd_base + IWH_SCD_CONTEXT_DATA_OFFSET;
5310 base < sc->sc_scd_base + IWH_SCD_TX_STTS_BITMAP_OFFSET;
5312 iwh_mem_write(sc, base, 0);
5315 for (; base < sc->sc_scd_base + IWH_SCD_TRANSLATE_TBL_OFFSET;
5317 iwh_mem_write(sc, base, 0);
5321 iwh_mem_write(sc, base + i, 0);
5324 iwh_reg_write(sc, IWH_SCD_DRAM_BASE_ADDR,
5325 sc->sc_dma_sh.cookie.dmac_address >> 10);
5327 iwh_reg_write(sc, IWH_SCD_QUEUECHAIN_SEL,
5330 iwh_reg_write(sc, IWH_SCD_AGGR_SEL, 0);
5333 iwh_reg_write(sc, IWH_SCD_QUEUE_RDPTR(i), 0);
5334 IWH_WRITE(sc, HBUS_TARG_WRPTR, 0 | (i << 8));
5335 iwh_mem_write(sc, sc->sc_scd_base +
5337 iwh_mem_write(sc, sc->sc_scd_base +
5347 iwh_reg_write(sc, IWH_SCD_INTERRUPT_MASK, (1 << IWH_NUM_QUEUES) - 1);
5349 iwh_reg_write(sc, (IWH_SCD_BASE + 0x10),
5352 IWH_WRITE(sc, HBUS_TARG_WRPTR, (IWH_CMD_QUEUE_NUM << 8));
5353 iwh_reg_write(sc, IWH_SCD_QUEUE_RDPTR(IWH_CMD_QUEUE_NUM), 0);
5360 iwh_reg_write(sc, IWH_SCD_QUEUE_STATUS_BITS(i),
5367 iwh_reg_write(sc, IWH_SCD_QUEUE_STATUS_BITS(IWH_CMD_QUEUE_NUM),
5374 iwh_reg_write(sc, IWH_SCD_QUEUE_STATUS_BITS(i),
5381 iwh_mac_access_exit(sc);
5385 rv = iwh_cmd(sc, COEX_PRIORITY_TABLE_CMD, &w_cmd, sizeof (w_cmd), 1);
5392 if ((sc->sc_dev_id != 0x423c) &&
5393 (sc->sc_dev_id != 0x423d)) {
5397 c_cmd.data.cap_pin1 = LE_16(sc->sc_eep_calib->xtal_calib[0]);
5398 c_cmd.data.cap_pin2 = LE_16(sc->sc_eep_calib->xtal_calib[1]);
5400 rv = iwh_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
5423 iwh_save_calib_result(iwh_sc_t *sc, iwh_rx_desc_t *desc)
5425 struct iwh_calib_results *res_p = &sc->sc_calib_results;
5522 iwh_tx_power_table(iwh_sc_t *sc, int async)
5530 txpower.channel = (uint8_t)LE_16(sc->sc_config.chan);
5552 err = iwh_cmd(sc, REPLY_TX_PWR_TABLE_CMD, &txpower,
5564 iwh_release_calib_buffer(iwh_sc_t *sc)
5566 if (sc->sc_calib_results.lo_res != NULL) {
5567 kmem_free(sc->sc_calib_results.lo_res,
5568 sc->sc_calib_results.lo_res_len);
5569 sc->sc_calib_results.lo_res = NULL;
5572 if (sc->sc_calib_results.tx_iq_res != NULL) {
5573 kmem_free(sc->sc_calib_results.tx_iq_res,
5574 sc->sc_calib_results.tx_iq_res_len);
5575 sc->sc_calib_results.tx_iq_res = NULL;
5578 if (sc->sc_calib_results.tx_iq_perd_res != NULL) {
5579 kmem_free(sc->sc_calib_results.tx_iq_perd_res,
5580 sc->sc_calib_results.tx_iq_perd_res_len);
5581 sc->sc_calib_results.tx_iq_perd_res = NULL;
5584 if (sc->sc_calib_results.dc_res != NULL) {
5585 kmem_free(sc->sc_calib_results.dc_res,
5586 sc->sc_calib_results.dc_res_len);
5587 sc->sc_calib_results.dc_res = NULL;
5590 if (sc->sc_calib_results.base_band_res != NULL) {
5591 kmem_free(sc->sc_calib_results.base_band_res,
5592 sc->sc_calib_results.base_band_res_len);
5593 sc->sc_calib_results.base_band_res = NULL;
5601 iwh_init_common(iwh_sc_t *sc)
5606 if (iwh_reset_hw(sc) != IWH_SUCCESS) {
5612 (void) iwh_preinit(sc);
5614 tmp = IWH_READ(sc, CSR_GP_CNTRL);
5624 iwh_mac_access_enter(sc);
5625 IWH_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
5627 IWH_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
5628 IWH_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
5629 sc->sc_rxq.dma_desc.cookie.dmac_address >> 8);
5631 IWH_WRITE(sc, FH_RSCSR_CHNL0_STTS_WPTR_REG,
5632 ((uint32_t)(sc->sc_dma_sh.cookie.dmac_address +
5635 IWH_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG,
5641 iwh_mac_access_exit(sc);
5642 IWH_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG,
5648 iwh_mac_access_enter(sc);
5649 iwh_reg_write(sc, IWH_SCD_TXFACT, 0);
5654 IWH_WRITE(sc, IWH_FH_KW_MEM_ADDR_REG,
5655 sc->sc_dma_kw.cookie.dmac_address >> 4);
5658 IWH_WRITE(sc, FH_MEM_CBBC_QUEUE(qid),
5659 sc->sc_txq[qid].dma_desc.cookie.dmac_address >> 8);
5660 IWH_WRITE(sc, IWH_FH_TCSR_CHNL_TX_CONFIG_REG(qid),
5665 iwh_mac_access_exit(sc);
5670 IWH_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5671 IWH_WRITE(sc, CSR_UCODE_DRV_GP1_CLR,
5677 IWH_WRITE(sc, CSR_INT, 0xffffffff);
5682 IWH_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);
5684 IWH_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5685 IWH_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5691 iwh_fast_recover(iwh_sc_t *sc)
5693 ieee80211com_t *ic = &sc->sc_ic;
5696 mutex_enter(&sc->sc_glock);
5701 bcopy(&sc->sc_config_save, &sc->sc_config,
5702 sizeof (sc->sc_config));
5704 sc->sc_config.assoc_id = 0;
5705 sc->sc_config.filter_flags &= ~LE_32(RXON_FILTER_ASSOC_MSK);
5707 if ((err = iwh_hw_set_before_auth(sc)) != IWH_SUCCESS) {
5710 mutex_exit(&sc->sc_glock);
5714 bcopy(&sc->sc_config_save, &sc->sc_config,
5715 sizeof (sc->sc_config));
5720 err = iwh_run_state_config(sc);
5724 mutex_exit(&sc->sc_glock);
5731 iwh_set_led(sc, 2, 0, 1);
5733 mutex_exit(&sc->sc_glock);
5735 atomic_and_32(&sc->sc_flags, ~IWH_F_HW_ERR_RECOVER);
5748 iwh_run_state_config(iwh_sc_t *sc)
5750 struct ieee80211com *ic = &sc->sc_ic;
5758 sc->sc_config.assoc_id = in->in_associd & 0x3fff;
5764 sc->sc_config.flags &=
5769 sc->sc_config.flags |=
5774 sc->sc_config.flags |=
5785 ht_protec = sc->sc_ht_conf.ht_protection;
5788 sc->sc_config.flags |=
5795 iwh_config_rxon_chain(sc);
5797 sc->sc_config.filter_flags |=
5801 sc->sc_config.filter_flags |=
5808 sc->sc_config.chan, sc->sc_config.flags,
5809 sc->sc_config.filter_flags));
5811 err = iwh_cmd(sc, REPLY_RXON, &sc->sc_config,
5819 if ((sc->sc_dev_id != 0x423c) &&
5820 (sc->sc_dev_id != 0x423d)) {
5824 err = iwh_tx_power_table(sc, 1);
5833 err = iwh_qosparam_to_hw(sc, 1);
5927 iwh_qosparam_to_hw(iwh_sc_t *sc, int async)
5929 ieee80211com_t *ic = &sc->sc_ic;
5975 err = iwh_cmd(sc, REPLY_QOS_PARAM, &qosparam_cmd,
6071 iwh_init_ht_conf(iwh_sc_t *sc)
6073 (void) memset(&sc->sc_ht_conf, 0, sizeof (iwh_ht_conf_t));
6075 if ((0x4235 == sc->sc_dev_id) ||
6076 (0x4236 == sc->sc_dev_id) ||
6077 (0x423a == sc->sc_dev_id)) {
6078 sc->sc_ht_conf.ht_support = 1;
6080 sc->sc_ht_conf.valid_chains = 3;
6081 sc->sc_ht_conf.tx_stream_count = 2;
6082 sc->sc_ht_conf.rx_stream_count = 2;
6084 sc->sc_ht_conf.tx_support_mcs[0] = 0xff;
6085 sc->sc_ht_conf.tx_support_mcs[1] = 0xff;
6086 sc->sc_ht_conf.rx_support_mcs[0] = 0xff;
6087 sc->sc_ht_conf.rx_support_mcs[1] = 0xff;
6089 sc->sc_ht_conf.ht_support = 1;
6091 sc->sc_ht_conf.valid_chains = 2;
6092 sc->sc_ht_conf.tx_stream_count = 1;
6093 sc->sc_ht_conf.rx_stream_count = 2;
6095 sc->sc_ht_conf.tx_support_mcs[0] = 0xff;
6096 sc->sc_ht_conf.rx_support_mcs[0] = 0xff;
6097 sc->sc_ht_conf.rx_support_mcs[1] = 0xff;
6100 if (sc->sc_ht_conf.ht_support) {
6101 sc->sc_ht_conf.cap |= HT_CAP_GRN_FLD;
6102 sc->sc_ht_conf.cap |= HT_CAP_SGI_20;
6103 sc->sc_ht_conf.cap |= HT_CAP_MAX_AMSDU;
6105 sc->sc_ht_conf.cap |= HT_CAP_MIMO_PS;
6107 sc->sc_ht_conf.ampdu_p.factor = HT_RX_AMPDU_FACTOR;
6108 sc->sc_ht_conf.ampdu_p.density = HT_MPDU_DENSITY;
6110 sc->sc_ht_conf.ht_protection = HT_PROT_CHAN_NON_HT;
6118 iwh_overwrite_11n_rateset(iwh_sc_t *sc)
6120 uint8_t *ht_rs = sc->sc_ht_conf.rx_support_mcs;
6157 iwh_overwrite_ic_default(iwh_sc_t *sc)
6159 ieee80211com_t *ic = &sc->sc_ic;
6161 sc->sc_newstate = ic->ic_newstate;
6166 if (sc->sc_ht_conf.ht_support) {
6167 sc->sc_recv_action = ic->ic_recv_action;
6169 sc->sc_send_action = ic->ic_send_action;
6172 ic->ic_ampdu_rxmax = sc->sc_ht_conf.ampdu_p.factor;
6173 ic->ic_ampdu_density = sc->sc_ht_conf.ampdu_p.density;
6183 iwh_config_rxon_chain(iwh_sc_t *sc)
6185 ieee80211com_t *ic = &sc->sc_ic;
6188 if (3 == sc->sc_ht_conf.valid_chains) {
6189 sc->sc_config.rx_chain = LE_16((RXON_RX_CHAIN_A_MSK |
6193 sc->sc_config.rx_chain |= LE_16((RXON_RX_CHAIN_A_MSK |
6197 sc->sc_config.rx_chain |= LE_16((RXON_RX_CHAIN_A_MSK |
6201 sc->sc_config.rx_chain = LE_16((RXON_RX_CHAIN_A_MSK |
6204 sc->sc_config.rx_chain |= LE_16((RXON_RX_CHAIN_A_MSK |
6207 sc->sc_config.rx_chain |= LE_16((RXON_RX_CHAIN_A_MSK |
6212 sc->sc_config.rx_chain |= LE_16(RXON_RX_CHAIN_DRIVER_FORCE_MSK);
6216 sc->sc_ht_conf.ht_support) {
6217 if (3 == sc->sc_ht_conf.valid_chains) {
6218 sc->sc_config.rx_chain |= LE_16(3 <<
6220 sc->sc_config.rx_chain |= LE_16(3 <<
6223 sc->sc_config.rx_chain |= LE_16(2 <<
6225 sc->sc_config.rx_chain |= LE_16(2 <<
6229 sc->sc_config.rx_chain |= LE_16(1 <<
6234 "rxon->rx_chain = %x\n", sc->sc_config.rx_chain));
6241 iwh_add_ap_sta(iwh_sc_t *sc)
6243 ieee80211com_t *ic = &sc->sc_ic;
6257 if (sc->sc_ht_conf.ht_support &&
6282 err = iwh_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 1);
6300 iwh_ap_lq(iwh_sc_t *sc)
6302 ieee80211com_t *ic = &sc->sc_ic;
6341 err = iwh_cmd(sc, REPLY_TX_LINK_QUALITY_CMD, &link_quality,
6375 iwh_sc_t *sc;
6391 sc = (iwh_sc_t *)ic;
6393 sc->sc_recv_action(in, frm, efrm);
6418 mutex_enter(&sc->sc_glock);
6419 err = iwh_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 1);
6423 mutex_exit(&sc->sc_glock);
6426 mutex_exit(&sc->sc_glock);
6452 mutex_enter(&sc->sc_glock);
6453 err = iwh_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 1);
6457 mutex_exit(&sc->sc_glock);
6460 mutex_exit(&sc->sc_glock);
6480 iwh_sc_t *sc;
6496 sc = (iwh_sc_t *)ic;
6498 ret = sc->sc_send_action(in, category, action, args);
6521 mutex_enter(&sc->sc_glock);
6522 err = iwh_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 1);
6526 mutex_exit(&sc->sc_glock);
6529 mutex_exit(&sc->sc_glock);
6542 iwh_reset_hw(iwh_sc_t *sc)
6547 tmp = IWH_READ(sc, CSR_HW_IF_CONFIG_REG);
6548 IWH_WRITE(sc, CSR_HW_IF_CONFIG_REG,
6555 if (IWH_READ(sc, CSR_HW_IF_CONFIG_REG) &
6566 tmp = IWH_READ(sc, CSR_HW_IF_CONFIG_REG);
6567 IWH_WRITE(sc, CSR_HW_IF_CONFIG_REG,
6571 if (0 == (IWH_READ(sc, CSR_HW_IF_CONFIG_REG) &
6582 tmp = IWH_READ(sc, CSR_HW_IF_CONFIG_REG);
6583 IWH_WRITE(sc, CSR_HW_IF_CONFIG_REG,
6590 if (IWH_READ(sc, CSR_HW_IF_CONFIG_REG) &