Lines Matching defs:efep
255 efe_t *efep;
263 efep = ddi_get_driver_private(dip);
264 return (efe_resume(efep));
298 efep = kmem_zalloc(sizeof (efe_t), KM_SLEEP);
299 ddi_set_driver_private(dip, efep);
301 efep->efe_dip = dip;
303 if (ddi_regs_map_setup(dip, 1, (caddr_t *)&efep->efe_regs, 0, 0,
304 &efe_regs_acc_attr, &efep->efe_regs_acch) != DDI_SUCCESS) {
309 efep->efe_rx_ring = efe_ring_alloc(efep->efe_dip, RXDESCL);
310 if (efep->efe_rx_ring == NULL) {
311 efe_error(efep->efe_dip, "unable to allocate rx ring!");
315 efep->efe_tx_ring = efe_ring_alloc(efep->efe_dip, TXDESCL);
316 if (efep->efe_tx_ring == NULL) {
317 efe_error(efep->efe_dip, "unable to allocate tx ring!");
321 if (ddi_intr_alloc(dip, &efep->efe_intrh, DDI_INTR_TYPE_FIXED, 0,
328 if (ddi_intr_get_pri(efep->efe_intrh, &pri) != DDI_SUCCESS ||
334 mutex_init(&efep->efe_intrlock, NULL, MUTEX_DRIVER,
337 mutex_init(&efep->efe_txlock, NULL, MUTEX_DRIVER,
343 mutex_enter(&efep->efe_intrlock);
344 mutex_enter(&efep->efe_txlock);
346 efe_reset(efep);
348 mutex_exit(&efep->efe_txlock);
349 mutex_exit(&efep->efe_intrlock);
352 efe_getaddr(efep, efep->efe_macaddr);
357 if (ddi_intr_add_handler(efep->efe_intrh, efe_intr, efep, NULL)
363 if (ddi_intr_enable(efep->efe_intrh) != DDI_SUCCESS) {
371 if ((efep->efe_miih = mii_alloc(efep, dip, &efe_mii_ops)) == NULL) {
385 macp->m_driver = efep;
387 macp->m_src_addr = efep->efe_macaddr;
393 if (mac_register(macp, &efep->efe_mh) != 0) {
408 if (efep->efe_miih != NULL) {
409 mii_free(efep->efe_miih);
412 if (efep->efe_intrh != NULL) {
413 (void) ddi_intr_disable(efep->efe_intrh);
414 (void) ddi_intr_remove_handler(efep->efe_intrh);
415 (void) ddi_intr_free(efep->efe_intrh);
418 mutex_destroy(&efep->efe_txlock);
419 mutex_destroy(&efep->efe_intrlock);
421 if (efep->efe_tx_ring != NULL) {
422 efe_ring_free(&efep->efe_tx_ring);
424 if (efep->efe_rx_ring != NULL) {
425 efe_ring_free(&efep->efe_rx_ring);
428 if (efep->efe_regs_acch != NULL) {
429 ddi_regs_map_free(&efep->efe_regs_acch);
432 kmem_free(efep, sizeof (efe_t));
440 efe_t *efep = ddi_get_driver_private(dip);
447 return (efe_suspend(efep));
453 if (mac_unregister(efep->efe_mh) != 0) {
458 mii_free(efep->efe_miih);
460 (void) ddi_intr_disable(efep->efe_intrh);
461 (void) ddi_intr_remove_handler(efep->efe_intrh);
462 (void) ddi_intr_free(efep->efe_intrh);
464 mutex_destroy(&efep->efe_txlock);
465 mutex_destroy(&efep->efe_intrlock);
467 if (efep->efe_tx_ring != NULL) {
468 efe_ring_free(&efep->efe_tx_ring);
470 if (efep->efe_rx_ring != NULL) {
471 efe_ring_free(&efep->efe_rx_ring);
474 ddi_regs_map_free(&efep->efe_regs_acch);
476 kmem_free(efep, sizeof (efe_t));
484 efe_t *efep = ddi_get_driver_private(dip);
486 PUTCSR(efep, CSR_GENCTL, GENCTL_RESET);
489 PUTCSR(efep, CSR_GENCTL, GENCTL_PWRDWN);
500 efe_t *efep = arg;
502 PUTCSR(efep, CSR_MMCTL, MMCTL_READ |
506 if (!(GETCSR(efep, CSR_MMCTL) & MMCTL_READ)) {
507 return ((uint16_t)GETCSR(efep, CSR_MMDATA));
511 efe_error(efep->efe_dip, "timed out reading from MII!");
519 efe_t *efep = arg;
521 PUTCSR(efep, CSR_MMDATA, data);
523 PUTCSR(efep, CSR_MMCTL, MMCTL_WRITE |
527 if (!(GETCSR(efep, CSR_MMCTL) & MMCTL_WRITE)) {
532 efe_error(efep->efe_dip, "timed out writing to MII!");
538 efe_t *efep = arg;
540 mac_link_update(efep->efe_mh, link);
549 efe_t *efep = arg;
551 if (mii_m_getstat(efep->efe_miih, stat, val) == 0) {
557 *val = efep->efe_multircv;
561 *val = efep->efe_brdcstrcv;
565 *val = efep->efe_multixmt;
569 *val = efep->efe_brdcstxmt;
573 *val = efep->efe_norcvbuf;
577 *val = efep->efe_ierrors;
581 *val = efep->efe_noxmtbuf;
585 *val = efep->efe_oerrors;
589 *val = efep->efe_collisions;
593 *val = efep->efe_rbytes;
597 *val = efep->efe_ipackets;
601 *val = efep->efe_obytes;
605 *val = efep->efe_opackets;
609 *val = efep->efe_uflo;
613 *val = efep->efe_oflo;
617 *val = efep->efe_align_errors;
621 *val = efep->efe_fcs_errors;
625 *val = efep->efe_first_collisions;
629 *val = efep->efe_tx_late_collisions;
633 *val = efep->efe_defer_xmts;
637 *val = efep->efe_ex_collisions;
641 *val = efep->efe_macxmt_errors;
645 *val = efep->efe_carrier_errors;
649 *val = efep->efe_toolong_errors;
653 *val = efep->efe_macrcv_errors;
657 *val = efep->efe_runt_errors;
661 *val = efep->efe_jabber_errors;
674 efe_t *efep = arg;
676 mutex_enter(&efep->efe_intrlock);
677 mutex_enter(&efep->efe_txlock);
679 efe_start(efep);
680 efep->efe_flags |= FLAG_RUNNING;
682 mutex_exit(&efep->efe_txlock);
683 mutex_exit(&efep->efe_intrlock);
685 mii_start(efep->efe_miih);
693 efe_t *efep = arg;
695 mutex_enter(&efep->efe_intrlock);
696 mutex_enter(&efep->efe_txlock);
698 efe_stop(efep);
699 efep->efe_flags &= ~FLAG_RUNNING;
701 mutex_exit(&efep->efe_txlock);
702 mutex_exit(&efep->efe_intrlock);
704 mii_stop(efep->efe_miih);
710 efe_t *efep = arg;
712 mutex_enter(&efep->efe_intrlock);
713 mutex_enter(&efep->efe_txlock);
715 if (efep->efe_flags & FLAG_SUSPENDED) {
716 mutex_exit(&efep->efe_txlock);
717 mutex_exit(&efep->efe_intrlock);
721 efep->efe_promisc = on;
723 if (efep->efe_flags & FLAG_RUNNING) {
724 efe_restart(efep);
727 mutex_exit(&efep->efe_txlock);
728 mutex_exit(&efep->efe_intrlock);
736 efe_t *efep = arg;
742 mutex_enter(&efep->efe_intrlock);
743 mutex_enter(&efep->efe_txlock);
745 if (efep->efe_flags & FLAG_SUSPENDED) {
746 mutex_exit(&efep->efe_txlock);
747 mutex_exit(&efep->efe_intrlock);
758 efep->efe_mccount[val]++;
759 if (efep->efe_mccount[val] == 1) {
760 efep->efe_mchash[index] |= bit;
765 efep->efe_mccount[val]--;
766 if (efep->efe_mccount[val] == 0) {
767 efep->efe_mchash[index] &= ~bit;
772 if (restart && efep->efe_flags & FLAG_RUNNING) {
773 efe_restart(efep);
776 mutex_exit(&efep->efe_txlock);
777 mutex_exit(&efep->efe_intrlock);
785 efe_t *efep = arg;
787 mutex_enter(&efep->efe_intrlock);
788 mutex_enter(&efep->efe_txlock);
790 if (efep->efe_flags & FLAG_SUSPENDED) {
791 mutex_exit(&efep->efe_txlock);
792 mutex_exit(&efep->efe_intrlock);
796 bcopy(macaddr, efep->efe_macaddr, ETHERADDRL);
798 if (efep->efe_flags & FLAG_RUNNING) {
799 efe_restart(efep);
802 mutex_exit(&efep->efe_txlock);
803 mutex_exit(&efep->efe_intrlock);
811 efe_t *efep = arg;
813 mutex_enter(&efep->efe_txlock);
815 if (efep->efe_flags & FLAG_SUSPENDED) {
816 mutex_exit(&efep->efe_txlock);
824 if (efe_send(efep, mp) != DDI_SUCCESS) {
832 PUTCSR(efep, CSR_COMMAND, COMMAND_TXQUEUED);
834 mutex_exit(&efep->efe_txlock);
843 efe_t *efep = arg;
845 return (mii_m_setprop(efep->efe_miih, name, id, valsize, val));
852 efe_t *efep = arg;
854 return (mii_m_getprop(efep->efe_miih, name, id, valsize, val));
861 efe_t *efep = arg;
863 mii_m_propinfo(efep->efe_miih, name, id, state);
872 efe_t *efep = (void *)arg1;
878 mutex_enter(&efep->efe_intrlock);
880 if (efep->efe_flags & FLAG_SUSPENDED) {
881 mutex_exit(&efep->efe_intrlock);
885 status = GETCSR(efep, CSR_INTSTAT);
887 mutex_exit(&efep->efe_intrlock);
890 PUTCSR(efep, CSR_INTSTAT, status);
893 mp = efe_recv(efep);
897 efep->efe_ierrors++;
898 efep->efe_macrcv_errors++;
901 PUTCSR(efep, CSR_COMMAND, COMMAND_RXQUEUED);
905 mutex_enter(&efep->efe_txlock);
907 efe_send_done(efep);
909 mutex_exit(&efep->efe_txlock);
913 mutex_enter(&efep->efe_txlock);
915 efe_error(efep->efe_dip, "bus error; resetting!");
916 efe_restart(efep);
918 mutex_exit(&efep->efe_txlock);
921 mutex_exit(&efep->efe_intrlock);
924 mac_rx(efep->efe_mh, NULL, mp);
928 mac_tx_update(efep->efe_mh);
932 mii_reset(efep->efe_miih);
942 efe_init(efe_t *efep)
946 ASSERT(mutex_owned(&efep->efe_intrlock));
947 ASSERT(mutex_owned(&efep->efe_txlock));
949 efe_reset(efep);
956 PUTCSR(efep, CSR_GENCTL, val);
957 PUTCSR(efep, CSR_PBLCNT, BURSTLEN);
959 efe_init_rx_ring(efep);
960 efe_init_tx_ring(efep);
962 efe_setaddr(efep, efep->efe_macaddr);
964 if (efep->efe_promisc) {
965 efe_setmchash(efep, efe_mchash_promisc);
967 efe_setmchash(efep, efep->efe_mchash);
972 efe_init_rx_ring(efe_t *efep)
976 ASSERT(mutex_owned(&efep->efe_intrlock));
978 rp = efep->efe_rx_ring;
994 efep->efe_rx_desc = 0;
996 PUTCSR(efep, CSR_PRCDAR, DESCADDR(rp, 0));
1000 efe_init_tx_ring(efe_t *efep)
1004 ASSERT(mutex_owned(&efep->efe_txlock));
1006 rp = efep->efe_tx_ring;
1022 efep->efe_tx_desc = 0;
1023 efep->efe_tx_sent = 0;
1025 PUTCSR(efep, CSR_PTCDAR, DESCADDR(rp, 0));
1029 efe_reset(efe_t *efep)
1031 ASSERT(mutex_owned(&efep->efe_intrlock));
1032 ASSERT(mutex_owned(&efep->efe_txlock));
1034 PUTCSR(efep, CSR_GENCTL, GENCTL_RESET);
1039 PUTCSR(efep, CSR_TEST, TEST_CLOCK);
1044 efe_start(efe_t *efep)
1046 ASSERT(mutex_owned(&efep->efe_intrlock));
1047 ASSERT(mutex_owned(&efep->efe_txlock));
1049 efe_init(efep);
1051 PUTCSR(efep, CSR_RXCON,
1053 (efep->efe_promisc ? RXCON_PROMISC : 0));
1055 PUTCSR(efep, CSR_TXCON, TXCON_LB_3);
1057 efe_intr_enable(efep);
1059 SETBIT(efep, CSR_COMMAND,
1064 efe_stop(efe_t *efep)
1066 ASSERT(mutex_owned(&efep->efe_intrlock));
1067 ASSERT(mutex_owned(&efep->efe_txlock));
1069 efe_intr_disable(efep);
1071 PUTCSR(efep, CSR_COMMAND, COMMAND_STOP_RX);
1073 efe_stop_dma(efep);
1075 PUTCSR(efep, CSR_GENCTL, GENCTL_RESET);
1078 PUTCSR(efep, CSR_GENCTL, GENCTL_PWRDWN);
1082 efe_stop_dma(efe_t *efep)
1084 ASSERT(mutex_owned(&efep->efe_intrlock));
1085 ASSERT(mutex_owned(&efep->efe_txlock));
1087 PUTCSR(efep, CSR_COMMAND,
1091 uint32_t status = GETCSR(efep, CSR_INTSTAT);
1098 efe_error(efep->efe_dip, "timed out stopping DMA engine!");
1102 efe_restart(efe_t *efep)
1104 efe_stop(efep);
1105 efe_start(efep);
1109 efe_suspend(efe_t *efep)
1111 mutex_enter(&efep->efe_intrlock);
1112 mutex_enter(&efep->efe_txlock);
1114 if (efep->efe_flags & FLAG_RUNNING) {
1115 efe_stop(efep);
1117 efep->efe_flags |= FLAG_SUSPENDED;
1119 mutex_exit(&efep->efe_txlock);
1120 mutex_exit(&efep->efe_intrlock);
1122 mii_suspend(efep->efe_miih);
1128 efe_resume(efe_t *efep)
1130 mutex_enter(&efep->efe_intrlock);
1131 mutex_enter(&efep->efe_txlock);
1133 if (efep->efe_flags & FLAG_RUNNING) {
1134 efe_start(efep);
1136 efep->efe_flags &= ~FLAG_SUSPENDED;
1138 mutex_exit(&efep->efe_txlock);
1139 mutex_exit(&efep->efe_intrlock);
1141 mii_resume(efep->efe_miih);
1285 efe_intr_enable(efe_t *efep)
1287 PUTCSR(efep, CSR_INTMASK,
1290 SETBIT(efep, CSR_GENCTL, GENCTL_INT);
1294 efe_intr_disable(efe_t *efep)
1296 PUTCSR(efep, CSR_INTMASK, 0);
1298 CLRBIT(efep, CSR_GENCTL, GENCTL_INT);
1302 efe_recv(efe_t *efep)
1308 ASSERT(mutex_owned(&efep->efe_intrlock));
1310 rp = efep->efe_rx_ring;
1316 dp = GETDESC(rp, efep->efe_rx_desc);
1317 SYNCDESC(rp, efep->efe_rx_desc, DDI_DMA_SYNC_FORKERNEL);
1327 mblk_t *tmp = efe_recv_pkt(efep, dp);
1334 efep->efe_ierrors++;
1337 efep->efe_align_errors++;
1340 efep->efe_fcs_errors++;
1343 efep->efe_oflo++;
1350 SYNCDESC(rp, efep->efe_rx_desc, DDI_DMA_SYNC_FORDEV);
1352 efep->efe_rx_desc = NEXTDESC(rp, efep->efe_rx_desc);
1359 efe_recv_pkt(efe_t *efep, efe_desc_t *dp)
1367 ASSERT(mutex_owned(&efep->efe_intrlock));
1369 rp = efep->efe_rx_ring;
1374 efep->efe_ierrors++;
1375 efep->efe_runt_errors++;
1380 efep->efe_ierrors++;
1381 efep->efe_toolong_errors++;
1387 efep->efe_ierrors++;
1388 efep->efe_norcvbuf++;
1393 bp = GETBUF(rp, efep->efe_rx_desc);
1398 efep->efe_ipackets++;
1399 efep->efe_rbytes += len;
1404 efep->efe_brdcstrcv++;
1407 efep->efe_multircv++;
1414 efe_send(efe_t *efep, mblk_t *mp)
1422 ASSERT(mutex_owned(&efep->efe_txlock));
1424 rp = efep->efe_tx_ring;
1429 efep->efe_oerrors++;
1430 efep->efe_macxmt_errors++;
1435 dp = GETDESC(rp, efep->efe_tx_desc);
1436 SYNCDESC(rp, efep->efe_tx_desc, DDI_DMA_SYNC_FORKERNEL);
1438 status = GETDESC16(efep->efe_tx_ring, &dp->d_status);
1445 bp = GETBUF(rp, efep->efe_tx_desc);
1464 SYNCDESC(rp, efep->efe_tx_desc, DDI_DMA_SYNC_FORDEV);
1466 efep->efe_opackets++;
1467 efep->efe_obytes += len;
1471 efep->efe_brdcstxmt++;
1473 efep->efe_multixmt++;
1477 efep->efe_tx_desc = NEXTDESC(rp, efep->efe_tx_desc);
1483 efe_send_done(efe_t *efep)
1487 ASSERT(mutex_owned(&efep->efe_txlock));
1489 rp = efep->efe_tx_ring;
1495 dp = GETDESC(rp, efep->efe_tx_sent);
1496 SYNCDESC(rp, efep->efe_tx_sent, DDI_DMA_SYNC_FORKERNEL);
1507 efep->efe_defer_xmts++;
1510 efep->efe_first_collisions++;
1514 efep->efe_oerrors++;
1517 efep->efe_carrier_errors++;
1520 efep->efe_uflo++;
1523 efep->efe_tx_late_collisions++;
1526 efep->efe_jabber_errors++;
1529 efep->efe_ex_collisions++;
1533 efep->efe_collisions +=
1536 efep->efe_tx_sent = NEXTDESC(rp, efep->efe_tx_sent);
1541 efe_getaddr(efe_t *efep, uint8_t *macaddr)
1543 efe_eeprom_read(efep, macaddr, ETHERADDRL, 0x0);
1545 efe_debug(efep->efe_dip,
1552 efe_setaddr(efe_t *efep, uint8_t *macaddr)
1557 PUTCSR(efep, CSR_LAN0, val);
1561 PUTCSR(efep, CSR_LAN1, val);
1565 PUTCSR(efep, CSR_LAN2, val);
1569 efe_setmchash(efe_t *efep, uint16_t *mchash)
1571 PUTCSR(efep, CSR_MC0, mchash[0]);
1572 PUTCSR(efep, CSR_MC1, mchash[1]);
1573 PUTCSR(efep, CSR_MC2, mchash[2]);
1574 PUTCSR(efep, CSR_MC3, mchash[3]);
1578 efe_eeprom_read(efe_t *efep, uint8_t *buf, size_t len, uint8_t addr)
1584 PUTCSR(efep, CSR_EECTL, EECTL_ENABLE | EECTL_EECS);
1587 addrlen = (GETCSR(efep, CSR_EECTL) & EECTL_SIZE ?
1591 uint16_t val = efe_eeprom_readw(efep, addrlen, addr + i);
1598 efe_eeprom_readw(efe_t *efep, int addrlen, uint8_t addr)
1605 efe_eeprom_writebit(efep, 1);
1608 efe_eeprom_writebit(efep, 1);
1609 efe_eeprom_writebit(efep, 0);
1613 efe_eeprom_writebit(efep, addr & 1U << i);
1618 val |= efe_eeprom_readbit(efep) << i;
1621 PUTCSR(efep, CSR_EECTL, EECTL_ENABLE);
1628 efe_eeprom_readbit(efe_t *efep)
1630 PUTCSR(efep, CSR_EECTL, EECTL_ENABLE | EECTL_EECS);
1633 PUTCSR(efep, CSR_EECTL, EECTL_ENABLE | EECTL_EECS |
1637 PUTCSR(efep, CSR_EECTL, EECTL_ENABLE | EECTL_EECS);
1640 return (!!(GETCSR(efep, CSR_EECTL) & EECTL_EEDO));
1644 efe_eeprom_writebit(efe_t *efep, int bit)
1646 PUTCSR(efep, CSR_EECTL, EECTL_ENABLE | EECTL_EECS);
1649 PUTCSR(efep, CSR_EECTL, EECTL_ENABLE | EECTL_EECS |
1653 PUTCSR(efep, CSR_EECTL, EECTL_ENABLE | EECTL_EECS);