Lines Matching refs:pp
92 * pp->io_mode defines PIO or DMA method of transfer;
104 * pp->current_mode -- 1284 mode used for forward transfers;
105 * pp->backchannel -- 1284 mode used for backward transfers;
106 * pp->curent_phase -- 1284 phase;
109 * pp->current_mode == ECPP_COMPAT_MODE && pp->backchannel == ECPP_NIBBLE_MODE
112 * Driver internal state is defined by pp->e_busy as follows:
120 * sets pp->current_mode and pp->backchannel accordingly.
124 * by copying them into pp->ioblock. If first the mblk data is bigger than
125 * pp->ioblock, then it is used instead of i/o block (pointed by pp->msg)
271 static int m1553_map_regs(struct ecppunit *pp);
272 static void m1553_unmap_regs(struct ecppunit *pp);
312 static uchar_t nibble_peripheral2host(struct ecppunit *pp, uint8_t *);
592 struct ecppunit *pp;
602 if (!(pp = ddi_get_soft_state(ecppsoft_statep, instance))) {
606 mutex_enter(&pp->umutex);
608 pp->suspended = FALSE;
613 (void) ECPP_CONFIG_CHIP(pp);
614 (void) ecpp_reset_port_regs(pp);
616 if (pp->oflag == TRUE) {
617 int current_mode = pp->current_mode;
619 (void) ecpp_1284_termination(pp);
620 (void) ecpp_mode_negotiation(pp, current_mode);
623 mutex_exit(&pp->umutex);
636 pp = ddi_get_soft_state(ecppsoft_statep, instance);
638 pp->dip = dip;
639 pp->suspended = FALSE;
644 hw_bind = ecpp_determine_sio_type(pp);
650 pp->hw = hw_bind->hw;
651 ecpp_error(pp->dip, "SuperIO type: %s\n", hw_bind->info);
657 if (ECPP_MAP_REGS(pp) != SUCCESS) {
661 if (ddi_dma_alloc_handle(dip, pp->hw->attr, DDI_DMA_DONTWAIT,
662 NULL, &pp->dma_handle) != DDI_SUCCESS) {
668 &pp->ecpp_trap_cookie) != DDI_SUCCESS) {
673 mutex_init(&pp->umutex, NULL, MUTEX_DRIVER,
674 (void *)pp->ecpp_trap_cookie);
676 cv_init(&pp->pport_cv, NULL, CV_DRIVER, NULL);
678 if (ddi_add_intr(dip, 0, &pp->ecpp_trap_cookie, NULL, ecpp_isr,
679 (caddr_t)pp) != DDI_SUCCESS) {
685 &pp->softintr_id, 0, 0, ecpp_softintr,
686 (caddr_t)pp) != DDI_SUCCESS) {
699 pp->ioblock = (caddr_t)kmem_alloc(IO_BLOCK_SZ, KM_SLEEP);
700 if (pp->ioblock == NULL) {
704 ecpp_error(pp->dip, "ecpp_attach: ioblock=0x%x\n", pp->ioblock);
707 ecpp_get_props(pp);
709 if (pp->hw == &x86 && pp->uh.x86.chn != 0xff) {
710 if (ddi_dmae_alloc(dip, pp->uh.x86.chn,
712 ecpp_error(pp->dip, "dmae_alloc success!\n");
715 if (ECPP_CONFIG_CHIP(pp) == FAILURE) {
716 ecpp_error(pp->dip, "config_chip failed.\n");
720 ecpp_kstat_init(pp);
728 kmem_free(pp->ioblock, IO_BLOCK_SZ);
732 ddi_remove_softintr(pp->softintr_id);
734 ddi_remove_intr(dip, (uint_t)0, pp->ecpp_trap_cookie);
736 mutex_destroy(&pp->umutex);
737 cv_destroy(&pp->pport_cv);
739 ddi_dma_free_handle(&pp->dma_handle);
741 ECPP_UNMAP_REGS(pp);
755 struct ecppunit *pp;
764 if (!(pp = ddi_get_soft_state(ecppsoft_statep, instance))) {
768 mutex_enter(&pp->umutex);
769 ASSERT(pp->suspended == FALSE);
771 pp->suspended = TRUE; /* prevent new transfers */
776 if ((pp->e_busy == ECPP_BUSY) || (pp->e_busy == ECPP_FLUSH)) {
777 (void) cv_reltimedwait(&pp->pport_cv, &pp->umutex,
780 if ((pp->e_busy == ECPP_BUSY) ||
781 (pp->e_busy == ECPP_FLUSH)) {
782 pp->suspended = FALSE;
783 mutex_exit(&pp->umutex);
784 ecpp_error(pp->dip,
790 mutex_exit(&pp->umutex);
797 pp = ddi_get_soft_state(ecppsoft_statep, instance);
799 if (pp->hw == &x86 && pp->uh.x86.chn != 0xff)
800 (void) ddi_dmae_release(pp->dip, pp->uh.x86.chn);
802 if (pp->dma_handle != NULL)
803 ddi_dma_free_handle(&pp->dma_handle);
807 ddi_remove_softintr(pp->softintr_id);
809 ddi_remove_intr(dip, (uint_t)0, pp->ecpp_trap_cookie);
811 if (pp->ksp) {
812 kstat_delete(pp->ksp);
814 if (pp->intrstats) {
815 kstat_delete(pp->intrstats);
818 cv_destroy(&pp->pport_cv);
820 mutex_destroy(&pp->umutex);
822 ECPP_UNMAP_REGS(pp);
824 kmem_free(pp->ioblock, IO_BLOCK_SZ);
841 ecpp_get_props(struct ecppunit *pp)
857 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pp->dip, 0,
859 pp->fast_centronics =
863 pp->fast_centronics = FALSE;
876 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pp->dip, 0,
878 pp->fast_compat = (strcmp(prop, "true") == 0) ? TRUE : FALSE;
881 pp->fast_compat = TRUE;
891 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pp->dip, 0,
893 pp->init_seq = (strcmp(prop, "true") == 0) ? TRUE : FALSE;
896 pp->init_seq = FALSE;
905 pp->wsrv_retry = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0,
914 pp->wait_for_busy = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0,
921 pp->data_setup_time = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0,
928 pp->strobe_pulse_width = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0,
936 pp->dip, 0, "ecpp-transfer-timeout", ecpp_def_timeout);
938 pp->xfer_parms = default_xfer_parms;
943 if (pp->hw == &m1553) {
944 pp->uh.m1553.chn = ddi_prop_get_int(DDI_DEV_T_ANY,
945 pp->dip, 0, "dma-channel", 0x1);
946 ecpp_error(pp->dip, "ecpp_get_prop:chn=%x\n", pp->uh.m1553.chn);
951 if (pp->hw == &x86) {
952 if (ddi_prop_op(DDI_DEV_T_ANY, pp->dip, PROP_LEN_AND_VAL_BUF,
955 ecpp_error(pp->dip, "No dma channel found\n");
956 pp->uh.x86.chn = 0xff;
957 pp->fast_compat = FALSE;
958 pp->noecpregs = TRUE;
960 pp->uh.x86.chn = (uint8_t)value;
966 pp->ecp_rev_speed = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0,
969 pp->rev_watchdog = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0,
972 ecpp_error(pp->dip,
977 pp->fast_centronics, pp->fast_compat,
978 pp->wsrv_retry, pp->wait_for_busy,
979 pp->data_setup_time, pp->strobe_pulse_width,
980 pp->xfer_parms.write_timeout);
988 struct ecppunit *pp;
995 pp = ddi_get_soft_state(ecppsoft_statep, instance);
996 if (pp != NULL) {
997 *result = pp->dip;
1021 struct ecppunit *pp;
1032 pp = (struct ecppunit *)ddi_get_soft_state(ecppsoft_statep, instance);
1034 if (pp == NULL) {
1038 mutex_enter(&pp->umutex);
1044 if (pp->oflag == TRUE) {
1045 ecpp_error(pp->dip, "ecpp open failed");
1046 mutex_exit(&pp->umutex);
1050 pp->oflag = TRUE;
1053 pp->prn_timeouts = prn_timeouts_default;
1054 pp->xfer_parms = default_xfer_parms;
1055 pp->current_mode = ECPP_CENTRONICS;
1056 pp->backchannel = ECPP_CENTRONICS;
1057 pp->current_phase = ECPP_PHASE_PO;
1058 pp->port = ECPP_PORT_DMA;
1059 pp->instance = instance;
1060 pp->timeout_error = 0;
1061 pp->saved_dsr = DSR_READ(pp);
1062 pp->ecpp_drain_counter = 0;
1063 pp->dma_cancelled = FALSE;
1064 pp->io_mode = ECPP_DMA;
1065 pp->joblen = 0;
1066 pp->tfifo_intr = 0;
1067 pp->softintr_pending = 0;
1068 pp->nread = 0;
1071 pp->e_busy = ECPP_IDLE;
1073 pp->readq = RD(q);
1074 pp->writeq = WR(q);
1075 pp->msg = NULL;
1077 RD(q)->q_ptr = WR(q)->q_ptr = (caddr_t)pp;
1082 if (ecpp_reset_port_regs(pp) == FAILURE) {
1083 mutex_exit(&pp->umutex);
1087 mutex_exit(&pp->umutex);
1113 mutex_enter(&pp->umutex);
1115 ecpp_default_negotiation(pp);
1118 (void) ecpp_idle_phase(pp);
1120 ecpp_error(pp->dip,
1122 pp->current_mode, pp->current_phase,
1123 ECR_READ(pp), DSR_READ(pp), DCR_READ(pp));
1125 mutex_exit(&pp->umutex);
1134 struct ecppunit *pp;
1137 pp = (struct ecppunit *)q->q_ptr;
1139 ecpp_error(pp->dip, "ecpp_close: entering ...\n");
1141 mutex_enter(&pp->umutex);
1155 while (pp->e_busy != ECPP_IDLE || qsize(WR(q))) {
1156 if (!cv_wait_sig(&pp->pport_cv, &pp->umutex)) {
1157 ecpp_error(pp->dip, "ecpp_close:B: received SIG\n");
1162 ecpp_flush(pp, FWRITE);
1165 ecpp_error(pp->dip, "ecpp_close:rcvd cv-sig\n");
1169 ecpp_error(pp->dip, "ecpp_close: joblen=%d, ctx_cf=%d, "
1171 pp->joblen, pp->ctx_cf, qsize(pp->writeq), qsize(q));
1181 timeout_id = pp->timeout_id;
1182 fifo_timer_id = pp->fifo_timer_id;
1183 wsrv_timer_id = pp->wsrv_timer_id;
1185 pp->timeout_id = pp->fifo_timer_id = pp->wsrv_timer_id = 0;
1187 pp->softintr_pending = 0;
1188 pp->dma_cancelled = TRUE;
1189 ECPP_MASK_INTR(pp);
1191 mutex_exit(&pp->umutex);
1205 mutex_enter(&pp->umutex);
1208 if ((pp->current_mode == ECPP_ECP_MODE) &&
1209 (pp->current_phase != ECPP_PHASE_ECP_FWD_IDLE)) {
1210 (void) ecp_reverse2forward(pp);
1213 (void) ecpp_1284_termination(pp);
1215 pp->oflag = FALSE;
1217 pp->readq = pp->writeq = NULL;
1218 pp->msg = NULL;
1220 ecpp_error(pp->dip, "ecpp_close: ecr=%x, dsr=%x, dcr=%x\n",
1221 ECR_READ(pp), DSR_READ(pp), DCR_READ(pp));
1223 mutex_exit(&pp->umutex);
1235 struct ecppunit *pp;
1237 pp = (struct ecppunit *)q->q_ptr;
1244 ecpp_error(pp->dip,
1264 ecpp_error(pp->dip,
1285 ecpp_error(pp->dip, "ecpp_wput:M_IOCTL %x\n", iocbp->ioc_cmd);
1287 mutex_enter(&pp->umutex);
1290 if ((pp->e_busy == ECPP_BUSY) &&
1293 mutex_exit(&pp->umutex);
1296 mutex_exit(&pp->umutex);
1306 ecpp_error(pp->dip, "ecpp_wput:M_IOCDATA\n");
1370 ecpp_error(pp->dip, "ecpp_wput:M_FLUSH\n");
1373 mutex_enter(&pp->umutex);
1374 ecpp_flush(pp, FWRITE);
1375 mutex_exit(&pp->umutex);
1379 mutex_enter(&pp->umutex);
1380 ecpp_flush(pp, FREAD);
1381 mutex_exit(&pp->umutex);
1396 mutex_enter(&pp->umutex);
1397 if (pp->e_busy == ECPP_IDLE) {
1398 pp->nread += *(size_t *)mp->b_rptr;
1399 ecpp_error(pp->dip, "ecpp_wput: M_READ %d", pp->nread);
1402 ecpp_error(pp->dip, "ecpp_wput: M_READ queueing");
1405 mutex_exit(&pp->umutex);
1409 ecpp_error(pp->dip, "ecpp_wput: bad messagetype 0x%x\n",
1501 struct ecppunit *pp;
1503 pp = (struct ecppunit *)q->q_ptr;
1523 mutex_enter(&pp->umutex);
1525 pp->xfer_parms.mode = pp->current_mode;
1526 xfer_parms = pp->xfer_parms;
1528 mutex_exit(&pp->umutex);
1535 mutex_enter(&pp->umutex);
1536 if (pp->current_mode != ECPP_DIAG_MODE) {
1537 mutex_exit(&pp->umutex);
1541 mutex_exit(&pp->umutex);
1551 mutex_enter(&pp->umutex);
1553 if (pp->current_mode != ECPP_DIAG_MODE) {
1554 mutex_exit(&pp->umutex);
1559 rg.dsr = DSR_READ(pp);
1560 rg.dcr = DCR_READ(pp);
1562 mutex_exit(&pp->umutex);
1564 ecpp_error(pp->dip, "ECPPIOC_GETREGS: dsr=%x,dcr=%x\n",
1577 mutex_enter(&pp->umutex);
1578 if (pp->current_mode != ECPP_DIAG_MODE) {
1579 mutex_exit(&pp->umutex);
1583 mutex_exit(&pp->umutex);
1597 mutex_enter(&pp->umutex);
1600 if (pp->current_mode != ECPP_DIAG_MODE) {
1601 mutex_exit(&pp->umutex);
1607 byte = pp->port;
1609 switch (pp->port) {
1611 byte = DATAR_READ(pp);
1614 byte = TFIFO_READ(pp);
1615 ecpp_error(pp->dip, "GETDATA=0x%x\n", byte);
1622 mutex_exit(&pp->umutex);
1623 ecpp_error(pp->dip, "weird command");
1628 mutex_exit(&pp->umutex);
1638 mutex_enter(&pp->umutex);
1640 bpp_status.timeout_occurred = pp->timeout_error;
1642 bpp_status.pin_status = ecpp_get_error_status(pp->saved_dsr);
1644 mutex_exit(&pp->umutex);
1652 mutex_enter(&pp->umutex);
1654 if (!((pp->current_mode == ECPP_CENTRONICS) ||
1655 (pp->current_mode == ECPP_COMPAT_MODE))) {
1658 pp->saved_dsr = DSR_READ(pp);
1660 if ((pp->saved_dsr & ECPP_PE) ||
1661 !(pp->saved_dsr & ECPP_SLCT) ||
1662 !(pp->saved_dsr & ECPP_nERR)) {
1669 mutex_exit(&pp->umutex);
1678 mutex_enter(&pp->umutex);
1679 if (pp->e_busy == ECPP_BUSY) {
1680 mutex_exit(&pp->umutex);
1683 (void) ecpp_mode_negotiation(pp, ECPP_CENTRONICS);
1685 DCR_WRITE(pp, ECPP_SLCTIN);
1687 DCR_WRITE(pp, ECPP_SLCTIN | ECPP_nINIT);
1689 ecpp_default_negotiation(pp);
1691 mutex_exit(&pp->umutex);
1699 mutex_enter(&pp->umutex);
1701 ifcap = ecpp_get_prn_ifcap(pp);
1703 mutex_exit(&pp->umutex);
1718 mutex_enter(&pp->umutex);
1719 timeouts = pp->prn_timeouts;
1720 mutex_exit(&pp->umutex);
1737 mutex_enter(&pp->umutex);
1740 if (pp->current_mode == ECPP_CENTRONICS ||
1741 pp->current_mode == ECPP_COMPAT_MODE) {
1742 dsr = DSR_READ(pp);
1753 mutex_exit(&pp->umutex);
1763 mutex_enter(&pp->umutex);
1766 if (pp->current_mode != ECPP_COMPAT_MODE &&
1767 pp->current_mode != ECPP_CENTRONICS) {
1768 mutex_exit(&pp->umutex);
1773 dsr = DSR_READ(pp); /* read status */
1775 mutex_exit(&pp->umutex);
1777 ecpp_error(pp->dip, "PRNIOC_GET_STATUS: %x\n", dsr);
1802 ecpp_error(pp->dip, "putioc: unknown IOCTL: %x\n",
1873 struct ecppunit *pp = (struct ecppunit *)q->q_ptr;
1875 mutex_enter(&pp->umutex);
1877 if (pp->e_busy == ECPP_IDLE) {
1878 (void) ecpp_idle_phase(pp);
1879 cv_signal(&pp->pport_cv); /* signal ecpp_close() */
1882 mutex_exit(&pp->umutex);
1891 struct ecppunit *pp = (struct ecppunit *)q->q_ptr;
1898 mutex_enter(&pp->umutex);
1900 ecpp_error(pp->dip, "ecpp_wsrv: e_busy=%x\n", pp->e_busy);
1903 if (pp->e_busy == ECPP_BUSY || pp->e_busy == ECPP_FLUSH) {
1904 mutex_exit(&pp->umutex);
1906 } else if (pp->suspended == TRUE) {
1911 cv_signal(&pp->pport_cv);
1912 mutex_exit(&pp->umutex);
1917 if (pp->e_busy == ECPP_ERR) {
1918 if (ecpp_check_status(pp) == FAILURE) {
1919 if (pp->wsrv_timer_id == 0) {
1920 ecpp_error(pp->dip, "wsrv: start wrsv_timer\n");
1921 pp->wsrv_timer_id = timeout(ecpp_wsrv_timer,
1922 (caddr_t)pp,
1923 drv_usectohz(pp->wsrv_retry * 1000));
1925 ecpp_error(pp->dip,
1929 mutex_exit(&pp->umutex);
1932 pp->e_busy = ECPP_IDLE;
1936 my_ioblock = pp->ioblock;
1940 * it`s important to null pp->msg here,
1943 pp->msg = NULL;
1953 * ioblock buffer. The pp->e_busy is set to E_BUSY as soon as
1959 pp->e_busy = ECPP_BUSY;
1969 pp->msg = mp;
1985 start_addr = (caddr_t)pp->ioblock;
2005 ecpp_error(pp->dip, "M_IOCTL.\n");
2007 mutex_exit(&pp->umutex);
2011 mutex_enter(&pp->umutex);
2018 ecpp_error(pp->dip, "M_IOCDATA\n");
2050 if (pp->e_busy != ECPP_IDLE) {
2051 ecpp_error(pp->dip, "wsrv: M_CTL postponed\n");
2055 ecpp_error(pp->dip, "wsrv: M_CTL\n");
2061 ecpp_error(pp->dip, "wsrv: bogus M_CTL");
2069 (void) ecpp_peripheral2host(pp);
2072 if (pp->e_busy == ECPP_BUSY) {
2078 pp->nread += *(size_t *)mp->b_rptr;
2080 ecpp_error(pp->dip, "wsrv: M_READ %d", pp->nread);
2084 ecpp_error(pp->dip, "wsrv: should never get here\n");
2094 ecpp_error(pp->dip, "wsrv:starting: total_len=%d\n", total_len);
2095 pp->e_busy = ECPP_BUSY;
2096 ecpp_start(pp, start_addr, total_len);
2098 ecpp_error(pp->dip, "wsrv:finishing: ebusy=%x\n", pp->e_busy);
2101 if (pp->e_busy == ECPP_IDLE) {
2102 (void) ecpp_idle_phase(pp);
2103 cv_signal(&pp->pport_cv); /* signal ecpp_close() */
2107 mutex_exit(&pp->umutex);
2118 struct ecppunit *pp;
2121 pp = (struct ecppunit *)q->q_ptr;
2144 pp->xfer_parms = *xferp;
2145 pp->prn_timeouts.tmo_forward = pp->xfer_parms.write_timeout;
2147 ecpp_error(pp->dip, "srvioc: current_mode =%x new mode=%x\n",
2148 pp->current_mode, pp->xfer_parms.mode);
2150 if (ecpp_mode_negotiation(pp, pp->xfer_parms.mode) == FAILURE) {
2157 if ((pp->current_mode == ECPP_NIBBLE_MODE) &&
2158 (read_nibble_backchan(pp) == FAILURE)) {
2170 if (pp->current_mode != ECPP_DIAG_MODE) {
2171 pp->port = ECPP_PORT_DMA;
2173 pp->port = ECPP_PORT_PIO;
2176 pp->xfer_parms.mode = pp->current_mode;
2188 if (pp->current_mode != ECPP_DIAG_MODE) {
2201 dcr = DCR_READ(pp) & ~ECPP_REV_DIR;
2205 DCR_WRITE(pp, dcr);
2206 ecpp_error(pp->dip, "ECPPIOC_SETREGS:dcr=%x\n", dcr);
2217 if (pp->current_mode != ECPP_DIAG_MODE) {
2225 ECR_WRITE(pp,
2227 pp->port = *port;
2232 ecpp_error(pp->dip, "SETPORT: to TDMA\n");
2233 pp->tfifo_intr = 1;
2235 ECR_WRITE(pp,
2237 pp->port = *port;
2254 if (pp->current_mode != ECPP_DIAG_MODE) {
2259 switch (pp->port) {
2261 DATAR_WRITE(pp, *data);
2266 TFIFO_WRITE(pp, *data);
2342 ifcap = ecpp_get_prn_ifcap(pp);
2357 ecpp_default_negotiation(pp);
2359 (void) ecpp_mode_negotiation(pp, ECPP_CENTRONICS);
2376 pp->prn_timeouts = *prn_timeouts;
2377 pp->xfer_parms.write_timeout = (int)prn_timeouts->tmo_forward;
2396 struct ecppunit *pp;
2404 pp = (struct ecppunit *)q->q_ptr;
2411 ecpp_error(pp->dip, "ecpp_srvioc_devid: mode=%x, len=%x\n",
2429 if (error = ecpp_getdevid(pp, NULL, &len, mode)) {
2457 error = ecpp_getdevid(pp, datamp->b_rptr, &len, mode);
2473 (void) ecpp_1284_termination(pp);
2545 ecpp_flush(struct ecppunit *pp, int cmd)
2551 ASSERT(mutex_owned(&pp->umutex));
2557 q = pp->writeq;
2560 ecpp_error(pp->dip, "ecpp_flush e_busy=%x\n", pp->e_busy);
2563 switch (pp->e_busy) {
2569 pp->e_busy = ECPP_FLUSH;
2583 pp->dma_cancelled = TRUE;
2586 if (COMPAT_DMA(pp) ||
2587 (pp->current_mode == ECPP_ECP_MODE) ||
2588 (pp->current_mode == ECPP_DIAG_MODE)) {
2594 if (ECPP_DMA_STOP(pp, NULL) == FAILURE) {
2595 ecpp_error(pp->dip,
2606 pp->dma_handle) != DDI_SUCCESS)
2607 ecpp_error(pp->dip,
2610 if (pp->msg != NULL) {
2611 freemsg(pp->msg);
2612 pp->msg = NULL;
2618 dcr = DCR_READ(pp);
2620 DCR_WRITE(pp, dcr);
2621 ECPP_MASK_INTR(pp);
2632 timeout_id = pp->timeout_id;
2633 fifo_timer_id = pp->fifo_timer_id;
2634 pp->timeout_id = pp->fifo_timer_id = 0;
2635 pp->softintr_pending = 0;
2644 pp->e_busy = ECPP_FLUSH;
2653 wsrv_timer_id = pp->wsrv_timer_id;
2654 pp->wsrv_timer_id = 0;
2663 ecpp_error(pp->dip,
2664 "ecpp_flush: illegal state %x\n", pp->e_busy);
2668 if (pp->current_mode == ECPP_DIAG_MODE) {
2669 ecr = ECR_READ(pp);
2671 ECR_WRITE(pp,
2673 ECR_WRITE(pp, ecr);
2681 pp->e_busy = ECPP_IDLE;
2684 if (pp->current_mode == ECPP_ECP_MODE) {
2685 if (pp->current_phase == ECPP_PHASE_ECP_REV_XFER) {
2686 pp->current_phase = ECPP_PHASE_ECP_REV_IDLE;
2688 pp->current_phase = ECPP_PHASE_ECP_FWD_IDLE;
2693 mutex_exit(&pp->umutex);
2705 mutex_enter(&pp->umutex);
2707 cv_signal(&pp->pport_cv); /* wake up ecpp_close() */
2711 ecpp_start(struct ecppunit *pp, caddr_t addr, size_t len)
2713 ASSERT(mutex_owned(&pp->umutex));
2714 ASSERT(pp->e_busy == ECPP_BUSY);
2716 ecpp_error(pp->dip,
2718 pp->current_mode, pp->current_phase, ECR_READ(pp), len);
2720 pp->dma_dir = DDI_DMA_WRITE; /* this is a forward transfer */
2722 switch (pp->current_mode) {
2724 (void) ecpp_1284_termination(pp);
2732 if (pp->io_mode == ECPP_DMA) {
2733 if (ecpp_init_dma_xfer(pp, addr, len) == FAILURE) {
2738 if (ecpp_prep_pio_xfer(pp, addr, len) == FAILURE) {
2741 (void) ecpp_pio_writeb(pp);
2749 ECR_WRITE(pp, ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_110);
2755 if (!(ECR_READ(pp) & ECPP_FIFO_EMPTY)) {
2756 ecpp_error(pp->dip,
2758 ECR_WRITE(pp,
2760 ECR_WRITE(pp,
2770 if (ecpp_init_dma_xfer(pp, addr, len) == FAILURE) {
2776 ecpp_putback_untransfered(pp, addr + len, oldlen - len);
2783 ASSERT(pp->current_phase == ECPP_PHASE_ECP_FWD_IDLE ||
2784 pp->current_phase == ECPP_PHASE_ECP_REV_IDLE);
2787 if (pp->current_phase == ECPP_PHASE_ECP_REV_IDLE) {
2788 if (ecp_reverse2forward(pp) == FAILURE) {
2789 if (pp->msg) {
2790 (void) putbq(pp->writeq, pp->msg);
2792 ecpp_putback_untransfered(pp,
2798 if (ecpp_init_dma_xfer(pp, addr, len) == FAILURE) {
2806 pp->timeout_id = timeout(ecpp_xfer_timeout, (caddr_t)pp,
2807 pp->xfer_parms.write_timeout * drv_usectohz(1000000));
2812 * The block is starts at addr and ends at pp->last_byte
2815 ecpp_prep_pio_xfer(struct ecppunit *pp, caddr_t addr, size_t len)
2817 pp->next_byte = addr;
2818 pp->last_byte = (caddr_t)((ulong_t)addr + len);
2820 if (ecpp_check_status(pp) == FAILURE) {
2825 ecpp_error(pp->dip,
2828 if (pp->msg != NULL) {
2834 ecpp_putback_untransfered(pp,
2835 (void *)pp->msg->b_rptr, len);
2836 ecpp_error(pp->dip,
2839 freemsg(pp->msg);
2840 pp->msg = NULL;
2842 ecpp_putback_untransfered(pp, pp->ioblock, len);
2843 ecpp_error(pp->dip,
2846 qenable(pp->writeq);
2851 pp->dma_cancelled = FALSE;
2854 if (ecr_write(pp, ECR_mode_001 |
2856 ecpp_error(pp->dip, "ecpp_prep_pio_xfer: failed w/ECR.\n");
2859 ecpp_error(pp->dip, "ecpp_prep_pio_xfer: dcr=%x ecr=%x\n",
2860 DCR_READ(pp), ECR_READ(pp));
2866 ecpp_init_dma_xfer(struct ecppunit *pp, caddr_t addr, size_t len)
2880 ASSERT((pp->current_mode <= ECPP_DIAG_MODE) &&
2881 (ecr_mode[pp->current_mode] != 0));
2883 if (ecpp_setup_dma_resources(pp, addr, len) == FAILURE) {
2884 qenable(pp->writeq);
2888 if (ecpp_check_status(pp) == FAILURE) {
2893 ecpp_error(pp->dip,
2895 pp->dma_cookie.dmac_size);
2897 if (pp->msg != NULL) {
2903 ecpp_putback_untransfered(pp,
2904 (void *)pp->msg->b_rptr, len);
2905 ecpp_error(pp->dip,
2908 freemsg(pp->msg);
2909 pp->msg = NULL;
2911 ecpp_putback_untransfered(pp, pp->ioblock, len);
2912 ecpp_error(pp->dip,
2916 if (ddi_dma_unbind_handle(pp->dma_handle) != DDI_SUCCESS) {
2917 ecpp_error(pp->dip,
2920 qenable(pp->writeq);
2924 pp->xfercnt = pp->resid = len;
2925 pp->dma_cancelled = FALSE;
2926 pp->tfifo_intr = 0;
2929 ecr = ecr_mode[pp->current_mode];
2930 (void) ecr_write(pp, ecr | ECPP_INTR_SRV | ECPP_INTR_MASK);
2933 if (ECPP_DMA_START(pp) == FAILURE) {
2934 ecpp_error(pp->dip, "ecpp_init_dma_xfer: dma_start FAILED.\n");
2939 (void) ecr_write(pp, ecr | ECPP_DMA_ENABLE | ECPP_INTR_MASK);
2945 ecpp_setup_dma_resources(struct ecppunit *pp, caddr_t addr, size_t len)
2951 ASSERT(pp->dma_dir == DDI_DMA_READ || pp->dma_dir == DDI_DMA_WRITE);
2953 err = ddi_dma_addr_bind_handle(pp->dma_handle, NULL,
2954 addr, len, pp->dma_dir | DDI_DMA_PARTIAL,
2956 &pp->dma_cookie, &pp->dma_cookie_count);
2960 ecpp_error(pp->dip, "ecpp_setup_dma: DMA_MAPPED\n");
2962 pp->dma_nwin = 1;
2963 pp->dma_curwin = 1;
2967 ecpp_error(pp->dip, "ecpp_setup_dma: DMA_PARTIAL_MAP\n");
2969 if (ddi_dma_numwin(pp->dma_handle,
2970 &pp->dma_nwin) != DDI_SUCCESS) {
2971 (void) ddi_dma_unbind_handle(pp->dma_handle);
2974 pp->dma_curwin = 1;
2981 if (ddi_dma_getwin(pp->dma_handle, 0, &woff, &wlen,
2982 &pp->dma_cookie, &pp->dma_cookie_count) != DDI_SUCCESS) {
2983 ecpp_error(pp->dip,
2985 (void) ddi_dma_unbind_handle(pp->dma_handle);
2989 ecpp_error(pp->dip,
2992 pp->dma_cookie_count, pp->dma_nwin,
2993 pp->dma_cookie.dmac_address, pp->dma_cookie.dmac_size);
2999 ecpp_error(pp->dip, "ecpp_setup_dma: err=%x\n", err);
3048 struct ecppunit *pp = (struct ecppunit *)(void *)arg;
3055 mutex_enter(&pp->umutex);
3063 if (pp->dma_cancelled == TRUE) {
3064 ecpp_error(pp->dip, "dma-cancel isr\n");
3066 pp->intr_hard++;
3067 pp->dma_cancelled = FALSE;
3069 mutex_exit(&pp->umutex);
3075 if (pp->hw == &x86)
3077 if (pp->hw == &m1553)
3080 retval = ecpp_M1553_intr(pp);
3084 mutex_exit(&pp->umutex);
3093 dcsr = GET_DMAC_CSR(pp);
3097 dcsr = GET_DMAC_CSR(pp);
3107 if (!COMPAT_PIO(pp)) {
3109 dcsr = GET_DMAC_CSR(pp);
3113 dsr = DSR_READ(pp);
3121 if (pp->hw != &pc97317) {
3138 ((COMPAT_PIO(pp)) && (pp->e_busy == ECPP_BUSY)) ||
3140 (pp->current_mode == ECPP_ECP_MODE))) {
3147 pp->intr_hard++;
3154 ASSERT(pp->e_busy == ECPP_BUSY);
3159 if (ECPP_DMA_STOP(pp, &bcr) == FAILURE) {
3160 ecpp_error(pp->dip, "ecpp_isr: dma_stop failed\n");
3163 ecpp_error(pp->dip, "ecpp_isr: DMAC ERROR bcr=%d\n", bcr);
3165 ecpp_xfer_cleanup(pp);
3167 if (ddi_dma_unbind_handle(pp->dma_handle) != DDI_SUCCESS) {
3168 ecpp_error(pp->dip, "ecpp_isr(e): unbind failed\n");
3171 mutex_exit(&pp->umutex);
3176 retval = ecpp_dma_ihdlr(pp);
3177 mutex_exit(&pp->umutex);
3181 if (COMPAT_PIO(pp)) {
3182 retval = ecpp_pio_ihdlr(pp);
3183 mutex_exit(&pp->umutex);
3189 retval = ecpp_nErr_ihdlr(pp);
3190 mutex_exit(&pp->umutex);
3194 pp->intr_hard--;
3198 pp->intr_spurious++;
3207 if (pp->lastspur == 0 || now - pp->lastspur > SPUR_PERIOD) {
3209 pp->lastspur = now;
3210 pp->nspur = 1;
3213 pp->nspur++;
3216 if (pp->nspur >= SPUR_CRITICAL) {
3217 ECPP_MASK_INTR(pp);
3218 ECR_WRITE(pp, ECR_READ(pp) | ECPP_INTR_MASK | ECPP_INTR_SRV);
3219 pp->nspur = 0;
3221 ddi_get_name(pp->dip), ddi_get_instance(pp->dip));
3223 ECR_WRITE(pp, ECR_READ(pp) | ECPP_INTR_SRV | ECPP_INTR_MASK);
3226 ecpp_error(pp->dip,
3228 dcsr, ECR_READ(pp), dsr, DCR_READ(pp),
3229 pp->current_mode, pp->current_phase);
3231 mutex_exit(&pp->umutex);
3236 pp->intr_spurious++;
3238 ecpp_error(pp->dip,
3240 dcsr, ECR_READ(pp), DSR_READ(pp), DCR_READ(pp),
3241 pp->current_mode, pp->current_phase);
3243 mutex_exit(&pp->umutex);
3251 ecpp_M1553_intr(struct ecppunit *pp)
3255 pp->intr_hard++;
3257 if (pp->e_busy == ECPP_BUSY) {
3259 if (COMPAT_PIO(pp)) {
3260 return (ecpp_pio_ihdlr(pp));
3264 if (COMPAT_DMA(pp) ||
3265 (pp->current_mode == ECPP_ECP_MODE) ||
3266 (pp->current_mode == ECPP_DIAG_MODE)) {
3267 return (ecpp_dma_ihdlr(pp));
3272 if ((DSR_READ(pp) & ECPP_nERR) == 0) {
3273 return (ecpp_nErr_ihdlr(pp));
3283 ecpp_dma_ihdlr(struct ecppunit *pp)
3287 ecpp_error(pp->dip, "ecpp_dma_ihdlr(%x): ecr=%x, dsr=%x, dcr=%x\n",
3288 pp->current_mode, ECR_READ(pp), DSR_READ(pp), DCR_READ(pp));
3291 ASSERT(pp->e_busy == ECPP_BUSY);
3294 if (pp->tfifo_intr == 1) {
3295 pp->tfifo_intr = 0;
3296 ecpp_error(pp->dip, "ecpp_dma_ihdlr: tfifo_intr is 1\n");
3300 if (ECPP_DMA_STOP(pp, NULL) == FAILURE) {
3301 ecpp_error(pp->dip, "ecpp_dma_ihdlr: dma_stop failed\n");
3304 if (pp->current_mode == ECPP_ECP_MODE &&
3305 pp->current_phase == ECPP_PHASE_ECP_REV_XFER) {
3306 ecpp_ecp_read_completion(pp);
3311 if ((ECR_READ(pp) & ECPP_FIFO_EMPTY) ||
3312 (pp->current_mode == ECPP_DIAG_MODE)) {
3317 pp->fifo_timer_id = timeout(ecpp_fifo_timer, (caddr_t)pp, tm);
3325 ecpp_untimeout_unblock(pp, &pp->timeout_id);
3335 ecpp_pio_ihdlr(struct ecppunit *pp)
3337 ASSERT(mutex_owned(&pp->umutex));
3338 ASSERT(pp->e_busy == ECPP_BUSY);
3341 pp->joblen++;
3342 pp->ctxpio_obytes++;
3345 ECPP_MASK_INTR(pp);
3346 DCR_WRITE(pp, DCR_READ(pp) & ~(ECPP_REV_DIR | ECPP_INTR_EN));
3352 if (pp->next_byte >= pp->last_byte) {
3353 ecpp_xfer_cleanup(pp);
3354 ecpp_error(pp->dip,
3355 "ecpp_pio_ihdlr: pp->joblen=%d,pp->ctx_cf=%d,\n",
3356 pp->joblen, pp->ctx_cf);
3358 if (pp->softintr_pending) {
3359 ecpp_error(pp->dip,
3362 pp->softintr_flags = ECPP_SOFTINTR_PIONEXT;
3363 pp->softintr_pending = 1;
3364 ddi_trigger_softintr(pp->softintr_id);
3375 ecpp_pio_writeb(struct ecppunit *pp)
3379 dcr = DCR_READ(pp) & ~ECPP_REV_DIR;
3383 DATAR_WRITE(pp, *(pp->next_byte++));
3385 drv_usecwait(pp->data_setup_time);
3388 if (dcr_write(pp, dcr | ECPP_STB) == FAILURE) {
3389 ecpp_error(pp->dip, "ecpp_pio_writeb:1: failed w/DCR\n");
3393 (void) DSR_READ(pp); /* ensure IRQ_ST is armed */
3394 ECPP_UNMASK_INTR(pp);
3396 drv_usecwait(pp->strobe_pulse_width);
3398 if (dcr_write(pp, dcr & ~ECPP_STB) == FAILURE) {
3399 ecpp_error(pp->dip, "ecpp_pio_writeb:2: failed w/DCR\n");
3407 ecpp_nErr_ihdlr(struct ecppunit *pp)
3409 ecpp_error(pp->dip, "ecpp_nErr_ihdlr: mode=%x, phase=%x\n",
3410 pp->current_mode, pp->current_phase);
3412 if (pp->oflag != TRUE) {
3413 ecpp_error(pp->dip, "ecpp_nErr_ihdlr: not open!\n");
3417 if (pp->e_busy == ECPP_BUSY) {
3418 ecpp_error(pp->dip, "ecpp_nErr_ihdlr: busy\n");
3419 ECR_WRITE(pp, ECR_READ(pp) | ECPP_INTR_MASK);
3424 ECPP_MASK_INTR(pp);
3425 DCR_WRITE(pp, DCR_READ(pp) & ~(ECPP_INTR_EN | ECPP_REV_DIR));
3426 ECR_WRITE(pp, ECR_READ(pp) | ECPP_INTR_MASK);
3429 switch (pp->current_mode) {
3443 pp->current_phase = ECPP_PHASE_NIBT_REVINTR;
3447 ecpp_error(pp->dip, "ecpp_nErr_ihdlr: wrong mode!\n");
3451 (void) ecpp_backchan_req(pp); /* put backchannel request on the wq */
3463 struct ecppunit *pp = (struct ecppunit *)arg;
3466 mutex_enter(&pp->umutex);
3468 pp->intr_soft++;
3470 if (!pp->softintr_pending) {
3471 mutex_exit(&pp->umutex);
3474 pp->softintr_pending = 0;
3477 if (pp->softintr_flags & ECPP_SOFTINTR_PIONEXT) {
3478 pp->softintr_flags &= ~ECPP_SOFTINTR_PIONEXT;
3484 if (ecpp_check_status(pp) == SUCCESS) {
3485 pp->e_busy = ECPP_BUSY;
3489 if (pp->isr_reattempt_high < ecpp_reattempts) {
3490 pp->isr_reattempt_high = ecpp_reattempts;
3492 } while (++ecpp_reattempts < pp->wait_for_busy);
3495 if (pp->e_busy == ECPP_ERR) {
3496 ++pp->ctx_cf; /* check status fail */
3497 ecpp_error(pp->dip, "ecpp_softintr:check_status:F: "
3499 DSR_READ(pp), pp->joblen, pp->ctx_cf);
3505 unx_len = pp->last_byte - pp->next_byte;
3506 if (pp->msg != NULL) {
3507 ecpp_putback_untransfered(pp,
3508 (void *)pp->msg->b_rptr, unx_len);
3509 ecpp_error(pp->dip,
3512 freemsg(pp->msg);
3513 pp->msg = NULL;
3515 ecpp_putback_untransfered(pp,
3516 pp->next_byte, unx_len);
3517 ecpp_error(pp->dip,
3521 ecpp_xfer_cleanup(pp);
3522 pp->e_busy = ECPP_ERR;
3523 qenable(pp->writeq);
3526 pp->e_busy = ECPP_BUSY;
3527 (void) ecpp_pio_writeb(pp);
3531 mutex_exit(&pp->umutex);
3543 ecpp_xfer_cleanup(struct ecppunit *pp)
3545 ASSERT(mutex_owned(&pp->umutex));
3551 if (pp->msg != NULL) {
3552 freemsg(pp->msg);
3553 pp->msg = NULL;
3557 pp->e_busy = ECPP_IDLE;
3560 ecpp_untimeout_unblock(pp, &pp->timeout_id);
3562 qenable(pp->writeq);
3614 struct ecppunit *pp = arg;
3620 mutex_enter(&pp->umutex);
3622 if (pp->timeout_id == 0) {
3623 mutex_exit(&pp->umutex);
3626 pp->timeout_id = 0;
3629 pp->xfer_tout++;
3631 pp->dma_cancelled = TRUE; /* prevent race with isr() */
3633 if (COMPAT_PIO(pp)) {
3639 dcr = DCR_READ(pp);
3640 (void) dcr_write(pp, dcr & ~(ECPP_REV_DIR | ECPP_INTR_EN));
3641 ECPP_MASK_INTR(pp);
3643 pp->softintr_pending = 0;
3644 unx_len = pp->last_byte - pp->next_byte;
3645 ecpp_error(pp->dip, "xfer_timeout: unx_len=%d\n", unx_len);
3648 unx_addr = pp->next_byte;
3650 ecpp_xfer_cleanup(pp);
3651 qenable(pp->writeq);
3652 mutex_exit(&pp->umutex);
3662 if (ECPP_DMA_STOP(pp, &unx_len) == FAILURE) {
3663 ecpp_error(pp->dip,
3667 ecpp_error(pp->dip, "xfer_timeout: unx_len=%d\n", unx_len);
3669 if (ddi_dma_unbind_handle(pp->dma_handle) == DDI_FAILURE) {
3670 ecpp_error(pp->dip,
3680 qenable(pp->writeq);
3681 mutex_exit(&pp->umutex);
3684 xferd = pp->dma_cookie.dmac_size - unx_len;
3685 pp->resid -= xferd;
3686 unx_len = pp->resid;
3689 pp->obytes[pp->current_mode] += xferd;
3690 pp->joblen += xferd;
3692 if (pp->msg != NULL) {
3693 unx_addr = (caddr_t)pp->msg->b_wptr - unx_len;
3695 unx_addr = pp->ioblock +
3696 (pp->xfercnt - unx_len);
3703 ecpp_putback_untransfered(pp, (caddr_t)unx_addr, unx_len);
3705 if (pp->msg != NULL) {
3706 freemsg(pp->msg);
3707 pp->msg = NULL;
3711 pp->timeout_error = 1;
3712 pp->e_busy = ECPP_ERR;
3713 fifo_timer_id = pp->fifo_timer_id;
3714 pp->fifo_timer_id = 0;
3716 qenable(pp->writeq);
3718 mutex_exit(&pp->umutex);
3726 ecpp_putback_untransfered(struct ecppunit *pp, void *startp, uint_t len)
3730 ecpp_error(pp->dip, "ecpp_putback_untrans=%d\n", len);
3738 ecpp_error(pp->dip,
3746 if (!putbq(pp->writeq, new_mp)) {
3752 ecr_write(struct ecppunit *pp, uint8_t ecr_byte)
3757 ECR_WRITE(pp, ecr_byte);
3759 current_ecr = ECR_READ(pp);
3769 dcr_write(struct ecppunit *pp, uint8_t dcr_byte)
3775 DCR_WRITE(pp, dcr_byte);
3777 current_dcr = DCR_READ(pp);
3783 ecpp_error(pp->dip,
3791 ecpp_reset_port_regs(struct ecppunit *pp)
3793 DCR_WRITE(pp, ECPP_SLCTIN | ECPP_nINIT);
3794 ECR_WRITE(pp, ECR_mode_001 | ECPP_INTR_MASK | ECPP_INTR_SRV);
3807 struct ecppunit *pp = arg;
3811 mutex_enter(&pp->umutex);
3816 if (pp->fifo_timer_id == 0) {
3817 ecpp_error(pp->dip, "ecpp_fifo_timer: untimedout\n");
3818 mutex_exit(&pp->umutex);
3821 pp->fifo_timer_id = 0;
3829 ecr = ECR_READ(pp);
3831 if ((pp->current_mode != ECPP_DIAG_MODE) &&
3833 (pp->ecpp_drain_counter < 10))) {
3835 ecpp_error(pp->dip,
3837 pp->ecpp_drain_counter, ecr);
3839 pp->fifo_timer_id = timeout(ecpp_fifo_timer,
3840 (caddr_t)pp, drv_usectohz(FIFO_DRAIN_PERIOD));
3841 ++pp->ecpp_drain_counter;
3843 mutex_exit(&pp->umutex);
3847 if (pp->current_mode != ECPP_DIAG_MODE) {
3852 if (pp->ecpp_drain_counter >= 10) {
3853 ecpp_error(pp->dip, "ecpp_fifo_timer(%d):"
3855 pp->ecpp_drain_counter, ecr);
3857 ecpp_error(pp->dip,
3859 pp->ecpp_drain_counter, ecr);
3862 pp->ecpp_drain_counter = 0;
3874 timeout_id = pp->timeout_id;
3875 pp->timeout_id = 0;
3878 if (pp->current_mode == ECPP_ECP_MODE ||
3879 pp->current_mode == ECPP_DIAG_MODE ||
3880 COMPAT_DMA(pp)) {
3885 pp->resid -= pp->dma_cookie.dmac_size;
3888 pp->joblen += pp->dma_cookie.dmac_size;
3889 if (pp->dma_dir == DDI_DMA_WRITE) {
3890 pp->obytes[pp->current_mode] +=
3891 pp->dma_cookie.dmac_size;
3893 pp->ibytes[pp->current_mode] +=
3894 pp->dma_cookie.dmac_size;
3900 if (--pp->dma_cookie_count > 0) {
3902 ddi_dma_nextcookie(pp->dma_handle,
3903 &pp->dma_cookie);
3904 } else if (pp->dma_curwin < pp->dma_nwin) {
3906 if (ddi_dma_getwin(pp->dma_handle,
3907 pp->dma_curwin, &off, &len,
3908 &pp->dma_cookie,
3909 &pp->dma_cookie_count) != DDI_SUCCESS) {
3910 ecpp_error(pp->dip,
3915 pp->dma_curwin++;
3920 ecpp_error(pp->dip, "ecpp_fifo_timer: next addr=%llx len=%d\n",
3921 pp->dma_cookie.dmac_address,
3922 pp->dma_cookie.dmac_size);
3925 if (ECPP_DMA_START(pp) != SUCCESS) {
3926 ecpp_error(pp->dip,
3931 (void) ecr_write(pp, (ecr & 0xe0) |
3934 mutex_exit(&pp->umutex);
3942 if (ddi_dma_unbind_handle(pp->dma_handle) != DDI_SUCCESS) {
3943 ecpp_error(pp->dip, "ecpp_fifo_timer: unbind failed\n");
3945 ecpp_error(pp->dip, "ecpp_fifo_timer: unbind ok\n");
3953 if (pp->msg != NULL) {
3954 freemsg(pp->msg);
3955 pp->msg = NULL;
3959 pp->e_busy = ECPP_IDLE;
3961 qenable(pp->writeq);
3963 mutex_exit(&pp->umutex);
3974 ecpp_check_status(struct ecppunit *pp)
3979 if (pp->current_mode == ECPP_ECP_MODE ||
3980 pp->current_mode == ECPP_DIAG_MODE)
3985 dsr = DSR_READ(pp);
3987 pp->e_busy = ECPP_ERR;
4002 struct ecppunit *pp = arg;
4004 ecpp_error(pp->dip, "ecpp_wsrv_timer: starting\n");
4006 mutex_enter(&pp->umutex);
4008 if (pp->wsrv_timer_id == 0) {
4009 mutex_exit(&pp->umutex);
4012 pp->wsrv_timer_id = 0;
4015 ecpp_error(pp->dip, "ecpp_wsrv_timer: qenabling...\n");
4017 qenable(pp->writeq);
4019 mutex_exit(&pp->umutex);
4027 ecpp_backchan_req(struct ecppunit *pp)
4032 ecpp_error(pp->dip, "ecpp_backchan_req: allocb failed\n");
4038 if (!putbq(pp->writeq, mp)) {
4039 ecpp_error(pp->dip, "ecpp_backchan_req:putbq failed\n");
4052 ecpp_untimeout_unblock(struct ecppunit *pp, timeout_id_t *id)
4056 ASSERT(mutex_owned(&pp->umutex));
4061 mutex_exit(&pp->umutex);
4063 mutex_enter(&pp->umutex);
4071 ecpp_get_prn_ifcap(struct ecppunit *pp)
4078 if (pp->current_mode == ECPP_CENTRONICS ||
4079 pp->current_mode == ECPP_COMPAT_MODE) {
4081 } else if (pp->current_mode == ECPP_NIBBLE_MODE ||
4082 pp->current_mode == ECPP_ECP_MODE) {
4093 ecpp_determine_sio_type(struct ecppunit *pp)
4099 name = ddi_binding_name(pp->dip);
4127 ecpp_1284_init_interface(struct ecppunit *pp)
4129 ECR_WRITE(pp, ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_001);
4135 if (pp->init_seq == TRUE) {
4136 DCR_WRITE(pp, ECPP_SLCTIN);
4140 DCR_WRITE(pp, ECPP_nINIT | ECPP_SLCTIN);
4142 pp->current_mode = pp->backchannel = ECPP_CENTRONICS;
4143 pp->current_phase = ECPP_PHASE_C_IDLE;
4144 ECPP_CONFIG_MODE(pp);
4145 pp->to_mode[pp->current_mode]++;
4147 ecpp_error(pp->dip, "ecpp_1284_init_interface: ok\n");
4154 ecp_negotiation(struct ecppunit *pp)
4160 if (ecpp_1284_negotiation(pp, ECPP_XREQ_ECP, &dsr) == FAILURE)
4166 ecpp_error(pp->dip,
4167 "ecp_negotiation: failed event 5 %x\n", DSR_READ(pp));
4168 (void) ecpp_1284_termination(pp);
4173 pp->current_phase = ECPP_PHASE_ECP_SETUP;
4176 DCR_WRITE(pp, ECPP_nINIT | ECPP_AFX);
4179 if (wait_dsr(pp, ECPP_PE, ECPP_PE, 35000) < 0) {
4180 ecpp_error(pp->dip,
4181 "ecp_negotiation: failed event 31 %x\n", DSR_READ(pp));
4182 (void) ecpp_1284_termination(pp);
4187 pp->current_phase = ECPP_PHASE_ECP_FWD_IDLE;
4190 pp->current_mode = ECPP_ECP_MODE;
4191 pp->backchannel = ECPP_ECP_MODE;
4193 ecpp_error(pp->dip, "ecp_negotiation: ok\n");
4202 nibble_negotiation(struct ecppunit *pp)
4206 if (ecpp_1284_negotiation(pp, ECPP_XREQ_NIBBLE, &dsr) == FAILURE) {
4215 pp->current_phase = ECPP_PHASE_NIBT_AVAIL;
4217 pp->current_phase = ECPP_PHASE_NIBT_NAVAIL;
4221 pp->current_mode = ECPP_NIBBLE_MODE;
4222 pp->backchannel = ECPP_NIBBLE_MODE;
4224 ecpp_error(pp->dip, "nibble_negotiation: ok (phase=%x)\n",
4225 pp->current_phase);
4237 wait_dsr(struct ecppunit *pp, uint8_t mask, uint8_t val, int ptimeout)
4239 while (((DSR_READ(pp) & mask) != val) && ptimeout--) {
4260 ecpp_1284_negotiation(struct ecppunit *pp, uint8_t xreq, uint8_t *rdsr)
4264 ecpp_error(pp->dip, "nego(%x): entering...\n", xreq);
4267 (void) ecpp_1284_termination(pp);
4270 ECR_WRITE(pp, ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_001);
4272 pp->current_phase = ECPP_PHASE_NEGO;
4275 DATAR_WRITE(pp, xreq);
4278 DCR_WRITE(pp, ECPP_nINIT | ECPP_AFX);
4286 if (wait_dsr(pp, ECPP_nERR | ECPP_SLCT | ECPP_PE | ECPP_nACK,
4289 ecpp_error(pp->dip,
4290 "nego(%x): failed event 2 %x\n", xreq, DSR_READ(pp));
4291 (void) ecpp_1284_termination(pp);
4299 DCR_WRITE(pp, ECPP_nINIT | ECPP_AFX | ECPP_STB);
4307 DCR_WRITE(pp, ECPP_nINIT);
4319 if (wait_dsr(pp, ECPP_nACK, ECPP_nACK, 35000) < 0) {
4321 ecpp_error(pp->dip,
4322 "nego(%x): failed event 6 %x\n", xreq, DSR_READ(pp));
4323 (void) ecpp_1284_termination(pp);
4327 if ((DSR_READ(pp) & ECPP_SLCT) != xflag) {
4329 ecpp_error(pp->dip,
4330 "nego(%x): failed event 5 %x\n", xreq, DSR_READ(pp));
4331 (void) ecpp_1284_termination(pp);
4336 *rdsr = DSR_READ(pp);
4356 ecpp_1284_termination(struct ecppunit *pp)
4358 int previous_mode = pp->current_mode;
4360 if (((pp->current_mode == ECPP_COMPAT_MODE ||
4361 pp->current_mode == ECPP_CENTRONICS) &&
4362 pp->current_phase == ECPP_PHASE_C_IDLE) ||
4363 pp->current_mode == ECPP_DIAG_MODE) {
4364 ecpp_error(pp->dip, "termination: not needed\n");
4369 ECPP_MASK_INTR(pp);
4370 ECR_WRITE(pp, ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_001);
4372 pp->current_mode = ECPP_COMPAT_MODE; /* needed by next function */
4374 ECPP_CONFIG_MODE(pp);
4381 DCR_WRITE(pp, 0);
4386 DCR_WRITE(pp, ECPP_nINIT | ECPP_SLCTIN);
4392 pp->current_phase = ECPP_PHASE_TERM;
4395 DCR_WRITE(pp, ECPP_nINIT | ECPP_SLCTIN);
4399 if (wait_dsr(pp, ECPP_nERR | ECPP_nBUSY | ECPP_nACK,
4401 ecpp_error(pp->dip,
4402 "termination: failed events 23,24 %x\n", DSR_READ(pp));
4403 ecpp_1284_init_interface(pp);
4410 DCR_WRITE(pp, ECPP_nINIT | ECPP_SLCTIN | ECPP_AFX);
4415 if (wait_dsr(pp, ECPP_nACK, ECPP_nACK, 35000) < 0) {
4416 ecpp_error(pp->dip,
4417 "termination: failed event 27 %x\n", DSR_READ(pp));
4418 ecpp_1284_init_interface(pp);
4425 DCR_WRITE(pp, ECPP_nINIT | ECPP_SLCTIN);
4431 pp->current_phase = ECPP_PHASE_C_IDLE;
4433 ecpp_error(pp->dip, "termination: completed %x %x\n",
4434 DSR_READ(pp), DCR_READ(pp));
4443 ecp_peripheral2host(struct ecppunit *pp)
4449 ASSERT(pp->current_mode == ECPP_ECP_MODE &&
4450 pp->current_phase == ECPP_PHASE_ECP_REV_IDLE);
4462 if (pp->nread > 0) {
4463 len = min(pp->nread, ECP_REV_BLKSZ_MAX);
4468 pp->nread = 0; /* clear after use */
4475 ecpp_error(pp->dip,
4488 pp->msg = mp;
4489 pp->e_busy = ECPP_BUSY;
4490 pp->dma_dir = DDI_DMA_READ;
4491 pp->current_phase = ECPP_PHASE_ECP_REV_XFER;
4493 if (ecpp_init_dma_xfer(pp, (caddr_t)mp->b_rptr, len) == FAILURE) {
4531 xfer_time = max((1000 * len) / pp->ecp_rev_speed, ECP_REV_MINTOUT);
4533 pp->rev_timeout_cnt = (pp->hw == &x86) ? 1 :
4534 max(xfer_time / pp->rev_watchdog, 1);
4536 pp->rev_timeout_cnt = (pp->hw == &m1553) ? 1 :
4537 max(xfer_time / pp->rev_watchdog, 1);
4540 pp->last_dmacnt = len; /* nothing xferred yet */
4542 pp->timeout_id = timeout(ecpp_ecp_read_timeout, (caddr_t)pp,
4543 drv_usectohz(pp->rev_watchdog * 1000));
4545 ecpp_error(pp->dip, "ecp_periph2host: DMA started len=%d\n"
4547 len, xfer_time, pp->rev_watchdog, pp->rev_timeout_cnt);
4555 pp->e_busy = ECPP_IDLE;
4556 pp->current_phase = ECPP_PHASE_ECP_REV_IDLE;
4570 struct ecppunit *pp = arg;
4573 mutex_enter(&pp->umutex);
4575 if (pp->timeout_id == 0) {
4576 mutex_exit(&pp->umutex);
4579 pp->timeout_id = 0;
4582 if (--pp->rev_timeout_cnt == 0) {
4586 ecpp_error(pp->dip, "ecp_read_timeout: timeout\n");
4587 pp->xfer_tout++;
4588 ecpp_ecp_read_completion(pp);
4594 dmacnt = ECPP_DMA_GETCNT(pp);
4595 if (dmacnt - pp->last_dmacnt == 0) {
4600 ecpp_error(pp->dip, "ecp_read_timeout: no progress\n");
4601 pp->xfer_tout++;
4602 ecpp_ecp_read_completion(pp);
4607 ecpp_error(pp->dip, "ecp_read_timeout: restarting\n");
4608 pp->last_dmacnt = dmacnt;
4609 pp->timeout_id = timeout(ecpp_ecp_read_timeout,
4610 (caddr_t)pp,
4611 drv_usectohz(pp->rev_watchdog * 1000));
4615 mutex_exit(&pp->umutex);
4623 ecpp_ecp_read_completion(struct ecppunit *pp)
4628 ASSERT(mutex_owned(&pp->umutex));
4629 ASSERT(pp->current_mode == ECPP_ECP_MODE &&
4630 pp->current_phase == ECPP_PHASE_ECP_REV_XFER);
4631 ASSERT(pp->msg != NULL);
4636 if (ECPP_DMA_STOP(pp, &unx_len) == FAILURE) {
4637 unx_len = pp->resid;
4638 ecpp_error(pp->dip, "ecp_read_completion: failed dma_stop\n");
4641 mp = pp->msg;
4642 xfer_len = pp->resid - unx_len; /* how much data was transferred */
4644 if (ddi_dma_unbind_handle(pp->dma_handle) != DDI_SUCCESS) {
4645 ecpp_error(pp->dip, "ecp_read_completion: unbind failed.\n");
4648 ecpp_error(pp->dip, "ecp_read_completion: xfered %d bytes of %d\n",
4649 xfer_len, pp->resid);
4652 pp->msg = NULL;
4653 pp->resid -= xfer_len;
4654 pp->ibytes[pp->current_mode] += xfer_len;
4655 pp->e_busy = ECPP_IDLE;
4656 pp->current_phase = ECPP_PHASE_ECP_REV_IDLE;
4662 if (canputnext(pp->readq)) {
4663 mutex_exit(&pp->umutex);
4664 putnext(pp->readq, mp);
4665 mutex_enter(&pp->umutex);
4667 ecpp_error(pp->dip, "ecp_read_completion: fail canputnext\n");
4668 if (!putq(pp->readq, mp)) {
4674 if (!(ECR_READ(pp) & ECPP_FIFO_EMPTY)) {
4675 (void) ecpp_backchan_req(pp);
4678 qenable(pp->writeq);
4685 nibble_peripheral2host(struct ecppunit *pp, uint8_t *byte)
4695 DCR_WRITE(pp, ECPP_nINIT | ECPP_AFX);
4700 if (wait_dsr(pp, ECPP_nACK, 0, 35000) < 0) {
4701 ecpp_error(pp->dip,
4703 i + 1, DSR_READ(pp));
4704 (void) ecpp_1284_termination(pp);
4708 n[i] = DSR_READ(pp); /* get a nibble */
4711 DCR_WRITE(pp, ECPP_nINIT);
4716 if (wait_dsr(pp, ECPP_nACK, ECPP_nACK, 35000) < 0) {
4717 ecpp_error(pp->dip,
4719 i + 1, DSR_READ(pp));
4720 (void) ecpp_1284_termination(pp);
4729 pp->ibytes[ECPP_NIBBLE_MODE]++;
4737 ecpp_peripheral2host(struct ecppunit *pp)
4739 if (!canputnext(pp->readq)) {
4740 ecpp_error(pp->dip, "ecpp_peripheral2host: readq full\n");
4744 switch (pp->backchannel) {
4750 ASSERT(pp->current_mode == ECPP_NIBBLE_MODE);
4755 DCR_WRITE(pp, ECPP_nINIT);
4758 if (wait_dsr(pp, ECPP_PE, 0, 35000) < 0) {
4759 ecpp_error(pp->dip,
4761 DSR_READ(pp));
4762 (void) ecpp_1284_termination(pp);
4766 pp->current_phase = ECPP_PHASE_NIBT_AVAIL;
4769 return (ecpp_idle_phase(pp));
4772 if ((pp->current_phase == ECPP_PHASE_ECP_FWD_IDLE) &&
4773 (ecp_forward2reverse(pp) == FAILURE)) {
4777 return (ecp_peripheral2host(pp)); /* start the transfer */
4783 if (ECR_READ(pp) & ECPP_FIFO_EMPTY) {
4784 ecpp_error(pp->dip, "ecpp_periph2host: fifo empty\n");
4790 ecpp_error(pp->dip,
4799 while (i-- && (!(ECR_READ(pp) & ECPP_FIFO_EMPTY))) {
4800 *mp->b_wptr++ = TFIFO_READ(pp);
4804 if (canputnext(pp->readq)) {
4805 mutex_exit(&pp->umutex);
4807 ecpp_error(pp->dip,
4810 putnext(pp->readq, mp);
4811 mutex_enter(&pp->umutex);
4814 ecpp_error(pp->dip,
4822 ecpp_error(pp->dip, "ecpp_peripheraltohost: illegal back");
4833 ecp_forward2reverse(struct ecppunit *pp)
4835 ASSERT(pp->current_mode == ECPP_ECP_MODE &&
4836 pp->current_phase == ECPP_PHASE_ECP_FWD_IDLE);
4839 ECR_WRITE(pp, ECR_mode_001 | ECPP_INTR_SRV | ECPP_INTR_MASK);
4842 DCR_WRITE(pp, ECPP_REV_DIR | ECPP_nINIT);
4845 ECR_WRITE(pp, ECR_mode_011 | ECPP_INTR_SRV | ECPP_INTR_MASK);
4850 DCR_WRITE(pp, ECPP_REV_DIR);
4854 pp->current_phase = ECPP_PHASE_ECP_REV_IDLE;
4856 ecpp_error(pp->dip, "ecp_forward2reverse ok\n");
4867 ecp_reverse2forward(struct ecppunit *pp)
4869 ASSERT(pp->current_mode == ECPP_ECP_MODE &&
4870 pp->current_phase == ECPP_PHASE_ECP_REV_IDLE);
4873 DCR_WRITE(pp, ECPP_REV_DIR | ECPP_nINIT);
4879 if (wait_dsr(pp, ECPP_PE, ECPP_PE, 35000) < 0) {
4880 ecpp_error(pp->dip,
4881 "ecp_reverse2forward: failed event 49 %x\n", DSR_READ(pp));
4882 (void) ecpp_1284_termination(pp);
4887 ECR_WRITE(pp, ECR_mode_001 | ECPP_INTR_SRV | ECPP_INTR_MASK);
4890 DCR_WRITE(pp, ECPP_nINIT);
4893 ECR_WRITE(pp, ECR_mode_011 | ECPP_INTR_SRV | ECPP_INTR_MASK);
4895 pp->current_phase = ECPP_PHASE_ECP_FWD_IDLE;
4897 ecpp_error(pp->dip, "ecp_reverse2forward ok\n");
4907 ecpp_default_negotiation(struct ecppunit *pp)
4909 if (!noecp && (ecpp_mode_negotiation(pp, ECPP_ECP_MODE) == SUCCESS)) {
4911 pp->io_mode = (pp->fast_compat == TRUE) ? ECPP_DMA : ECPP_PIO;
4913 } else if (ecpp_mode_negotiation(pp, ECPP_NIBBLE_MODE) == SUCCESS) {
4915 pp->io_mode = (pp->fast_compat == TRUE) ? ECPP_DMA : ECPP_PIO;
4918 pp->io_mode =
4919 (pp->fast_centronics == TRUE) ? ECPP_DMA : ECPP_PIO;
4921 ECPP_CONFIG_MODE(pp);
4928 ecpp_mode_negotiation(struct ecppunit *pp, uchar_t newmode)
4931 ASSERT(pp->current_mode == ECPP_CENTRONICS ||
4932 pp->current_mode == ECPP_COMPAT_MODE ||
4933 pp->current_mode == ECPP_NIBBLE_MODE ||
4934 pp->current_mode == ECPP_ECP_MODE ||
4935 pp->current_mode == ECPP_DIAG_MODE);
4937 if (pp->current_mode == newmode) {
4942 if ((pp->current_mode == ECPP_ECP_MODE) &&
4943 (pp->current_phase != ECPP_PHASE_ECP_FWD_IDLE)) {
4945 (void) ecp_reverse2forward(pp);
4950 (void) ecpp_1284_termination(pp);
4953 ECR_WRITE(pp, ECR_mode_001 | ECPP_INTR_MASK | ECPP_INTR_SRV);
4955 pp->current_mode = ECPP_CENTRONICS;
4956 pp->backchannel = ECPP_CENTRONICS;
4957 ECPP_CONFIG_MODE(pp);
4959 pp->to_mode[pp->current_mode]++;
4964 if (pp->current_mode == ECPP_NIBBLE_MODE) {
4965 if (ecpp_1284_termination(pp) == SUCCESS) {
4966 pp->current_mode = ECPP_COMPAT_MODE;
4967 pp->backchannel = ECPP_NIBBLE_MODE;
4968 ECPP_CONFIG_MODE(pp);
4969 pp->to_mode[pp->current_mode]++;
4976 if ((nibble_negotiation(pp) == SUCCESS) &&
4977 (ecpp_1284_termination(pp) == SUCCESS)) {
4978 pp->backchannel = ECPP_NIBBLE_MODE;
4979 pp->current_mode = ECPP_COMPAT_MODE;
4980 ECPP_CONFIG_MODE(pp);
4981 pp->to_mode[pp->current_mode]++;
4988 if (nibble_negotiation(pp) == FAILURE) {
4992 pp->backchannel = ECPP_NIBBLE_MODE;
4993 ECPP_CONFIG_MODE(pp);
4994 pp->to_mode[pp->current_mode]++;
4999 if (pp->noecpregs)
5001 if (ecp_negotiation(pp) == FAILURE) {
5008 DCR_WRITE(pp, ECPP_nINIT);
5010 if (ecr_write(pp, ECR_mode_011 |
5012 ecpp_error(pp->dip, "mode_nego:ECP: failed w/ecr\n");
5016 ECPP_CONFIG_MODE(pp);
5017 pp->to_mode[pp->current_mode]++;
5026 (void) ecpp_1284_termination(pp);
5029 if (ecr_write(pp, ECR_mode_001 |
5031 ecpp_error(pp->dip, "put to TFIFO: failed w/ecr\n");
5035 pp->current_mode = ECPP_DIAG_MODE;
5036 pp->backchannel = ECPP_DIAG_MODE;
5037 ECPP_CONFIG_MODE(pp);
5038 pp->to_mode[pp->current_mode]++;
5043 ecpp_error(pp->dip,
5056 ecpp_idle_phase(struct ecppunit *pp)
5063 if (!canputnext(pp->readq)) {
5064 ecpp_error(pp->dip, "ecpp_idle_phase: readq full\n");
5068 switch (pp->backchannel) {
5073 ecpp_error(pp->dip, "ecpp_idle_phase: compat idle\n");
5081 ecpp_error(pp->dip, "ecpp_idle_phase: nibble backchannel\n");
5082 if ((pp->current_mode != ECPP_NIBBLE_MODE) &&
5083 (ecpp_mode_negotiation(pp, ECPP_NIBBLE_MODE) == FAILURE)) {
5087 rval = read_nibble_backchan(pp);
5090 if (pp->current_phase == ECPP_PHASE_NIBT_NAVAIL &&
5091 canputnext(pp->readq)) {
5092 ecpp_error(pp->dip, "ecpp_idle_phase: going revidle\n");
5098 DCR_WRITE(pp, ECPP_nINIT | ECPP_AFX | ECPP_INTR_EN);
5100 ECPP_UNMASK_INTR(pp);
5110 ecpp_error(pp->dip, "ecpp_idle_phase: ECP forward\n");
5112 ASSERT(pp->current_phase == ECPP_PHASE_ECP_FWD_IDLE ||
5113 pp->current_phase == ECPP_PHASE_ECP_REV_IDLE);
5116 if ((pp->current_phase == ECPP_PHASE_ECP_REV_IDLE) &&
5117 (ecp_reverse2forward(pp) == FAILURE)) {
5125 if ((DSR_READ(pp) & ECPP_nERR) == 0) {
5126 (void) ecpp_backchan_req(pp);
5128 ECR_WRITE(pp,
5129 ECR_READ(pp) & ~ECPP_INTR_MASK | ECPP_INTR_SRV);
5131 ECPP_UNMASK_INTR(pp);
5137 ecpp_error(pp->dip, "ecpp_idle_phase: illegal backchannel");
5153 read_nibble_backchan(struct ecppunit *pp)
5159 ASSERT(pp->current_mode == ECPP_NIBBLE_MODE);
5161 pp->current_phase = (DSR_READ(pp) & (ECPP_nERR | ECPP_PE))
5164 ecpp_error(pp->dip, "read_nibble_backchan: %x\n", DSR_READ(pp));
5170 while (pp->current_phase == ECPP_PHASE_NIBT_AVAIL && rval == SUCCESS) {
5172 if (!canputnext(pp->readq)) {
5173 ecpp_error(pp->dip,
5179 ecpp_error(pp->dip,
5186 while (i-- && !(DSR_READ(pp) & ECPP_nERR)) {
5187 if (nibble_peripheral2host(pp, mp->b_wptr) != SUCCESS) {
5194 pp->current_phase = (DSR_READ(pp) & (ECPP_nERR | ECPP_PE))
5199 ecpp_error(pp->dip,
5202 pp->nread = 0;
5203 mutex_exit(&pp->umutex);
5204 putnext(pp->readq, mp);
5205 mutex_enter(&pp->umutex);
5218 devidnib_negotiation(struct ecppunit *pp)
5222 if (ecpp_1284_negotiation(pp,
5232 pp->current_phase = ECPP_PHASE_NIBT_AVAIL;
5234 pp->current_phase = ECPP_PHASE_NIBT_NAVAIL;
5237 ecpp_error(pp->dip, "ecpp_devidnib_nego: current_phase=%x\n",
5238 pp->current_phase);
5241 pp->current_mode = ECPP_NIBBLE_MODE;
5242 pp->backchannel = ECPP_NIBBLE_MODE;
5244 ecpp_error(pp->dip, "ecpp_devidnib_nego: ok\n");
5253 * 1) ecpp_getdevid(pp, NULL, &len) - to retrieve ID length;
5254 * 2) ecpp_getdevid(pp, buffer, &len) - to read len bytes into buffer
5261 ecpp_getdevid(struct ecppunit *pp, uint8_t *id, int *lenp, int mode)
5270 if ((pp->current_mode != mode) || (id == NULL)) {
5271 if (devidnib_negotiation(pp) == FAILURE) {
5276 if (pp->current_phase != ECPP_PHASE_NIBT_AVAIL) {
5286 dsr = DSR_READ(pp);
5295 (nibble_peripheral2host(pp, &lenhi) == FAILURE) ||
5297 (nibble_peripheral2host(pp, &lenlo) == FAILURE)) {
5298 ecpp_error(pp->dip,
5305 ecpp_error(pp->dip,
5317 if (nibble_peripheral2host(pp, id++) == FAILURE)
5321 dsr = DSR_READ(pp);
5323 ecpp_error(pp->dip,
5330 (void) ecpp_1284_termination(pp);
5351 empty_config_mode(struct ecppunit *pp)
5357 empty_mask_intr(struct ecppunit *pp)
5363 x86_getcnt(struct ecppunit *pp)
5367 (void) ddi_dmae_getcnt(pp->dip, pp->uh.x86.chn, &count);
5381 pc87332_map_regs(struct ecppunit *pp)
5383 if (ddi_regs_map_setup(pp->dip, 1, (caddr_t *)&pp->uh.ebus.c_reg, 0,
5385 &pp->uh.ebus.c_handle) != DDI_SUCCESS) {
5386 ecpp_error(pp->dip, "pc87332_map_regs: failed c_reg\n");
5390 if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->i_reg, 0,
5391 sizeof (struct info_reg), &acc_attr, &pp->i_handle)
5393 ecpp_error(pp->dip, "pc87332_map_regs: failed i_reg\n");
5397 if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->f_reg, 0x400,
5398 sizeof (struct fifo_reg), &acc_attr, &pp->f_handle)
5400 ecpp_error(pp->dip, "pc87332_map_regs: failed f_reg\n");
5404 if (ddi_regs_map_setup(pp->dip, 2, (caddr_t *)&pp->uh.ebus.dmac, 0,
5406 &pp->uh.ebus.d_handle) != DDI_SUCCESS) {
5407 ecpp_error(pp->dip, "pc87332_map_regs: failed dmac\n");
5414 pc87332_unmap_regs(pp);
5419 pc87332_unmap_regs(struct ecppunit *pp)
5421 if (pp->uh.ebus.c_handle) {
5422 ddi_regs_map_free(&pp->uh.ebus.c_handle);
5424 if (pp->uh.ebus.d_handle) {
5425 ddi_regs_map_free(&pp->uh.ebus.d_handle);
5427 if (pp->i_handle) {
5428 ddi_regs_map_free(&pp->i_handle);
5430 if (pp->f_handle) {
5431 ddi_regs_map_free(&pp->f_handle);
5436 pc87332_read_config_reg(struct ecppunit *pp, uint8_t reg_num)
5440 PP_PUTB(pp->uh.ebus.c_handle, &pp->uh.ebus.c_reg->index, reg_num);
5441 retval = PP_GETB(pp->uh.ebus.c_handle, &pp->uh.ebus.c_reg->data);
5447 pc87332_write_config_reg(struct ecppunit *pp, uint8_t reg_num, uint8_t val)
5449 PP_PUTB(pp->uh.ebus.c_handle, &pp->uh.ebus.c_reg->index, reg_num);
5450 PP_PUTB(pp->uh.ebus.c_handle, &pp->uh.ebus.c_reg->data, val);
5458 PP_PUTB(pp->uh.ebus.c_handle, &pp->uh.ebus.c_reg->data, val);
5462 pc87332_config_chip(struct ecppunit *pp)
5466 pp->current_phase = ECPP_PHASE_INIT;
5469 pmc = pc87332_read_config_reg(pp, PMC);
5471 pc87332_write_config_reg(pp, PMC,
5479 fcr = pc87332_read_config_reg(pp, FCR);
5481 pc87332_write_config_reg(pp, FCR,
5491 if (dcr_write(pp, ECPP_DCR_SET | ECPP_nINIT) == FAILURE) {
5492 ecpp_error(pp->dip, "ecpp_config_87332: DCR config\n");
5496 pc87332_write_config_reg(pp, PCR,
5500 if (ecr_write(pp, ECR_mode_001 |
5502 ecpp_error(pp->dip, "ecpp_config_87332: ECR\n");
5505 if (dcr_write(pp, ECPP_DCR_SET | ECPP_SLCTIN | ECPP_nINIT) == FAILURE) {
5506 ecpp_error(pp->dip, "ecpp_config_87332: w/DCR failed2.\n");
5511 pp->current_mode = ECPP_CENTRONICS;
5514 pp->current_phase = ECPP_PHASE_C_IDLE;
5524 pc87332_config_mode(struct ecppunit *pp)
5526 if (COMPAT_PIO(pp)) {
5527 pc87332_write_config_reg(pp, PCR, 0x04);
5529 pc87332_write_config_reg(pp, PCR, 0x14);
5534 pc97317_map_regs(struct ecppunit *pp)
5536 if (pc87332_map_regs(pp) != SUCCESS) {
5540 if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->uh.ebus.c2_reg,
5542 &pp->uh.ebus.c2_handle) != DDI_SUCCESS) {
5543 ecpp_error(pp->dip, "pc97317_map_regs: failed c2_reg\n");
5544 pc87332_unmap_regs(pp);
5552 pc97317_unmap_regs(struct ecppunit *pp)
5554 if (pp->uh.ebus.c2_handle) {
5555 ddi_regs_map_free(&pp->uh.ebus.c2_handle);
5558 pc87332_unmap_regs(pp);
5568 pc97317_config_chip(struct ecppunit *pp)
5573 pc87332_write_config_reg(pp, PC97317_CONFIG_DEV_NO, 0x4);
5576 PP_PUTB(pp->uh.ebus.c2_handle,
5577 &pp->uh.ebus.c2_reg->eir, PC97317_CONFIG2_CONTROL2);
5578 PP_PUTB(pp->uh.ebus.c2_handle, &pp->uh.ebus.c2_reg->edr, 0x80);
5581 pc87332_write_config_reg(pp, PC97317_CONFIG_INTR_TYPE, 0x00);
5584 pc87332_write_config_reg(pp, PC97317_CONFIG_PP_CONFIG, 0xf2);
5586 if (dcr_write(pp, ECPP_SLCTIN | ECPP_nINIT) == FAILURE) {
5587 ecpp_error(pp->dip, "pc97317_config_chip: failed w/DCR\n");
5590 if (ecr_write(pp, ECR_mode_001 |
5592 ecpp_error(pp->dip, "pc97317_config_chip: failed w/ECR\n");
5596 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_DEV_NO);
5597 ecpp_error(pp->dip, "97317:conreg7(logical dev)=%x\n", conreg);
5599 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_BASE_ADDR_MSB);
5600 ecpp_error(pp->dip, "97317:conreg60(addrHi)=%x\n", conreg);
5602 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_BASE_ADDR_LSB);
5603 ecpp_error(pp->dip, "97317:conreg61(addrLo)=%x\n", conreg);
5605 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_INTR_SEL);
5606 ecpp_error(pp->dip, "97317:conreg70(IRQL)=%x\n", conreg);
5608 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_INTR_TYPE);
5609 ecpp_error(pp->dip, "97317:conreg71(intr type)=%x\n", conreg);
5611 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_ACTIVATE);
5612 ecpp_error(pp->dip, "97317:conreg30(Active)=%x\n", conreg);
5614 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_IO_RANGE);
5615 ecpp_error(pp->dip, "97317:conreg31(IO Range Check)=%x\n", conreg);
5617 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_DMA0_CHAN);
5618 ecpp_error(pp->dip, "97317:conreg74(DMA0 Chan)=%x\n", conreg);
5619 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_DMA1_CHAN);
5620 ecpp_error(pp->dip, "97317:conreg75(DMA1 Chan)=%x\n", conreg);
5622 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_PP_CONFIG);
5623 ecpp_error(pp->dip, "97317:conregFO(pport conf)=%x\n", conreg);
5625 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_PP_CONFIG);
5626 ecpp_error(pp->dip, "97317:conregFO(pport conf)=%x\n", conreg);
5637 pc97317_config_mode(struct ecppunit *pp)
5640 pc87332_write_config_reg(pp, PC97317_CONFIG_DEV_NO, 0x4);
5642 if (COMPAT_PIO(pp) || pp->current_mode == ECPP_NIBBLE_MODE) {
5643 pc87332_write_config_reg(pp, PC97317_CONFIG_INTR_TYPE, 0x02);
5645 pc87332_write_config_reg(pp, PC97317_CONFIG_INTR_TYPE, 0x00);
5650 cheerio_mask_intr(struct ecppunit *pp)
5653 AND_SET_LONG_R(pp->uh.ebus.d_handle,
5654 &pp->uh.ebus.dmac->csr, ~DCSR_INT_EN);
5658 cheerio_unmask_intr(struct ecppunit *pp)
5661 OR_SET_LONG_R(pp->uh.ebus.d_handle,
5662 &pp->uh.ebus.dmac->csr, DCSR_INT_EN | DCSR_TCI_DIS);
5666 cheerio_dma_start(struct ecppunit *pp)
5668 cheerio_reset_dcsr(pp);
5669 SET_DMAC_BCR(pp, pp->dma_cookie.dmac_size);
5670 SET_DMAC_ACR(pp, pp->dma_cookie.dmac_address);
5672 if (pp->dma_dir == DDI_DMA_READ) {
5673 SET_DMAC_CSR(pp, DCSR_INT_EN | DCSR_EN_CNT | DCSR_EN_DMA |
5676 SET_DMAC_CSR(pp, DCSR_INT_EN | DCSR_EN_CNT | DCSR_EN_DMA |
5687 cheerio_dma_stop(struct ecppunit *pp, size_t *countp)
5692 AND_SET_LONG_R(pp->uh.ebus.d_handle, &pp->uh.ebus.dmac->csr,
5696 OR_SET_LONG_R(pp->uh.ebus.d_handle, &pp->uh.ebus.dmac->csr,
5701 *countp = cheerio_getcnt(pp);
5704 cheerio_reset_dcsr(pp);
5705 SET_DMAC_BCR(pp, 0);
5708 ecr = ECR_READ(pp);
5709 if (ecr_write(pp, ecr & ~ECPP_DMA_ENABLE) == FAILURE) {
5714 ecr = ECR_READ(pp);
5716 return (ecr_write(pp, ecr | ECPP_INTR_SRV));
5720 cheerio_getcnt(struct ecppunit *pp)
5722 return (GET_DMAC_BCR(pp));
5731 cheerio_reset_dcsr(struct ecppunit *pp)
5735 SET_DMAC_CSR(pp, DCSR_RESET);
5737 while (GET_DMAC_CSR(pp) & DCSR_CYC_PEND) {
5739 ecpp_error(pp->dip, "cheerio_reset_dcsr: timeout\n");
5747 SET_DMAC_CSR(pp, 0);
5760 m1553_map_regs(struct ecppunit *pp)
5762 if (ddi_regs_map_setup(pp->dip, 1, (caddr_t *)&pp->uh.m1553.isa_space,
5764 &pp->uh.m1553.d_handle) != DDI_SUCCESS) {
5765 ecpp_error(pp->dip, "m1553_map_regs: failed isa space\n");
5769 if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->i_reg, 0,
5770 sizeof (struct info_reg), &acc_attr, &pp->i_handle)
5772 ecpp_error(pp->dip, "m1553_map_regs: failed i_reg\n");
5776 if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->f_reg, 0x400,
5777 sizeof (struct fifo_reg), &acc_attr, &pp->f_handle)
5779 ecpp_error(pp->dip, "m1553_map_regs: failed f_reg\n");
5786 m1553_unmap_regs(pp);
5791 m1553_unmap_regs(struct ecppunit *pp)
5793 if (pp->uh.m1553.d_handle) {
5794 ddi_regs_map_free(&pp->uh.m1553.d_handle);
5796 if (pp->i_handle) {
5797 ddi_regs_map_free(&pp->i_handle);
5799 if (pp->f_handle) {
5800 ddi_regs_map_free(&pp->f_handle);
5806 x86_map_regs(struct ecppunit *pp)
5810 if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->i_reg, 0,
5811 sizeof (struct info_reg), &acc_attr, &pp->i_handle)
5813 ecpp_error(pp->dip, "x86_map_regs: failed i_reg\n");
5816 if (ddi_dev_nregs(pp->dip, &nregs) == DDI_SUCCESS && nregs == 2) {
5817 if (ddi_regs_map_setup(pp->dip, 1, (caddr_t *)&pp->f_reg, 0,
5818 sizeof (struct fifo_reg), &acc_attr, &pp->f_handle)
5820 ecpp_error(pp->dip, "x86_map_regs: failed f_reg\n");
5823 pp->noecpregs = FALSE;
5825 pp->noecpregs = TRUE;
5829 x86_unmap_regs(pp);
5834 x86_unmap_regs(struct ecppunit *pp)
5836 if (pp->i_handle) {
5837 ddi_regs_map_free(&pp->i_handle);
5839 if (pp->f_handle) {
5840 ddi_regs_map_free(&pp->f_handle);
5846 m1553_read_config_reg(struct ecppunit *pp, uint8_t reg_num)
5850 dma8237_write(pp, 0x3F0, reg_num);
5851 retval = dma8237_read(pp, 0x3F1);
5857 m1553_write_config_reg(struct ecppunit *pp, uint8_t reg_num, uint8_t val)
5859 dma8237_write(pp, 0x3F0, reg_num);
5860 dma8237_write(pp, 0x3F1, val);
5864 m1553_config_chip(struct ecppunit *pp)
5869 dma8237_write(pp, 0x3F0, 0x51);
5870 dma8237_write(pp, 0x3F0, 0x23);
5872 m1553_write_config_reg(pp, PnP_CONFIG_DEV_NO, 0x3);
5873 conreg = m1553_read_config_reg(pp, PnP_CONFIG_DEV_NO);
5874 ecpp_error(pp->dip, "M1553:conreg7(logical dev)=%x\n", conreg);
5876 conreg = m1553_read_config_reg(pp, PnP_CONFIG_ACTIVATE);
5877 ecpp_error(pp->dip, "M1553:conreg30(Active)=%x\n", conreg);
5879 conreg = m1553_read_config_reg(pp, PnP_CONFIG_BASE_ADDR_MSB);
5880 ecpp_error(pp->dip, "M1553:conreg60(addrHi)=%x\n", conreg);
5881 conreg = m1553_read_config_reg(pp, PnP_CONFIG_BASE_ADDR_LSB);
5882 ecpp_error(pp->dip, "M1553:conreg61(addrLo)=%x\n", conreg);
5884 conreg = m1553_read_config_reg(pp, PnP_CONFIG_INTR_SEL);
5885 ecpp_error(pp->dip, "M1553:conreg70(IRQL)=%x\n", conreg);
5887 conreg = m1553_read_config_reg(pp, PnP_CONFIG_DMA0_CHAN);
5888 ecpp_error(pp->dip, "M1553:conreg74(DMA0 Chan)=%x\n", conreg);
5891 conreg = m1553_read_config_reg(pp, PnP_CONFIG_PP_CONFIG0);
5893 m1553_write_config_reg(pp, PnP_CONFIG_PP_CONFIG0, conreg);
5894 conreg = m1553_read_config_reg(pp, PnP_CONFIG_PP_CONFIG0);
5895 ecpp_error(pp->dip, "M1553:conregFO(pport conf)=%x\n", conreg);
5897 m1553_write_config_reg(pp, PnP_CONFIG_PP_CONFIG1, 0x04);
5898 conreg = m1553_read_config_reg(pp, PnP_CONFIG_PP_CONFIG1);
5899 ecpp_error(pp->dip, "M1553:conregF1(outconf)=%x\n", conreg);
5902 dma8237_write(pp, 0x3F0, 0xBB);
5905 ECR_WRITE(pp, ECR_mode_001 | ECPP_INTR_MASK | ECPP_INTR_SRV);
5906 DCR_WRITE(pp, ECPP_SLCTIN | ECPP_nINIT);
5908 ecpp_error(pp->dip, "m1553_config_chip: ecr=%x, dsr=%x, dcr=%x\n",
5909 ECR_READ(pp), DSR_READ(pp), DCR_READ(pp));
5916 x86_config_chip(struct ecppunit *pp)
5918 if (ecr_write(pp, ECR_mode_001 |
5920 ecpp_error(pp->dip, "config chip: failed w/ecr\n");
5921 pp->noecpregs = TRUE;
5923 if (pp->noecpregs)
5924 pp->fast_compat = FALSE;
5925 DCR_WRITE(pp, ECPP_SLCTIN | ECPP_nINIT);
5926 ecpp_error(pp->dip, "x86_config_chip: ecr=%x, dsr=%x, dcr=%x\n",
5927 ECR_READ(pp), DSR_READ(pp), DCR_READ(pp));
5934 * of DMAC1 with the dma cookie. pp->dma_cookie must
5938 dma8237_dma_start(struct ecppunit *pp)
5942 chn = pp->uh.m1553.chn;
5945 pp->dma_cookie.dmac_size != 0 &&
5946 pp->dma_cookie.dmac_address != NULL);
5951 dma8237_write(pp, DMAC2_MODE, DMAMODE_CASC);
5952 if (pp->dma_dir == DDI_DMA_READ) {
5953 dma8237_write(pp, DMAC1_MODE, DMAMODE_SINGLE |
5956 dma8237_write(pp, DMAC1_MODE, DMAMODE_SINGLE |
5960 dma8237_write_addr(pp, pp->dma_cookie.dmac_address);
5961 dma8237_write_count(pp, pp->dma_cookie.dmac_size - 1);
5978 dma8237_write(pp, DMAC1_ALLMASK, ~(1 << chn));
5979 pp->uh.m1553.isadma_entered = 1;
5985 dma8237_dma_stop(struct ecppunit *pp, size_t *countp)
5990 ecr = (ECR_READ(pp) & 0xe0) | ECPP_INTR_MASK | ECPP_INTR_SRV;
5991 (void) ecr_write(pp, ecr);
5993 if (pp->uh.m1553.isadma_entered) {
5995 dma8237_write(pp, DMAC1_ALLMASK, 0);
5996 pp->uh.m1553.isadma_entered = 0;
6002 *countp = dma8237_getcnt(pp);
6003 if (pp->dma_dir == DDI_DMA_READ && *countp > 0) {
6011 x86_dma_start(struct ecppunit *pp)
6016 chn = pp->uh.x86.chn;
6018 pp->dma_cookie.dmac_size != 0 &&
6019 pp->dma_cookie.dmac_address != NULL);
6022 (pp->dma_dir & DDI_DMA_READ) ? DMAE_CMD_READ : DMAE_CMD_WRITE;
6023 if (ddi_dmae_prog(pp->dip, &dmaereq, &pp->dma_cookie, chn)
6025 ecpp_error(pp->dip, "prog failed !!!\n");
6026 ecpp_error(pp->dip, "dma_started..\n");
6031 x86_dma_stop(struct ecppunit *pp, size_t *countp)
6036 if (pp->uh.x86.chn == 0xff)
6038 ecr = (ECR_READ(pp) & 0xe0) | ECPP_INTR_MASK | ECPP_INTR_SRV;
6039 (void) ecr_write(pp, ecr);
6040 ecpp_error(pp->dip, "dma_stop\n");
6044 *countp = x86_getcnt(pp);
6046 ecpp_error(pp->dip, "dma_stoped..\n");
6053 dma8237_write_addr(struct ecppunit *pp, uint32_t addr)
6058 switch (pp->uh.m1553.chn) {
6087 p = (uint16_t *)&pp->uh.m1553.isa_space->isa_reg[c_addr];
6088 ddi_put16(pp->uh.m1553.d_handle, p, addr & 0xFFFF);
6090 dma8237_write(pp, c_lpage, (addr & 0xFF0000) >> 16);
6091 dma8237_write(pp, c_hpage, (addr & 0xFF000000) >> 24);
6101 dma8237_read_addr(struct ecppunit *pp)
6109 switch (pp->uh.m1553.chn) {
6138 p = (uint16_t *)&pp->uh.m1553.isa_space->isa_reg[c_addr];
6139 rval16 = ddi_get16(pp->uh.m1553.d_handle, p);
6141 rval3 = dma8237_read(pp, c_lpage);
6142 rval4 = dma8237_read(pp, c_hpage);
6151 dma8237_write_count(struct ecppunit *pp, uint32_t count)
6156 switch (pp->uh.m1553.chn) {
6177 p = (uint16_t *)&pp->uh.m1553.isa_space->isa_reg[c_wcnt];
6178 ddi_put16(pp->uh.m1553.d_handle, p, count & 0xFFFF);
6183 dma8237_read_count(struct ecppunit *pp)
6188 switch (pp->uh.m1553.chn) {
6209 p = (uint16_t *)&pp->uh.m1553.isa_space->isa_reg[c_wcnt];
6210 return (ddi_get16(pp->uh.m1553.d_handle, p));
6215 dma8237_write(struct ecppunit *pp, int reg_num, uint8_t val)
6217 ddi_put8(pp->uh.m1553.d_handle,
6218 &pp->uh.m1553.isa_space->isa_reg[reg_num], val);
6222 dma8237_read(struct ecppunit *pp, int reg_num)
6224 return (ddi_get8(pp->uh.m1553.d_handle,
6225 &pp->uh.m1553.isa_space->isa_reg[reg_num]));
6229 dma8237_getcnt(struct ecppunit *pp)
6233 if ((cnt = dma8237_read_count(pp)) == 0xffff)
6247 ecpp_kstat_init(struct ecppunit *pp)
6255 (void) sprintf(buf, "ecppc%d", pp->instance);
6256 pp->intrstats = kstat_create("ecpp", pp->instance, buf, "controller",
6258 if (pp->intrstats == NULL) {
6259 ecpp_error(pp->dip, "ecpp_kstat_init:1: kstat_create failed");
6261 pp->intrstats->ks_update = ecpp_kstatintr_update;
6262 pp->intrstats->ks_private = (void *) pp;
6263 kstat_install(pp->intrstats);
6269 pp->ksp = kstat_create("ecpp", pp->instance, NULL, "misc",
6273 if (pp->ksp == NULL) {
6274 ecpp_error(pp->dip, "ecpp_kstat_init:2: kstat_create failed");
6278 ekp = (struct ecppkstat *)pp->ksp->ks_data;
6306 pp->ksp->ks_update = ecpp_kstat_update;
6307 pp->ksp->ks_private = (void *) pp;
6308 kstat_install(pp->ksp);
6314 struct ecppunit *pp;
6325 pp = (struct ecppunit *)ksp->ks_private;
6328 mutex_enter(&pp->umutex);
6330 ekp->ek_ctx_obytes.value.ui32 = pp->obytes[ECPP_CENTRONICS] +
6331 pp->obytes[ECPP_COMPAT_MODE];
6332 ekp->ek_ctxpio_obytes.value.ui32 = pp->ctxpio_obytes;
6333 ekp->ek_nib_ibytes.value.ui32 = pp->ibytes[ECPP_NIBBLE_MODE];
6334 ekp->ek_ecp_obytes.value.ui32 = pp->obytes[ECPP_ECP_MODE];
6335 ekp->ek_ecp_ibytes.value.ui32 = pp->ibytes[ECPP_ECP_MODE];
6336 ekp->ek_epp_obytes.value.ui32 = pp->obytes[ECPP_EPP_MODE];
6337 ekp->ek_epp_ibytes.value.ui32 = pp->ibytes[ECPP_EPP_MODE];
6338 ekp->ek_diag_obytes.value.ui32 = pp->obytes[ECPP_DIAG_MODE];
6339 ekp->ek_to_ctx.value.ui32 = pp->to_mode[ECPP_CENTRONICS] +
6340 pp->to_mode[ECPP_COMPAT_MODE];
6341 ekp->ek_to_nib.value.ui32 = pp->to_mode[ECPP_NIBBLE_MODE];
6342 ekp->ek_to_ecp.value.ui32 = pp->to_mode[ECPP_ECP_MODE];
6343 ekp->ek_to_epp.value.ui32 = pp->to_mode[ECPP_EPP_MODE];
6344 ekp->ek_to_diag.value.ui32 = pp->to_mode[ECPP_DIAG_MODE];
6345 ekp->ek_xfer_tout.value.ui32 = pp->xfer_tout;
6346 ekp->ek_ctx_cf.value.ui32 = pp->ctx_cf;
6347 ekp->ek_joblen.value.ui32 = pp->joblen;
6348 ekp->ek_isr_reattempt_high.value.ui32 = pp->isr_reattempt_high;
6349 ekp->ek_mode.value.ui32 = pp->current_mode;
6350 ekp->ek_phase.value.ui32 = pp->current_phase;
6351 ekp->ek_backchan.value.ui32 = pp->backchannel;
6352 ekp->ek_iomode.value.ui32 = pp->io_mode;
6353 ekp->ek_state.value.ui32 = pp->e_busy;
6355 mutex_exit(&pp->umutex);
6363 struct ecppunit *pp;
6373 pp = (struct ecppunit *)ksp->ks_private;
6375 mutex_enter(&pp->umutex);
6377 KSTAT_INTR_PTR(ksp)->intrs[KSTAT_INTR_HARD] = pp->intr_hard;
6378 KSTAT_INTR_PTR(ksp)->intrs[KSTAT_INTR_SPURIOUS] = pp->intr_spurious;
6379 KSTAT_INTR_PTR(ksp)->intrs[KSTAT_INTR_SOFT] = pp->intr_soft;
6381 mutex_exit(&pp->umutex);