Lines Matching defs:dsr

1121 	    "ecpp_open: mode=%x, phase=%x ecr=%x, dsr=%x, dcr=%x\n",
1220 	ecpp_error(pp->dip, "ecpp_close: ecr=%x, dsr=%x, dcr=%x\n",
1559 		rg.dsr = DSR_READ(pp);
1564 		ecpp_error(pp->dip, "ECPPIOC_GETREGS: dsr=%x,dcr=%x\n",
1565 		    rg.dsr, rg.dcr);
1568 		rg.dsr |= ECPP_SETREGS_DSR_MASK;
1734 		uint8_t	dsr;
1742 			dsr = DSR_READ(pp);
1743 			if ((dsr & ECPP_PE) ||
1744 			    !(dsr & ECPP_SLCT) || !(dsr & ECPP_nERR)) {
1760 		uint8_t	dsr;
1773 		dsr = DSR_READ(pp);		/* read status */
1777 		ecpp_error(pp->dip, "PRNIOC_GET_STATUS: %x\n", dsr);
1779 		status = (dsr & (ECPP_SLCT | ECPP_PE | ECPP_nERR)) |
1780 		    (~dsr & ECPP_nBUSY);
3050 	uint8_t		dsr;
3113 	dsr = DSR_READ(pp);
3137 		if (((dsr & ECPP_IRQ_ST) == 0) ||
3139 		    (((dsr & ECPP_nERR) == 0) &&
3188 	if ((dsr & ECPP_nERR) == 0) {
3227 	    "isr:unknown: dcsr=%x ecr=%x dsr=%x dcr=%x\nmode=%x phase=%x\n",
3228 	    dcsr, ECR_READ(pp), dsr, DCR_READ(pp),
3239 	    "isr:UNCL: dcsr=%x ecr=%x dsr=%x dcr=%x\nmode=%x phase=%x\n",
3287 	ecpp_error(pp->dip, "ecpp_dma_ihdlr(%x): ecr=%x, dsr=%x, dcr=%x\n",
3498 			    "dsr=%x jl=%d cf_isr=%d\n",
3976 	uint8_t	dsr;
3985 	dsr = DSR_READ(pp);
3986 	if ((dsr & ECPP_PE) || ((dsr & statmask) != statmask)) {
4156 	uint8_t dsr;
4160 	if (ecpp_1284_negotiation(pp, ECPP_XREQ_ECP, &dsr) == FAILURE)
4164 	if ((dsr & (ECPP_PE | ECPP_nBUSY | ECPP_SLCT)) !=
4204 	uint8_t	dsr;
4206 	if (ecpp_1284_negotiation(pp, ECPP_XREQ_NIBBLE, &dsr) == FAILURE) {
4214 	if ((dsr & (ECPP_PE | ECPP_nERR)) == 0) {
5220 	uint8_t dsr;
5223 	    ECPP_XREQ_NIBBLE | ECPP_XREQ_ID, &dsr) == FAILURE) {
5231 	if ((dsr & (ECPP_PE | ECPP_nERR)) == 0) {
5264 	uint8_t dsr;
5286 		dsr = DSR_READ(pp);
5294 			if ((dsr & ECPP_nERR) ||
5296 			    (dsr & ECPP_nERR) ||
5316 			while (i && ((dsr & ECPP_nERR) == 0)) {
5321 				dsr = DSR_READ(pp);
5908 	ecpp_error(pp->dip, "m1553_config_chip: ecr=%x, dsr=%x, dcr=%x\n",
5926 	ecpp_error(pp->dip, "x86_config_chip: ecr=%x, dsr=%x, dcr=%x\n",