Lines Matching defs:sa
79 static void link_start(ch_t *sa, struct pe_port_t *pp);
80 static ch_esb_t *ch_alloc_small_esbbuf(ch_t *sa, uint32_t i);
81 static ch_esb_t *ch_alloc_big_esbbuf(ch_t *sa, uint32_t i);
84 static const struct board_info *pe_sa_init(ch_t *sa);
87 static void pe_free_driver_resources(ch_t *sa);
107 static int pe_small_rbuf_pool_init(ch_t *sa);
108 static int pe_big_rbuf_pool_init(ch_t *sa);
130 pe_intr(ch_t *sa)
132 mutex_enter(&sa->ch_intr);
134 if (sge_data_in(sa->sge)) {
135 sa->isr_intr++;
136 mutex_exit(&sa->ch_intr);
140 mutex_exit(&sa->ch_intr);
152 ch_t *sa = NULL;
155 sa = (ch_t *)xsa;
163 if (sa->init_counter == 0) {
164 for_each_port(sa, i) {
169 if (sa->port[i].line_up == 0) {
170 link_start(sa, &sa->port[i]);
171 sa->port[i].line_up = 1;
175 (void) t1_init_hw_modules(sa);
180 if (sa->ch_config.cksum_enabled) {
181 if (sa->config_data.offload_ip_cksum) {
183 t1_tp_set_ip_checksum_offload(sa->tp, 1);
186 if (sa->config_data.offload_tcp_cksum) {
188 t1_tp_set_tcp_checksum_offload(sa->tp, 1);
191 if (sa->config_data.offload_udp_cksum) {
193 t1_tp_set_udp_checksum_offload(sa->tp, 1);
197 sa->ch_flags |= PEINITDONE;
199 sa->init_counter++;
206 (void) sge_start(sa->sge);
207 t1_interrupts_enable(sa);
212 (void) pe_change_mtu(sa);
217 (void) t1_tpi_read(sa, SUNI1x10GEXP_REG_TXXG_CONFIG_1 << 2,
218 &sa->txxg_cfg1);
224 link_start(ch_t *sa, struct pe_port_t *p)
239 pe_stop(ch_t *sa)
241 t1_interrupts_disable(sa);
242 (void) sge_stop(sa->sge);
248 mutex_enter(&sa->ch_intr);
249 mutex_exit(&sa->ch_intr);
257 pe_start(ch_t *sa, mblk_t *mp, uint32_t flg)
287 if (sge_data_out(sa->sge, 0, mp, hmp, 1, flg) == 0) {
295 sa->ch_blked = 1;
305 if (sa->ch_ip == NULL) {
308 if (is_T2(sa)) {
313 if (pe_make_fake_arp(sa, mp->b_rptr)) {
315 sa->oerr++;
319 sa->ch_ip = pe_get_ip(mp->b_rptr);
336 sa->sge->intr_cnt.tx_need_cpl_space++;
341 sa->oerr++;
365 sa->sge->intr_cnt.tx_multi_mblks++;
413 if (sa->ch_config.enable_dvma) {
414 lseg = ch_bind_dvma_handle(sa, len,
418 sa->sge->intr_cnt.tx_no_dvma1++;
419 if ((lseg = ch_bind_dma_handle(sa, len,
423 sa->sge->intr_cnt.tx_no_dma1++;
444 lseg = ch_bind_dma_handle(sa, len,
448 sa->sge->intr_cnt.tx_no_dma1++;
467 lseg = ch_bind_dma_handle(sa, len,
471 sa->sge->intr_cnt.tx_no_dma1++;
511 if (sa->ch_config.enable_dvma) {
512 nseg = ch_bind_dvma_handle(sa, len,
516 sa->sge->intr_cnt.tx_no_dvma2++;
517 nseg = ch_bind_dma_handle(sa, len,
521 sa->sge->intr_cnt.tx_no_dma2++;
531 nseg = ch_bind_dma_handle(sa, len,
534 sa->sge->intr_cnt.tx_no_dma2++;
544 nseg = ch_bind_dma_handle(sa, len,
547 sa->sge->intr_cnt.tx_no_dma2++;
564 if (sge_data_out(sa->sge, 0, m0, hmp, nseg, flg) == 0) {
575 sa->ch_blked = 1;
586 ch_unbind_dma_handle(sa, cmp->ce_dh);
589 ch_unbind_dvma_handle(sa, cmp->ce_dh);
618 sa->oerr++;
626 pe_set_mac(ch_t *sa, unsigned char *ac_enaddr)
628 sa->port[0].mac->ops->macaddress_set(sa->port[0].mac, ac_enaddr);
633 pe_get_mac(ch_t *sa)
635 return (sa->port[0].enaddr);
640 pe_set_promiscuous(ch_t *sa, int flag)
642 struct cmac *mac = sa->port[0].mac;
647 sa->ch_flags &= ~(PEPROMISC|PEALLMULTI);
651 sa->ch_flags |= PEPROMISC;
655 sa->ch_flags |= PEALLMULTI;
659 mutex_enter(&sa->ch_mc_lck);
660 rm.chp = sa;
661 rm.mc = sa->ch_mc;
664 mutex_exit(&sa->ch_mc_lck);
668 pe_set_mc(ch_t *sa, uint8_t *ep, int flg)
670 struct cmac *mac = sa->port[0].mac;
683 mutex_enter(&sa->ch_mc_lck);
684 mcp->cmc_next = sa->ch_mc;
685 sa->ch_mc = mcp;
686 sa->ch_mc_cnt++;
687 mutex_exit(&sa->ch_mc_lck);
690 ch_mc_t **p = &sa->ch_mc;
693 mutex_enter(&sa->ch_mc_lck);
694 p = &sa->ch_mc;
700 sa->ch_mc_cnt--;
706 mutex_exit(&sa->ch_mc_lck);
713 mutex_enter(&sa->ch_mc_lck);
714 rm.chp = sa;
715 rm.mc = sa->ch_mc;
718 mutex_exit(&sa->ch_mc_lck);
749 pe_get_stats(ch_t *sa, uint64_t *speed, uint32_t *intrcnt, uint32_t *norcvbuf,
764 pt = &(sa->port[0]);
791 *intrcnt = sa->isr_intr;
792 *norcvbuf = sa->norcvbuf;
794 sp = sa->port[0].mac->ops->statistics_update(sa->port[0].mac,
803 *oerrors = sa->oerr + sp->TxFramesAbortedDueToXSCollisions +
1089 pe_sa_init(ch_t *sa)
1095 sa->config = sa->config_data.global_config;
1096 device_id = pci_config_get16(sa->ch_hpci, 2);
1097 device_subid = pci_config_get16(sa->ch_hpci, 0x2e);
1107 if (t1_get_board_rev(sa, bi, &sa->params)) {
1123 pe_small_rbuf_pool_init(ch_t *sa)
1132 if (is_T2(sa))
1137 mutex_init(&sa->ch_small_esbl, NULL, MUTEX_DRIVER, sa->ch_icookp);
1145 sa->ch_small_owner = NULL;
1146 sa->ch_sm_index = j;
1147 sa->ch_small_esb_free = NULL;
1149 rbp = ch_alloc_small_esbbuf(sa, j);
1155 rbp->cs_next = sa->ch_small_esb_free;
1156 sa->ch_small_esb_free = rbp;
1161 rbp->cs_owner = sa->ch_small_owner;
1162 sa->ch_small_owner = rbp;
1167 sa->ch_small_owner = NULL;
1170 pe_rbuf_pool_free(sa);
1182 pe_big_rbuf_pool_init(ch_t *sa)
1191 if (is_T2(sa))
1196 mutex_init(&sa->ch_big_esbl, NULL, MUTEX_DRIVER, sa->ch_icookp);
1204 sa->ch_big_owner = NULL;
1205 sa->ch_big_index = j;
1206 sa->ch_big_esb_free = NULL;
1208 rbp = ch_alloc_big_esbbuf(sa, j);
1211 rbp->cs_next = sa->ch_big_esb_free;
1212 sa->ch_big_esb_free = rbp;
1217 rbp->cs_owner = sa->ch_big_owner;
1218 sa->ch_big_owner = rbp;
1223 sa->ch_big_owner = NULL;
1226 pe_rbuf_pool_free(sa);
1237 ch_alloc_small_esbbuf(ch_t *sa, uint32_t i)
1247 rbp->cs_buf = (caddr_t)ch_alloc_dma_mem(sa, 1, DMA_STREAM|DMA_SMALN,
1248 SGE_SM_BUF_SZ(sa), &rbp->cs_pa, &rbp->cs_dh, &rbp->cs_ah);
1250 rbp->cs_buf = (caddr_t)ch_alloc_dma_mem(sa, 0, DMA_STREAM|DMA_SMALN,
1251 SGE_SM_BUF_SZ(sa), &rbp->cs_pa, &rbp->cs_dh, &rbp->cs_ah);
1259 rbp->cs_sa = sa;
1274 ch_alloc_big_esbbuf(ch_t *sa, uint32_t i)
1284 rbp->cs_buf = (caddr_t)ch_alloc_dma_mem(sa, 1, DMA_STREAM|DMA_BGALN,
1285 SGE_BG_BUF_SZ(sa), &rbp->cs_pa, &rbp->cs_dh, &rbp->cs_ah);
1287 rbp->cs_buf = (caddr_t)ch_alloc_dma_mem(sa, 0, DMA_STREAM|DMA_BGALN,
1288 SGE_BG_BUF_SZ(sa), &rbp->cs_pa, &rbp->cs_dh, &rbp->cs_ah);
1296 rbp->cs_sa = sa;
1309 pe_rbuf_pool_free(ch_t *sa)
1313 mutex_enter(&sa->ch_small_esbl);
1318 while (sa->ch_small_owner) {
1319 rbp = sa->ch_small_owner;
1320 sa->ch_small_owner = rbp->cs_owner;
1325 while ((rbp = sa->ch_small_esb_free) != NULL) {
1327 sa->ch_small_esb_free = rbp->cs_next;
1334 mutex_exit(&sa->ch_small_esbl);
1337 mutex_destroy(&sa->ch_small_esbl);
1340 mutex_enter(&sa->ch_big_esbl);
1345 while (sa->ch_big_owner) {
1346 rbp = sa->ch_big_owner;
1347 sa->ch_big_owner = rbp->cs_owner;
1352 while ((rbp = sa->ch_big_esb_free) != NULL) {
1354 sa->ch_big_esb_free = rbp->cs_next;
1361 mutex_exit(&sa->ch_big_esbl);
1364 mutex_destroy(&sa->ch_big_esbl);
1370 ch_t *sa = rbp->cs_sa;
1396 mutex_enter(&sa->ch_small_esbl);
1397 rbp->cs_next = sa->ch_small_esb_free;
1398 sa->ch_small_esb_free = rbp;
1399 mutex_exit(&sa->ch_small_esbl);
1413 ch_t *sa = rbp->cs_sa;
1439 mutex_enter(&sa->ch_big_esbl);
1440 rbp->cs_next = sa->ch_big_esb_free;
1441 sa->ch_big_esb_free = rbp;
1442 mutex_exit(&sa->ch_big_esbl);
1455 ch_get_small_rbuf(ch_t *sa)
1459 mutex_enter(&sa->ch_small_esbl);
1460 rbp = sa->ch_small_esb_free;
1462 sa->ch_small_esb_free = rbp->cs_next;
1464 mutex_exit(&sa->ch_small_esbl);
1475 ch_get_big_rbuf(ch_t *sa)
1479 mutex_enter(&sa->ch_big_esbl);
1480 rbp = sa->ch_big_esb_free;
1482 sa->ch_big_esb_free = rbp->cs_next;
1484 mutex_exit(&sa->ch_big_esbl);
1490 pe_detach(ch_t *sa)
1492 (void) sge_stop(sa->sge);
1494 pe_free_driver_resources(sa);
1498 pe_free_driver_resources(ch_t *sa)
1500 if (sa) {
1501 t1_free_sw_modules(sa);
1504 pe_rbuf_pool_free(sa);