Lines Matching defs:afep
167 #define KIOIP KSTAT_INTR_PTR(afep->afe_intrstat)
308 afe_t *afep;
403 afep = kmem_zalloc(sizeof (afe_t), KM_SLEEP);
404 ddi_set_driver_private(dip, afep);
407 if (ddi_get_iblock_cookie(dip, 0, &afep->afe_icookie) != DDI_SUCCESS) {
410 kmem_free(afep, sizeof (afe_t));
414 afep->afe_dip = dip;
415 afep->afe_cardp = cardp;
416 afep->afe_phyaddr = -1;
417 afep->afe_cachesize = cachesize;
419 afep->afe_forcefiber = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
422 mutex_init(&afep->afe_xmtlock, NULL, MUTEX_DRIVER, afep->afe_icookie);
423 mutex_init(&afep->afe_intrlock, NULL, MUTEX_DRIVER, afep->afe_icookie);
439 afep->afe_intrstat = kstat_create("afe", inst, "intr", "controller",
441 if (afep->afe_intrstat == NULL) {
445 kstat_install(afep->afe_intrstat);
450 if ((afep->afe_mii = mii_alloc(afep, dip, &afe_mii_ops)) == NULL) {
457 if (AFE_MODEL(afep) == MODEL_CENTAUR) {
458 mii_set_pauseable(afep->afe_mii, B_TRUE, B_FALSE);
460 mii_set_pauseable(afep->afe_mii, B_FALSE, B_FALSE);
466 if (ddi_regs_map_setup(dip, 1, (caddr_t *)&afep->afe_regs,
467 0, 0, &afe_devattr, &afep->afe_regshandle)) {
475 if ((afe_allocrxring(afep) != DDI_SUCCESS) ||
476 (afe_alloctxring(afep) != DDI_SUCCESS)) {
482 mutex_enter(&afep->afe_intrlock);
483 mutex_enter(&afep->afe_xmtlock);
484 if (!afe_initialize(afep)) {
485 mutex_exit(&afep->afe_xmtlock);
486 mutex_exit(&afep->afe_intrlock);
489 mutex_exit(&afep->afe_xmtlock);
490 mutex_exit(&afep->afe_intrlock);
493 afep->afe_sromwidth = afe_sromwidth(afep);
499 afe_getfactaddr(afep, afep->afe_curraddr);
500 afep->afe_promisc = B_FALSE;
503 (void) afe_m_unicst(afep, afep->afe_curraddr);
504 (void) afe_m_multicst(afep, B_TRUE, afe_broadcast);
509 if (ddi_add_intr(dip, 0, NULL, NULL, afe_intr, (caddr_t)afep) !=
523 macp->m_driver = afep;
525 macp->m_src_addr = afep->afe_curraddr;
531 if (mac_register(macp, &afep->afe_mh) == DDI_SUCCESS) {
539 if (afep->afe_icookie != NULL) {
540 ddi_remove_intr(dip, 0, afep->afe_icookie);
542 if (afep->afe_intrstat) {
543 kstat_delete(afep->afe_intrstat);
545 mutex_destroy(&afep->afe_intrlock);
546 mutex_destroy(&afep->afe_xmtlock);
548 afe_freerxring(afep);
549 afe_freetxring(afep);
551 if (afep->afe_regshandle != NULL) {
552 ddi_regs_map_free(&afep->afe_regshandle);
554 kmem_free(afep, sizeof (afe_t));
561 afe_t *afep;
563 afep = ddi_get_driver_private(dip);
564 if (afep == NULL) {
572 if (mac_unregister(afep->afe_mh) != 0) {
577 mutex_enter(&afep->afe_intrlock);
578 mutex_enter(&afep->afe_xmtlock);
579 afep->afe_flags &= ~AFE_RUNNING;
580 afe_stopall(afep);
581 mutex_exit(&afep->afe_xmtlock);
582 mutex_exit(&afep->afe_intrlock);
585 ddi_remove_intr(dip, 0, afep->afe_icookie);
588 mii_free(afep->afe_mii);
591 kstat_delete(afep->afe_intrstat);
596 afe_freerxring(afep);
597 afe_freetxring(afep);
599 ddi_regs_map_free(&afep->afe_regshandle);
600 mutex_destroy(&afep->afe_intrlock);
601 mutex_destroy(&afep->afe_xmtlock);
603 kmem_free(afep, sizeof (afe_t));
608 mii_suspend(afep->afe_mii);
611 mutex_enter(&afep->afe_intrlock);
612 mutex_enter(&afep->afe_xmtlock);
613 afep->afe_flags |= AFE_SUSPENDED;
614 afe_stopall(afep);
615 mutex_exit(&afep->afe_xmtlock);
616 mutex_exit(&afep->afe_intrlock);
626 afe_t *afep;
628 if ((afep = ddi_get_driver_private(dip)) == NULL) {
632 mutex_enter(&afep->afe_intrlock);
633 mutex_enter(&afep->afe_xmtlock);
635 afep->afe_flags &= ~AFE_SUSPENDED;
638 if (!afe_initialize(afep)) {
639 afe_error(afep->afe_dip, "unable to resume chip!");
640 afep->afe_flags |= AFE_SUSPENDED;
641 mutex_exit(&afep->afe_intrlock);
642 mutex_exit(&afep->afe_xmtlock);
647 if (afep->afe_flags & AFE_RUNNING) {
648 afe_startall(afep);
652 mutex_exit(&afep->afe_xmtlock);
653 mutex_exit(&afep->afe_intrlock);
655 mii_resume(afep->afe_mii);
663 afe_t *afep;
665 if ((afep = ddi_get_driver_private(dip)) == NULL) {
669 SETBIT(afep, CSR_PAR, PAR_RESET);
677 if ((GETCSR(afep, CSR_PAR) & PAR_RESET) == 0) {
687 afe_setrxfilt(afe_t *afep)
691 if (afep->afe_flags & AFE_SUSPENDED) {
696 rxen = GETCSR(afep, CSR_NAR) & NAR_RX_ENABLE;
700 afe_stopmac(afep);
704 if (afep->afe_promisc)
705 SETBIT(afep, CSR_NAR, NAR_RX_PROMISC);
707 CLRBIT(afep, CSR_NAR, NAR_RX_PROMISC);
710 pa0 = (afep->afe_curraddr[3] << 24) | (afep->afe_curraddr[2] << 16) |
711 (afep->afe_curraddr[1] << 8) | afep->afe_curraddr[0];
712 pa1 = (afep->afe_curraddr[5] << 8) | afep->afe_curraddr[4];
714 PUTCSR(afep, CSR_PAR0, pa0);
715 PUTCSR(afep, CSR_PAR1, pa1);
717 SETBIT(afep, CSR_NAR, rxen);
721 if (AFE_MODEL(afep) == MODEL_COMET) {
722 if (afep->afe_mctab[0] || afep->afe_mctab[1]) {
723 SETBIT(afep, CSR_NAR, NAR_RX_MULTI);
725 CLRBIT(afep, CSR_NAR, NAR_RX_MULTI);
728 CLRBIT(afep, CSR_NAR, NAR_RX_MULTI);
729 PUTCSR(afep, CSR_MAR0, afep->afe_mctab[0]);
730 PUTCSR(afep, CSR_MAR1, afep->afe_mctab[1]);
735 afe_startmac(afep);
740 afe_watchdog(afe_t *afep)
742 if ((afep->afe_txstall_time != 0) &&
743 (gethrtime() > afep->afe_txstall_time) &&
744 (afep->afe_txavail != AFE_TXRING)) {
745 afep->afe_txstall_time = 0;
746 afe_error(afep->afe_dip, "TX stall detected!");
756 afe_t *afep = arg;
769 mutex_enter(&afep->afe_intrlock);
770 mutex_enter(&afep->afe_xmtlock);
771 newval = oldval = afep->afe_mctab[index];
774 afep->afe_mccount[crc]++;
775 if (afep->afe_mccount[crc] == 1)
778 afep->afe_mccount[crc]--;
779 if (afep->afe_mccount[crc] == 0)
783 afep->afe_mctab[index] = newval;
784 afe_setrxfilt(afep);
787 mutex_exit(&afep->afe_xmtlock);
788 mutex_exit(&afep->afe_intrlock);
796 afe_t *afep = arg;
799 mutex_enter(&afep->afe_intrlock);
800 mutex_enter(&afep->afe_xmtlock);
802 afep->afe_promisc = on;
804 afe_setrxfilt(afep);
805 mutex_exit(&afep->afe_xmtlock);
806 mutex_exit(&afep->afe_intrlock);
814 afe_t *afep = arg;
817 mutex_enter(&afep->afe_intrlock);
818 mutex_enter(&afep->afe_xmtlock);
820 bcopy(macaddr, afep->afe_curraddr, ETHERADDRL);
821 afe_setrxfilt(afep);
823 mutex_exit(&afep->afe_xmtlock);
824 mutex_exit(&afep->afe_intrlock);
832 afe_t *afep = arg;
835 mutex_enter(&afep->afe_xmtlock);
837 if (afep->afe_flags & AFE_SUSPENDED) {
839 afep->afe_carrier_errors++;
843 mutex_exit(&afep->afe_xmtlock);
851 if (!afe_send(afep, mp)) {
857 mutex_exit(&afep->afe_xmtlock);
865 afe_t *afep = arg;
867 if (mii_m_loop_ioctl(afep->afe_mii, wq, mp))
877 afe_initialize(afe_t *afep)
883 ASSERT(mutex_owned(&afep->afe_intrlock));
884 ASSERT(mutex_owned(&afep->afe_xmtlock));
886 SETBIT(afep, CSR_PAR, PAR_RESET);
889 val = GETCSR(afep, CSR_PAR);
895 afe_error(afep->afe_dip, "timed out waiting for reset!");
906 switch (afep->afe_cachesize) {
923 PUTCSR(afep, CSR_PAR, par);
926 SETBIT(afep, CSR_CR, CR_TXURAUTOR);
928 afe_resetrings(afep);
931 (void) GETCSR(afep, CSR_LPC);
933 nar = GETCSR(afep, CSR_NAR);
937 PUTCSR(afep, CSR_NAR, nar);
939 afe_setrxfilt(afep);
949 afe_sromwidth(afe_t *afep)
957 PUTCSR(afep, CSR_SPR, eeread & ~SPR_SROM_CHIP);
959 PUTCSR(afep, CSR_SPR, eeread);
965 PUTCSR(afep, CSR_SPR, eeread | val);
967 PUTCSR(afep, CSR_SPR, eeread | val | SPR_SROM_CLOCK);
971 PUTCSR(afep, CSR_SPR, eeread);
974 PUTCSR(afep, CSR_SPR, eeread | SPR_SROM_CLOCK);
976 if (!(GETCSR(afep, CSR_SPR) & SPR_SROM_DOUT)) {
977 PUTCSR(afep, CSR_SPR, eeread);
981 PUTCSR(afep, CSR_SPR, eeread);
986 PUTCSR(afep, CSR_SPR, eeread &~ SPR_SROM_CHIP);
997 afe_readsromword(afe_t *afep, unsigned romaddr)
1008 addrlen = afep->afe_sromwidth;
1016 PUTCSR(afep, CSR_SPR, eeread & ~SPR_SROM_CHIP);
1017 PUTCSR(afep, CSR_SPR, eeread);
1023 PUTCSR(afep, CSR_SPR, eeread | val);
1025 PUTCSR(afep, CSR_SPR, eeread | val | SPR_SROM_CLOCK);
1029 PUTCSR(afep, CSR_SPR, eeread);
1032 PUTCSR(afep, CSR_SPR, eeread | SPR_SROM_CLOCK);
1035 if (GETCSR(afep, CSR_SPR) & SPR_SROM_DOUT) {
1038 PUTCSR(afep, CSR_SPR, eeread);
1043 PUTCSR(afep, CSR_SPR, eeread &~ SPR_SROM_CHIP);
1055 afe_readsrom(afe_t *afep, unsigned romaddr, unsigned len, char *dest)
1061 word = afe_readsromword(afep, romaddr + i);
1068 afe_getfactaddr(afe_t *afep, uchar_t *eaddr)
1070 afe_readsrom(afep, SROM_ENADDR, ETHERADDRL / 2, (char *)eaddr);
1081 afe_t *afep = arg;
1091 if ((mii_get_id(afep->afe_mii) & 0xfffffff0) != 0x225410) {
1096 phyaddr = mii_get_addr(afep->afe_mii);
1100 switch (afep->afe_forcefiber) {
1111 mcr = afe_mii_read(afep, phyaddr, PHY_MCR);
1121 afe_mii_write(afep, phyaddr, PHY_MCR, mcr);
1128 pilr = afe_mii_read(afep, phyaddr, PHY_PILR);
1130 afe_mii_write(afep, phyaddr, PHY_PILR, pilr);
1136 afe_t *afep = arg;
1138 if (AFE_MODEL(afep) == MODEL_CENTAUR) {
1139 if (mii_get_flowctrl(afep->afe_mii) == LINK_FLOWCTRL_BI) {
1140 SETBIT(afep, CSR_CR, CR_PAUSE);
1142 CLRBIT(afep, CSR_CR, CR_PAUSE);
1145 mac_link_update(afep->afe_mh, link);
1149 afe_miitristate(afe_t *afep)
1153 PUTCSR(afep, CSR_SPR, val);
1155 PUTCSR(afep, CSR_SPR, val | SPR_MII_CLOCK);
1160 afe_miiwritebit(afe_t *afep, uint8_t bit)
1164 PUTCSR(afep, CSR_SPR, val);
1166 PUTCSR(afep, CSR_SPR, val | SPR_MII_CLOCK);
1171 afe_miireadbit(afe_t *afep)
1176 PUTCSR(afep, CSR_SPR, val);
1178 bit = (GETCSR(afep, CSR_SPR) & SPR_MII_DIN) ? 1 : 0;
1179 PUTCSR(afep, CSR_SPR, val | SPR_MII_CLOCK);
1187 afe_t *afep = arg;
1195 switch (AFE_MODEL(afep)) {
1197 return (afe_miireadcomet(afep, phy, reg));
1199 return (afe_miireadgeneral(afep, phy, reg));
1205 afe_miireadgeneral(afe_t *afep, uint8_t phy, uint8_t reg)
1212 afe_miiwritebit(afep, 1);
1216 afe_miiwritebit(afep, 0);
1217 afe_miiwritebit(afep, 1);
1220 afe_miiwritebit(afep, 1);
1221 afe_miiwritebit(afep, 0);
1225 afe_miiwritebit(afep, (phy & i) ? 1 : 0);
1230 afe_miiwritebit(afep, (reg & i) ? 1 : 0);
1234 afe_miitristate(afep);
1235 afe_miiwritebit(afep, 0);
1240 value |= afe_miireadbit(afep);
1242 afe_miitristate(afep);
1247 afe_miireadcomet(afe_t *afep, uint8_t phy, uint8_t reg)
1277 return (GETCSR16(afep, reg) & 0xFFFF);
1283 afe_t *afep = arg;
1292 switch (AFE_MODEL(afep)) {
1294 afe_miiwritecomet(afep, phy, reg, val);
1297 afe_miiwritegeneral(afep, phy, reg, val);
1303 afe_miiwritegeneral(afe_t *afep, uint8_t phy, uint8_t reg, uint16_t val)
1309 afe_miiwritebit(afep, 1);
1313 afe_miiwritebit(afep, 0);
1314 afe_miiwritebit(afep, 1);
1317 afe_miiwritebit(afep, 0);
1318 afe_miiwritebit(afep, 1);
1322 afe_miiwritebit(afep, (phy & i) ? 1 : 0);
1327 afe_miiwritebit(afep, (reg & i) ? 1 : 0);
1331 afe_miiwritebit(afep, 1);
1332 afe_miiwritebit(afep, 0);
1336 afe_miiwritebit(afep, (val & i) ? 1 : 0);
1340 afe_miitristate(afep);
1344 afe_miiwritecomet(afe_t *afep, uint8_t phy, uint8_t reg, uint16_t val)
1374 PUTCSR16(afep, reg, val);
1380 afe_t *afep = arg;
1383 mutex_enter(&afep->afe_intrlock);
1384 mutex_enter(&afep->afe_xmtlock);
1386 afe_startall(afep);
1387 afep->afe_flags |= AFE_RUNNING;
1389 mutex_exit(&afep->afe_xmtlock);
1390 mutex_exit(&afep->afe_intrlock);
1392 mii_start(afep->afe_mii);
1400 afe_t *afep = arg;
1402 mii_stop(afep->afe_mii);
1405 mutex_enter(&afep->afe_intrlock);
1406 mutex_enter(&afep->afe_xmtlock);
1408 afe_stopall(afep);
1409 afep->afe_flags &= ~AFE_RUNNING;
1411 mutex_exit(&afep->afe_xmtlock);
1412 mutex_exit(&afep->afe_intrlock);
1416 afe_startmac(afe_t *afep)
1419 ASSERT(mutex_owned(&afep->afe_intrlock));
1420 ASSERT(mutex_owned(&afep->afe_xmtlock));
1423 SETBIT(afep, CSR_NAR, NAR_TX_ENABLE | NAR_RX_ENABLE);
1425 if (afep->afe_txavail != AFE_TXRING)
1426 PUTCSR(afep, CSR_TDR, 0);
1429 if (afep->afe_flags & AFE_RUNNING)
1430 mac_tx_update(afep->afe_mh);
1433 PUTCSR(afep, CSR_TIMER, TIMER_LOOP |
1438 afe_stopmac(afe_t *afep)
1443 ASSERT(mutex_owned(&afep->afe_intrlock));
1444 ASSERT(mutex_owned(&afep->afe_xmtlock));
1446 CLRBIT(afep, CSR_NAR, NAR_TX_ENABLE | NAR_RX_ENABLE);
1458 if ((GETCSR(afep, CSR_SR) & (SR_TX_STATE | SR_RX_STATE)) == 0)
1464 PUTCSR(afep, CSR_SR2, INT_RXSTOPPED | INT_TXSTOPPED);
1467 PUTCSR(afep, CSR_TIMER, 0);
1471 afe_resetrings(afe_t *afep)
1476 PUTCSR(afep, CSR_RDB, 0);
1477 PUTCSR(afep, CSR_TDB, 0);
1480 afep->afe_rxhead = 0;
1481 afep->afe_txreclaim = 0;
1482 afep->afe_txsend = 0;
1483 afep->afe_txavail = AFE_TXRING;
1487 afe_desc_t *tmdp = &afep->afe_txdescp[i];
1492 PUTTXDESC(afep, tmdp->desc_status, 0);
1493 PUTTXDESC(afep, tmdp->desc_control, control);
1494 PUTTXDESC(afep, tmdp->desc_buffer1, 0);
1495 PUTTXDESC(afep, tmdp->desc_buffer2, 0);
1496 SYNCTXDESC(afep, i, DDI_DMA_SYNC_FORDEV);
1498 PUTCSR(afep, CSR_TDB, afep->afe_txdesc_paddr);
1502 afe_rxbuf_t *rxb = afep->afe_rxbufs[i];
1503 afe_desc_t *rmdp = &afep->afe_rxdescp[i];
1510 PUTRXDESC(afep, rmdp->desc_buffer1, rxb->rxb_paddr);
1511 PUTRXDESC(afep, rmdp->desc_buffer2, 0);
1512 PUTRXDESC(afep, rmdp->desc_control, control);
1513 PUTRXDESC(afep, rmdp->desc_status, RXSTAT_OWN);
1514 SYNCRXDESC(afep, i, DDI_DMA_SYNC_FORDEV);
1516 PUTCSR(afep, CSR_RDB, afep->afe_rxdesc_paddr);
1520 afe_stopall(afe_t *afep)
1522 afe_disableinterrupts(afep);
1523 afe_stopmac(afep);
1527 afe_startall(afe_t *afep)
1529 ASSERT(mutex_owned(&afep->afe_intrlock));
1530 ASSERT(mutex_owned(&afep->afe_xmtlock));
1533 afe_disableinterrupts(afep);
1536 (void) afe_initialize(afep);
1539 afe_enableinterrupts(afep);
1542 afe_startmac(afep);
1546 afe_resetall(afe_t *afep)
1548 afe_stopall(afep);
1549 afe_startall(afep);
1553 afe_alloctxbuf(afe_t *afep)
1562 if (ddi_dma_alloc_handle(afep->afe_dip, &afe_dma_txattr,
1597 afe_allocrxbuf(afe_t *afep)
1606 if (ddi_dma_alloc_handle(afep->afe_dip, &afe_dma_attr,
1646 afe_allocrxring(afe_t *afep)
1658 rval = ddi_dma_alloc_handle(afep->afe_dip, &afe_dma_attr,
1659 DDI_DMA_SLEEP, NULL, &afep->afe_rxdesc_dmah);
1661 afe_error(afep->afe_dip,
1666 rval = ddi_dma_mem_alloc(afep->afe_rxdesc_dmah, size, &afe_devattr,
1668 &afep->afe_rxdesc_acch);
1670 afe_error(afep->afe_dip,
1675 rval = ddi_dma_addr_bind_handle(afep->afe_rxdesc_dmah, NULL, kaddr,
1679 afe_error(afep->afe_dip,
1688 afep->afe_rxdesc_paddr = dmac.dmac_address;
1689 afep->afe_rxdescp = (void *)kaddr;
1692 afep->afe_rxbufs = kmem_zalloc(AFE_RXRING * sizeof (afe_rxbuf_t *),
1697 afe_rxbuf_t *rxb = afe_allocrxbuf(afep);
1700 afep->afe_rxbufs[i] = rxb;
1710 afe_alloctxring(afe_t *afep)
1722 rval = ddi_dma_alloc_handle(afep->afe_dip, &afe_dma_attr,
1723 DDI_DMA_SLEEP, NULL, &afep->afe_txdesc_dmah);
1725 afe_error(afep->afe_dip,
1730 rval = ddi_dma_mem_alloc(afep->afe_txdesc_dmah, size, &afe_devattr,
1732 &afep->afe_txdesc_acch);
1734 afe_error(afep->afe_dip,
1739 rval = ddi_dma_addr_bind_handle(afep->afe_txdesc_dmah, NULL, kaddr,
1743 afe_error(afep->afe_dip,
1752 afep->afe_txdesc_paddr = dmac.dmac_address;
1753 afep->afe_txdescp = (void *)kaddr;
1756 afep->afe_txbufs = kmem_zalloc(AFE_TXRING * sizeof (afe_txbuf_t *),
1761 afe_txbuf_t *txb = afe_alloctxbuf(afep);
1764 afep->afe_txbufs[i] = txb;
1771 afe_freerxring(afe_t *afep)
1776 afe_destroyrxbuf(afep->afe_rxbufs[i]);
1779 if (afep->afe_rxbufs) {
1780 kmem_free(afep->afe_rxbufs,
1784 if (afep->afe_rxdesc_paddr)
1785 (void) ddi_dma_unbind_handle(afep->afe_rxdesc_dmah);
1786 if (afep->afe_rxdesc_acch)
1787 ddi_dma_mem_free(&afep->afe_rxdesc_acch);
1788 if (afep->afe_rxdesc_dmah)
1789 ddi_dma_free_handle(&afep->afe_rxdesc_dmah);
1793 afe_freetxring(afe_t *afep)
1798 afe_destroytxbuf(afep->afe_txbufs[i]);
1801 if (afep->afe_txbufs) {
1802 kmem_free(afep->afe_txbufs,
1805 if (afep->afe_txdesc_paddr)
1806 (void) ddi_dma_unbind_handle(afep->afe_txdesc_dmah);
1807 if (afep->afe_txdesc_acch)
1808 ddi_dma_mem_free(&afep->afe_txdesc_acch);
1809 if (afep->afe_txdesc_dmah)
1810 ddi_dma_free_handle(&afep->afe_txdesc_dmah);
1819 afe_t *afep = (void *)arg;
1824 mutex_enter(&afep->afe_intrlock);
1826 if (afep->afe_flags & AFE_SUSPENDED) {
1828 mutex_exit(&afep->afe_intrlock);
1833 status = GETCSR(afep, CSR_SR2) & INT_ALL;
1837 mutex_exit(&afep->afe_intrlock);
1841 PUTCSR(afep, CSR_SR2, status);
1844 if (!(afep->afe_flags & AFE_RUNNING)) {
1846 mutex_exit(&afep->afe_intrlock);
1852 mp = afe_receive(afep);
1854 PUTCSR(afep, CSR_RDR, 0); /* wake up chip */
1859 mutex_enter(&afep->afe_xmtlock);
1860 afe_reclaim(afep);
1861 mutex_exit(&afep->afe_xmtlock);
1864 if ((status & INT_TIMER) && (afe_watchdog(afep) != DDI_SUCCESS)) {
1872 afep->afe_jabber++;
1878 switch (GETCSR(afep, CSR_SR) & SR_BERR_TYPE) {
1880 afe_error(afep->afe_dip, "PCI parity error");
1883 afe_error(afep->afe_dip, "PCI target abort");
1886 afe_error(afep->afe_dip, "PCI master abort");
1889 afe_error(afep->afe_dip, "Unknown PCI error");
1899 mutex_enter(&afep->afe_xmtlock);
1900 afe_resetall(afep);
1901 mutex_exit(&afep->afe_xmtlock);
1902 mutex_exit(&afep->afe_intrlock);
1904 mii_reset(afep->afe_mii);
1906 mutex_exit(&afep->afe_intrlock);
1910 mii_check(afep->afe_mii);
1917 mac_rx(afep->afe_mh, NULL, mp);
1924 afe_enableinterrupts(afe_t *afep)
1928 if (afep->afe_wantw)
1931 PUTCSR(afep, CSR_IER2, mask);
1933 if (AFE_MODEL(afep) == MODEL_COMET) {
1939 PUTCSR16(afep, CSR_XIE, XIE_LDE | XIE_ANCE);
1944 afe_disableinterrupts(afe_t *afep)
1947 PUTCSR(afep, CSR_IER2, INT_NONE);
1950 PUTCSR(afep, CSR_SR2, INT_ALL);
1954 afe_send(afe_t *afep, mblk_t *mp)
1962 ASSERT(mutex_owned(&afep->afe_xmtlock));
1967 afep->afe_macxmt_errors++;
1972 if (afep->afe_txavail < AFE_TXRECLAIM)
1973 afe_reclaim(afep);
1975 if (afep->afe_txavail == 0) {
1977 afep->afe_wantw = B_TRUE;
1979 afe_enableinterrupts(afep);
1983 txsend = afep->afe_txsend;
1990 txb = afep->afe_txbufs[txsend];
1996 afep->afe_opackets++;
1997 afep->afe_obytes += len;
2000 afep->afe_multixmt++;
2002 afep->afe_brdcstxmt++;
2011 tmd = &afep->afe_txdescp[txsend];
2014 PUTTXDESC(afep, tmd->desc_control, control);
2015 PUTTXDESC(afep, tmd->desc_buffer1, txb->txb_paddr);
2016 PUTTXDESC(afep, tmd->desc_buffer2, 0);
2017 PUTTXDESC(afep, tmd->desc_status, TXSTAT_OWN);
2019 SYNCTXDESC(afep, txsend, DDI_DMA_SYNC_FORDEV);
2024 afep->afe_txavail--;
2025 afep->afe_txsend = (txsend + 1) % AFE_TXRING;
2031 afep->afe_txstall_time = gethrtime() + (5 * 1000000000ULL);
2037 PUTCSR(afep, CSR_TDR, 0);
2046 afe_reclaim(afe_t *afep)
2050 while (afep->afe_txavail != AFE_TXRING) {
2053 int index = afep->afe_txreclaim;
2055 tmdp = &afep->afe_txdescp[index];
2058 SYNCTXDESC(afep, index, DDI_DMA_SYNC_FORKERNEL);
2060 control = GETTXDESC(afep, tmdp->desc_control);
2061 status = GETTXDESC(afep, tmdp->desc_status);
2068 afep->afe_txavail++;
2069 afep->afe_txreclaim = (index + 1) % AFE_TXRING;
2079 afep->afe_errxmt++;
2083 afep->afe_macxmt_errors++;
2087 afep->afe_carrier_errors++;
2090 afep->afe_underflow++;
2093 afep->afe_tx_late_collisions++;
2096 afep->afe_ex_collisions++;
2097 afep->afe_collisions += 16;
2102 afep->afe_defer_xmts++;
2107 afep->afe_collisions++;
2108 afep->afe_first_collisions++;
2110 afep->afe_collisions += TXCOLLCNT(status);
2111 afep->afe_multi_collisions += TXCOLLCNT(status);
2115 if (afep->afe_txavail >= AFE_TXRESCHED) {
2116 if (afep->afe_wantw) {
2121 afep->afe_wantw = B_FALSE;
2122 afe_enableinterrupts(afep);
2123 mac_tx_update(afep->afe_mh);
2129 afe_receive(afe_t *afep)
2140 head = afep->afe_rxhead;
2145 rmd = &afep->afe_rxdescp[head];
2146 rxb = afep->afe_rxbufs[head];
2148 SYNCRXDESC(afep, head, DDI_DMA_SYNC_FORKERNEL);
2149 status = GETRXDESC(afep, rmd->desc_status);
2161 afep->afe_errrcv++;
2170 afep->afe_toolong_errors++;
2173 afep->afe_macrcv_errors++;
2176 afep->afe_runt++;
2180 afep->afe_macrcv_errors++;
2183 afep->afe_align_errors++;
2186 afep->afe_fcs_errors++;
2189 afep->afe_overflow++;
2194 afep->afe_errrcv++;
2195 afep->afe_toolong_errors++;
2204 afep->afe_errrcv++;
2205 afep->afe_norcvbuf++;
2215 afep->afe_ipackets++;
2216 afep->afe_rbytes += len;
2220 afep->afe_brdcstrcv++;
2222 afep->afe_multircv++;
2230 PUTRXDESC(afep, rmd->desc_status, RXSTAT_OWN);
2231 SYNCRXDESC(afep, head, DDI_DMA_SYNC_FORDEV);
2237 afep->afe_rxhead = head;
2245 afe_t *afep = arg;
2247 mutex_enter(&afep->afe_xmtlock);
2248 if ((afep->afe_flags & (AFE_RUNNING|AFE_SUSPENDED)) == AFE_RUNNING)
2249 afe_reclaim(afep);
2250 mutex_exit(&afep->afe_xmtlock);
2252 if (mii_m_getstat(afep->afe_mii, stat, val) == 0) {
2257 *val = afep->afe_multircv;
2261 *val = afep->afe_brdcstrcv;
2265 *val = afep->afe_multixmt;
2269 *val = afep->afe_brdcstxmt;
2273 *val = afep->afe_ipackets;
2277 *val = afep->afe_rbytes;
2281 *val = afep->afe_opackets;
2285 *val = afep->afe_obytes;
2289 *val = afep->afe_norcvbuf;
2297 *val = afep->afe_collisions;
2301 *val = afep->afe_errrcv;
2305 *val = afep->afe_errxmt;
2309 *val = afep->afe_align_errors;
2313 *val = afep->afe_fcs_errors;
2317 *val = afep->afe_sqe_errors;
2321 *val = afep->afe_defer_xmts;
2325 *val = afep->afe_first_collisions;
2329 *val = afep->afe_multi_collisions;
2333 *val = afep->afe_tx_late_collisions;
2337 *val = afep->afe_ex_collisions;
2341 *val = afep->afe_macxmt_errors;
2345 *val = afep->afe_carrier_errors;
2349 *val = afep->afe_toolong_errors;
2353 *val = afep->afe_macrcv_errors;
2357 *val = afep->afe_overflow;
2361 *val = afep->afe_underflow;
2365 *val = afep->afe_runt;
2369 *val = afep->afe_jabber;
2382 afe_t *afep = arg;
2384 return (mii_m_getprop(afep->afe_mii, name, num, sz, val));
2391 afe_t *afep = arg;
2393 return (mii_m_setprop(afep->afe_mii, name, num, sz, val));
2400 afe_t *afep = arg;
2402 mii_m_propinfo(afep->afe_mii, name, num, prh);