7911 	drmach_slot1_pause_t *slot1;  in drmach_slot1_pause_add_axq()  local
7920 	slot1 = kmem_zalloc(sizeof (*slot1), KM_SLEEP);  in drmach_slot1_pause_add_axq()
7934 	slot1->axq.dip = axq_dip;  in drmach_slot1_pause_add_axq()
7935 	slot1->axq.portid = axq_portid;  in drmach_slot1_pause_add_axq()
7936 	slot1->axq.reg_basepa = reg;  in drmach_slot1_pause_add_axq()
7937 	slot1_paused[axq_exp] = slot1;  in drmach_slot1_pause_add_axq()
7958 	drmach_slot1_pause_t *slot1;  in drmach_slot1_pause_free()  local
7961 		if ((slot1 = slot1_paused[i]) == NULL)  in drmach_slot1_pause_free()
7966 				drmach_s1p_pci_free(&slot1->schizo[j].pci[k]);  in drmach_slot1_pause_free()
7968 		kmem_free(slot1, sizeof (*slot1));  in drmach_slot1_pause_free()
8217 	drmach_slot1_pause_t *slot1;  in drmach_slot1_pause_update()  local
8220 		if ((slot1 = slot1_paused[i]) == NULL)  in drmach_slot1_pause_update()
8223 		drmach_s1p_axq_update(&slot1->axq, iter);  in drmach_slot1_pause_update()
8225 			drmach_s1p_schizo_update(&slot1->schizo[j], iter);  in drmach_slot1_pause_update()
8390 	drmach_slot1_pause_t *slot1;  in drmach_slot1_pause_verify()  local
8396 		if ((slot1 = slot1_paused[i]) == NULL)  in drmach_slot1_pause_verify()
8400 			if (slot1->schizo[j].csr_basepa == 0x0UL)  in drmach_slot1_pause_verify()
8403 			if (slot1->schizo[j].regs[iter].errlog &  in drmach_slot1_pause_verify()
8413 				drmach_s1p_schizo_log_intr(&slot1->schizo[j],  in drmach_slot1_pause_verify()
8424 			if ((slot1 = slot1_paused[i]) == NULL)  in drmach_slot1_pause_verify()
8427 			if (slot1->axq.pic_l2_io_q[DRMACH_POST_SUSPEND] !=  in drmach_slot1_pause_verify()
8428 			    slot1->axq.pic_l2_io_q[DRMACH_PRE_RESUME]) {  in drmach_slot1_pause_verify()
8433 				    slot1->axq.pic_l2_io_q[DRMACH_POST_SUSPEND],  in drmach_slot1_pause_verify()
8434 				    slot1->axq.pic_l2_io_q[DRMACH_PRE_RESUME]);  in drmach_slot1_pause_verify()