7843 	drmach_s1p_schizo_t	schizo[STARCAT_SLOT1_IO_MAX];  member
7966 				drmach_s1p_pci_free(&slot1->schizo[j].pci[k]);  in drmach_slot1_pause_free()
8019 	ASSERT(slot1_paused[exp]->schizo[ioc_unum].csr_basepa == 0x0UL ||  in drmach_find_slot1_io()
8020 	    slot1_paused[exp]->schizo[ioc_unum].csr_basepa == schizo_csr_pa);  in drmach_find_slot1_io()
8023 	slot1_paused[exp]->schizo[ioc_unum].csr_basepa = schizo_csr_pa;  in drmach_find_slot1_io()
8024 	pci = &slot1_paused[exp]->schizo[ioc_unum].pci[leaf_unum];  in drmach_find_slot1_io()
8177 drmach_s1p_schizo_update(drmach_s1p_schizo_t *schizo, drmach_sr_iter_t iter)  in drmach_s1p_schizo_update()  argument
8182 	if (schizo->csr_basepa == 0x0UL)  in drmach_s1p_schizo_update()
8185 	schizo->regs[iter].csr =  in drmach_s1p_schizo_update()
8186 	    lddphysio(schizo->csr_basepa + SCHIZO_CB_CSR_OFFSET);  in drmach_s1p_schizo_update()
8187 	schizo->regs[iter].errctrl =  in drmach_s1p_schizo_update()
8188 	    lddphysio(schizo->csr_basepa + SCHIZO_CB_ERRCTRL_OFFSET);  in drmach_s1p_schizo_update()
8189 	schizo->regs[iter].errlog =  in drmach_s1p_schizo_update()
8190 	    lddphysio(schizo->csr_basepa + SCHIZO_CB_ERRLOG_OFFSET);  in drmach_s1p_schizo_update()
8193 		pci = &schizo->pci[i];  in drmach_s1p_schizo_update()
8225 			drmach_s1p_schizo_update(&slot1->schizo[j], iter);  in drmach_slot1_pause_update()
8314 drmach_s1p_schizo_log_intr(drmach_s1p_schizo_t *schizo, int exp,  in drmach_s1p_schizo_log_intr()  argument
8330 		pci = &schizo->pci[i];  in drmach_s1p_schizo_log_intr()
8400 			if (slot1->schizo[j].csr_basepa == 0x0UL)  in drmach_slot1_pause_verify()
8403 			if (slot1->schizo[j].regs[iter].errlog &  in drmach_slot1_pause_verify()
8413 				drmach_s1p_schizo_log_intr(&slot1->schizo[j],  in drmach_slot1_pause_verify()