Lines Matching refs:tmp3
54 #define DCACHE_FLUSHPAGE(arg1, arg2, tmp1, tmp2, tmp3) \ argument
65 sethi %hi(dcache_size), tmp3 ;\
66 ld [tmp3 + %lo(dcache_size)], tmp3 ;\
75 sub tmp3, tmp1, tmp2 ;\
93 set MMU_PAGESIZE, tmp3 ;\
95 sub tmp3, tmp1, tmp3 ;\
97 ldxa [arg2 + tmp3]ASI_DC_TAG, tmp2 /* read tag */ ;\
104 stxa %g0, [arg2 + tmp3]ASI_DC_TAG ;\
107 cmp %g0, tmp3 ;\
109 sub tmp3, tmp1, tmp3 ;\
121 sub tmp3, tmp1, arg2 ;\
215 #define VTAG_FLUSHUPAGE(lbl, arg1, arg2, tmp1, tmp2, tmp3, tmp4) \ argument
220 set MMU_SCONTEXT, tmp3 ;\
221 ldxa [tmp3]ASI_DMMU, tmp4 ;\
226 stxa arg2, [tmp3]ASI_DMMU ;\
233 stxa tmp4, [tmp3]ASI_DMMU ;\
247 #define DTLB_FLUSH_UNLOCKED_UCTXS(lbl, arg1, tmp1, tmp2, tmp3, \ argument
250 sllx arg1, 3, tmp3 ;\
252 ldxa [tmp3]ASI_DTLB_ACCESS, tmp4 ;\
261 ldxa [tmp3]ASI_DTLB_TAGREAD, tmp2 ;\
268 VTAG_FLUSHUPAGE(VD/**/lbl, tmp5, tmp6, tmp1, tmp2, tmp3, tmp4) ;\
282 #define ITLB_FLUSH_UNLOCKED_UCTXS(lbl, arg1, tmp1, tmp2, tmp3, \ argument
285 sllx arg1, 3, tmp3 ;\
287 ldxa [tmp3]ASI_ITLB_ACCESS, tmp4 ;\
296 ldxa [tmp3]ASI_ITLB_TAGREAD, tmp2 ;\
303 VTAG_FLUSHUPAGE(VI/**/lbl, tmp5, tmp6, tmp1, tmp2, tmp3, tmp4) ;\