Lines Matching refs:prefetch
1208 ! On US-III, the prefetch instruction queue is 8 entries deep.
1213 ! Since prefetch can only bring in 64 bytes at a time (See Sparc
1218 ! Since the prefetch queue is 8 entries deep, we currently can
1238 ! |Preftch| but we enqueue prefetch for addr = XXX1
1240 ! +-------+<--- this queue slot will be a prefetch instruction for
1270 ! we'll need an additional prefetch to get an entire page
1291 prefetch [%o0+STRIDE1], #n_writes
1293 prefetch [%o0+STRIDE2], #n_writes
1297 ! Note on CHEETAH to prefetch for read, we really use #one_write.
1301 prefetch [%o0+STRIDE1], #one_write
1303 prefetch [%o0+STRIDE2], #one_write
1311 ! So prefetch for pp + 1, which is
1325 prefetch [%o0+STRIDE1], #n_writes
1327 prefetch [%o0+STRIDE2], #n_writes
1331 prefetch [%o0+STRIDE1], #n_reads
1333 prefetch [%o0+STRIDE2], #n_reads
1345 prefetch [%o0+STRIDE1], #n_writes
1347 prefetch [%o0+STRIDE2], #n_writes
1351 prefetch [%o0+STRIDE1], #n_writes
1353 prefetch [%o0+STRIDE2], #n_writes
1404 ! The hardware will prefetch the 64 byte cache aligned block
1405 ! that contains the address specified in the prefetch instruction.
1406 ! Since the size of the smap struct is 48 bytes, issuing 1 prefetch
1407 ! per pass will suffice as long as we prefetch far enough ahead to
1409 ! spans multiple hardware prefetch blocks. Let's prefetch as far
1421 prefetch [%o0-SMAP_STRIDE], #n_writes