Lines Matching defs:fdctlr
269 struct fdctlr { struct
270 struct fdctlr *c_next; /* next in a linked list */ argument
271 union fdcreg *c_reg; /* controller registers */
272 volatile uchar_t *c_control; /* addr of c_reg->fdc_control */
273 uchar_t *c_fifo; /* addr of c_reg->fdc_fifo */
274 uchar_t *c_dor; /* addr of c_reg->fdc_dor (077) */
275 uchar_t *c_dir; /* addr of c_reg->fdc_dir (077) */
276 caddr_t *c_dma_regs; /* DMA engine registers */
277 uint_t c_fdtype; /* type of ctlr */
278 uint_t *c_hiintct; /* for convenience.. */
279 uint_t c_softic; /* for use by hi level interrupt */
280 uchar_t c_fasttrap; /* 1 if fast traps enabled, else 0 */
281 struct fdcsb c_csb; /* current csb */
282 kmutex_t c_hilock; /* high level mutex */
283 kmutex_t c_lolock; /* low level mutex */
284 kcondvar_t c_iocv; /* condition var for I/O done */
285 kcondvar_t c_csbcv; /* condition var for owning csb */
286 kcondvar_t c_motoncv; /* condition var for motor on */
287 kcondvar_t c_statecv; /* condition var for media state */
288 kcondvar_t c_suspend_cv; /* Cond Var on power management */
289 ksema_t c_ocsem; /* sem for serializing opens/closes */
290 ddi_iblock_cookie_t c_block; /* returned from ddi_add_fastintr */
291 ddi_softintr_t c_softid; /* returned from ddi_add_softintr */
292 dev_info_t *c_dip; /* controller's dev_info node */
293 timeout_id_t c_timeid; /* watchdog timer id */
294 timeout_id_t c_mtimeid; /* motor off timer id */
295 struct fdunit *c_un; /* unit on controller */
296 struct buf *c_actf; /* head of wait list */
297 struct buf *c_actl; /* tail of wait list */
298 struct buf *c_current; /* currently active buf */
299 struct kstat *c_intrstat; /* interrupt stats pointer */
300 struct fdstat fdstats; /* statistics */
301 uchar_t c_flags; /* state information */
302 caddr_t c_auxiova; /* auxio virtual address */
303 uchar_t c_auxiodata; /* auxio data to enable TC */
304 uchar_t c_auxiodata2; /* auxio data to disable TC */
305 ddi_acc_handle_t c_handlep_cont;
307 ddi_acc_handle_t c_handlep_dma; /* data access handle for DMA engine */
308 ddi_acc_handle_t c_handlep_aux; /* data access handle for aux regs */
309 ddi_dma_handle_t c_dmahandle; /* DMA handle */
310 uint_t *c_auxio_reg; /* auxio registers */
311 ddi_dma_attr_t c_fd_dma_lim; /* DMA limit structure */
312 caddr_t dma_buf; /* Temporary DMAble buffer */
313 ddi_acc_handle_t c_dma_buf_handle; /* DMA handle for dma_buf */
314 uint_t sb_dma_channel; /* 8237 dma channel no. */
315 uchar_t sb_dma_lock; /* Status of DMA lock by isadma */