346 struct	eri {  struct
347 	mac_handle_t		mh;		/* GLDv3 handle */
348 	dev_info_t		*dip;		/* associated dev_info */
349 	uint_t			instance;	/* instance */
351 	int			pci_mode;	/* sbus/pci device (future) */
352 	int			cpci_mode;	/* compact pci dev (future) */
353 	int			low_power_mode; /* E* (low power) */
354 	int			asic_rev;	/* ERI ASIC rev no. */
355 	int			board_rev;	/* ERI ASIC rev no. */
356 	int			burstsizes;	/* binary encoded val */
357 	int			pagesize;	/* btop(9f) */
358 	uint32_t		rxfifo_size;	/* RX FIFO size */
360 	int			rpending;	/* Max.no. of RX bufs post */
361 	int			tpending;	/* Max.no. of tX bufs post */
362 	int			tx_cur_cnt;	/* # of packets for int_me */
364 	uint_t			multi_refcnt;
365 	boolean_t		promisc;
367 	int			mifpoll_enable;
368 	int			frame_enable;
369 	int			lance_mode_enable;
370 	int			ngu_enable;
371 	int			link_pulse_disabled;
372 	int			xmit_dma_mode;
373 	int			rcv_dma_mode;
374 	uint8_t			ouraddr[ETHERADDRL];	/* unicast address */
375 	uint32_t		flags;		/* misc. flags */
376 	uint32_t		alloc_flag;	/* Buff alloc. status flags */
377 	boolean_t		wantw;		/* xmit: out of resources */
402 	struct	eri_tmd		*eri_tmdp;	/* xmit descript ring start */  argument
403 	struct	eri_tmd		*eri_tmdlimp;	/* xmit descript ring end */  argument
406 	volatile struct	eri_tmd	*tnextp;	/* next free tmd */  argument
408 	volatile struct	eri_tmd	*tcurp;	/* nxt tmd to reclaim(used) */  argument
413 	ddi_dma_handle_t	eri_dvmarh;	/* dvma recv handle */  argument
419 	ddi_dma_handle_t	ndmarh[ERI_RMDMAX];
421 	ddi_dma_handle_t	tbuf_handle;
422 	ddi_acc_handle_t	tbuf_acch;
423 	caddr_t			tbuf_kaddr;
424 	uint32_t		tbuf_ioaddr;
426 	int			rcv_handle_cnt;
428 	int			rx_reset_issued;
429 	int			tx_reset_issued;
430 	int			rxmac_reset_issued;
431 	int			txmac_reset_issued;
433 	int			global_reset_issued;
434 	uint32_t		rpending_mask;
435 	int			rmdmax_mask;
436 	int			init_macregs;
438 	int			phyad;	/* addr of the PHY in use */
439 	int			xcvr;  /* current PHY in use */
441 	int			openloop_autoneg;
443 	uint16_t		mif_config;
444 	uint16_t		mif_mask;
446 	uint32_t		tx_config;
448 	uint32_t		vendor_id;	/* Vendor ID	*/
449 	uint16_t		device_id;	/* Device Model	*/
450 	uint16_t		device_rev;	/* Device Rev.	*/
451 	uint32_t		phy_address;	/* PHY Address	*/
452 	uint32_t		xcvr_status;	/* xcvr_status	*/
453 	uint32_t		xcvr_state;	/* xcvr_state	*/
454 	uint32_t		bringup_mode;	/* Bringup Mode	*/
455 	uint32_t		speed;		/* Current speed */
456 	uint32_t		duplex;		/* Xcvr Duplex	*/
457 	uint32_t		capability;	/* Xcvr Capability */
459 	uint16_t		mii_control;
483 	timeout_id_t		timerid;	/* timer id for links */  argument
484 	int			linkup_cnt;
486 	uint16_t		aner;	/* MII ANER register */
488 	int			linkup;		/* selected link status */
489 	int			linkup_state; /* link bringup state */
490 	int			linkup_changed; /* link bringup state */
492 	int			linkcheck;
493 	caddr_t			g_nd;	/* head of the */
496 	ddi_device_acc_attr_t	dev_attr;
497 	ddi_iblock_cookie_t	cookie;	/* interrupt cookie */
498 	ddi_acc_handle_t	globregh;   /* ERI global regs */
499 	ddi_acc_handle_t	etxregh;    /* ERI ETX regs */
500 	ddi_acc_handle_t	erxregh;    /* ERI ERX regs */
501 	ddi_acc_handle_t	bmacregh;   /* BigMAC registers */
502 	ddi_acc_handle_t	mifregh;    /* ERI transceiver */
503 	ddi_acc_handle_t	pcsregh;    /* ERI PCS regs */
505 	ddi_acc_handle_t	sw_reset_regh;	/* ERI Reset Reg */
507 	ddi_dma_cookie_t	md_c;	/* trmd dma cookie */
508 	ddi_acc_handle_t	mdm_h;	/* trmd memory handle */
509 	ddi_dma_handle_t	md_h;	/* trmdp dma handle */
511 	ddi_acc_handle_t	pci_config_handle; /* ERI PCI config */
538 	struct		erisave erisave;  argument
555  * array of words defined by erip->ladrf, converting a bit (0-255) into  argument