Lines Matching refs:UINT32
172 UINT32 MfgId;
241 UINT32 EnterpriseId;
299 UINT32 Length;
300 UINT32 VendorId;
301 UINT32 SubvendorId;
306 UINT32 SharedInfoLength;
318 UINT32 MmioBaseLow;
319 UINT32 MmioBaseHigh;
320 UINT32 GsiInterrupt;
327 UINT32 MaxBlockSize;
337 UINT32 Length;
340 UINT32 Uid;
374 UINT32 InfoOffset;
375 UINT32 InfoCount;
382 UINT32 InfoOffset;
383 UINT32 InfoCount;
595 UINT32 Reserved;
597 UINT32 ProximityDomain;
627 UINT32 Id; /* Hardware ID of event timer block */
774 UINT32 NodeCount;
775 UINT32 NodeOffset;
776 UINT32 Reserved;
789 UINT32 Reserved;
790 UINT32 MappingCount;
791 UINT32 MappingOffset;
810 UINT32 InputBase; /* Lowest value in input range */
811 UINT32 IdCount; /* Number of IDs */
812 UINT32 OutputBase; /* Lowest value in output range */
813 UINT32 OutputReference; /* A reference to the output node */
814 UINT32 Flags;
825 UINT32 CacheCoherency;
855 UINT32 ItsCount;
856 UINT32 Identifiers[1]; /* GIC ITS identifier arrary */
863 UINT32 NodeFlags;
874 UINT32 AtsAttribute;
875 UINT32 PciSegmentNumber;
889 UINT32 Model;
890 UINT32 Flags;
891 UINT32 GlobalInterruptOffset;
892 UINT32 ContextInterruptCount;
893 UINT32 ContextInterruptOffset;
894 UINT32 PmuInterruptCount;
895 UINT32 PmuInterruptOffset;
916 UINT32 Flags;
917 UINT32 Reserved;
919 UINT32 Model; /* O: generic SMMUv3 */
920 UINT32 EventGsiv;
921 UINT32 PriGsiv;
922 UINT32 GerrGsiv;
923 UINT32 SyncGsiv;
946 UINT32 Info; /* Common virtualization info */
1008 UINT32 Reserved;
1093 UINT32 ExtendedData;
1150 UINT32 Type; /* Subtable type */
1151 UINT32 Length; /* Subtable length */
1154 UINT32 Flags;
1181 UINT32 Residency;
1182 UINT32 Latency;
1214 UINT32 Reserved;
1238 UINT32 GlobalInterrupt;
1288 UINT32 Frequency;
1289 UINT32 Irq;
1330 UINT32 Interrupt;
1342 UINT32 PciFlags;
1344 UINT32 Reserved2;
1376 UINT32 Interrupt;
1430 UINT32 MinimumLogLength; /* Minimum length for the event log area */
1445 UINT32 GlobalInterrupt;
1447 UINT32 Reserved3;
1486 UINT32 StartMethod;
1542 UINT32 Irq;
1559 UINT32 Flags;
1582 UINT32 HeaderLength; /* Watchdog Header Length */
1588 UINT32 TimerPeriod; /* Period of one timer count (msec) */
1589 UINT32 MaxCount; /* Maximum counter value supported */
1590 UINT32 MinCount; /* Minimum counter value */
1593 UINT32 Entries; /* Number of watchdog entries that follow */
1611 UINT32 Value; /* Value used with Read/Write register */
1612 UINT32 Mask; /* Bitmask required for this register instruction */