Lines Matching refs:cp_eax
375 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20)
376 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16)
377 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12)
378 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8)
379 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0)
380 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4)
402 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26)
403 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14)
404 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9)
405 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8)
406 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5)
407 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0)
460 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0)
529 cp->cp_eax &= 0x03fffffff; in platform_cpuid_mangle()
642 cp.cp_eax = 0x1; in determine_platform()
645 cp.cp_eax = 0x40000000; in determine_platform()
691 cp.cp_eax = base; in determine_platform()
698 cp.cp_eax >= (base + 2)) { in determine_platform()
862 cp->cp_eax = 0x8000001e; in cpuid_amd_getids()
971 cp->cp_eax = 0; in cpuid_pass1()
993 cp->cp_eax = 1; in cpuid_pass1()
1076 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; in cpuid_pass1()
1242 ecp->cp_eax = 7; in cpuid_pass1()
1481 cp->cp_eax = 0x80000000; in cpuid_pass1()
1496 cp->cp_eax = 0x80000001; in cpuid_pass1()
1602 cp->cp_eax = 4; in cpuid_pass1()
1612 cp->cp_eax = 0x80000008; in cpuid_pass1()
1620 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); in cpuid_pass1()
1621 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); in cpuid_pass1()
1637 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; in cpuid_pass1()
1669 cp->cp_eax = 0x80000007; in cpuid_pass1()
1773 cp->cp_eax = n; in cpuid_pass2()
1807 BITX(cp->cp_eax, 7, 0); in cpuid_pass2()
1821 if (BITX(cp->cp_eax, 31, 31) == 0) { in cpuid_pass2()
1822 uint8_t *p = (void *)&cp->cp_eax; in cpuid_pass2()
1896 cp->cp_eax = 0xB; in cpuid_pass2()
1916 cp->cp_eax = 0xB; in cpuid_pass2()
1924 coreid_shift = BITX(cp->cp_eax, 4, 0); in cpuid_pass2()
1928 chipid_shift = BITX(cp->cp_eax, 4, 0); in cpuid_pass2()
1955 cp->cp_eax = 0xD; in cpuid_pass2()
1963 if ((cp->cp_eax & XFEATURE_LEGACY_FP) == 0 || in cpuid_pass2()
1964 (cp->cp_eax & XFEATURE_SSE) == 0) { in cpuid_pass2()
1968 cpi->cpi_xsave.xsav_hw_features_low = cp->cp_eax; in cpuid_pass2()
1977 cp->cp_eax = 0xD; in cpuid_pass2()
1984 cp->cp_eax != CPUID_LEAFD_2_YMM_SIZE) { in cpuid_pass2()
1988 cpi->cpi_xsave.ymm_size = cp->cp_eax; in cpuid_pass2()
2075 cp->cp_eax = 0x80000000 + n; in cpuid_pass2()
2085 *iptr++ = cp->cp_eax; in cpuid_pass2()
2102 cp->cp_eax = 0; in cpuid_pass2()
2119 cp->cp_eax = cp->cp_ebx = 0; in cpuid_pass2()
2208 tmp = (cp->cp_eax >> (8 * i)) & 0xff; in intel_cpubrand()
2548 cp->cp_eax = 4; in cpuid_pass3()
2584 cp->cp_eax = 4; in cpuid_pass3()
2926 cp.cp_eax = 0x80860001; in cpuid_pass4()
2965 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) in cpuid_insn()
2966 xcp = &cpi->cpi_std[cp->cp_eax]; in cpuid_insn()
2967 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && in cpuid_insn()
2968 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) in cpuid_insn()
2969 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; in cpuid_insn()
2978 cp->cp_eax = xcp->cp_eax; in cpuid_insn()
2982 return (cp->cp_eax); in cpuid_insn()
3060 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, in cpuid_getidstr()
3064 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, in cpuid_getidstr()
3136 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); in cpuid_getsig()
3329 if ((cp->cp_eax & 0xffff0000) == 0) in cpuid_get_dtlb_nent()
3330 dtlb_nent = cp->cp_eax & 0x0000ffff; in cpuid_get_dtlb_nent()
3332 dtlb_nent = BITX(cp->cp_eax, 27, 16); in cpuid_get_dtlb_nent()
3355 dtlb_nent = BITX(cp->cp_eax, 23, 16); in cpuid_get_dtlb_nent()
3389 eax = cpi->cpi_std[1].cp_eax; in cpuid_opteron_erratum()
3554 regs.cp_eax = 0x80000007; in cpuid_opteron_erratum()
4077 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); in amd_cache_info()
4079 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); in amd_cache_info()
4134 if (BITX(cp->cp_eax, 31, 16) == 0) in amd_cache_info()
4136 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); in amd_cache_info()
4139 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); in amd_cache_info()
4141 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); in amd_cache_info()
4148 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); in amd_cache_info()
4151 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); in amd_cache_info()
4153 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); in amd_cache_info()
4318 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); in cpuid_set_cpu_properties()
4652 regs.cp_eax = 0x80000007; in cpuid_deep_cstates_supported()
4739 regs.cp_eax = 6; in cpuid_arat_supported()
4741 return (regs.cp_eax & CPUID_CSTATE_ARAT); in cpuid_arat_supported()
4773 regs.cp_eax = 0x6; in cpuid_iepb_supported()
4799 regs.cp_eax = 1; in cpuid_deadline_tsc_supported()
4849 cp->cp_eax = 0; in cpuid_get_ext_topo()
4852 cp->cp_eax = 0xB; in cpuid_get_ext_topo()
4868 cp->cp_eax = 0xB; in cpuid_get_ext_topo()
4880 coreid_shift = BITX(cp->cp_eax, 4, 0); in cpuid_get_ext_topo()
4887 chipid_shift = BITX(cp->cp_eax, 4, 0); in cpuid_get_ext_topo()