Lines Matching refs:pnum
278 int pnum = port->p_port; in yge_mii_readreg() local
281 GMAC_WRITE_2(dev, pnum, GM_SMI_CTRL, in yge_mii_readreg()
286 val = GMAC_READ_2(dev, pnum, GM_SMI_CTRL); in yge_mii_readreg()
288 val = GMAC_READ_2(dev, pnum, GM_SMI_DATA); in yge_mii_readreg()
307 int pnum = port->p_port; in yge_mii_writereg() local
309 GMAC_WRITE_2(dev, pnum, GM_SMI_DATA, val); in yge_mii_writereg()
310 GMAC_WRITE_2(dev, pnum, GM_SMI_CTRL, in yge_mii_writereg()
315 if ((GMAC_READ_2(dev, pnum, GM_SMI_CTRL) & GM_SMI_CT_BUSY) == 0) in yge_mii_writereg()
452 int pnum; in yge_setrxfilt() local
455 pnum = port->p_port; in yge_setrxfilt()
464 GMAC_WRITE_2(dev, pnum, GM_SRC_ADDR_1L + i * 4, in yge_setrxfilt()
468 GMAC_WRITE_2(dev, pnum, GM_SRC_ADDR_2L + i * 4, in yge_setrxfilt()
473 mode = GMAC_READ_2(dev, pnum, GM_RX_CTRL); in yge_setrxfilt()
480 GMAC_WRITE_2(dev, pnum, GM_MC_ADDR_H1, mchash[0] & 0xffff); in yge_setrxfilt()
481 GMAC_WRITE_2(dev, pnum, GM_MC_ADDR_H2, (mchash[0] >> 16) & 0xffff); in yge_setrxfilt()
482 GMAC_WRITE_2(dev, pnum, GM_MC_ADDR_H3, mchash[1] & 0xffff); in yge_setrxfilt()
483 GMAC_WRITE_2(dev, pnum, GM_MC_ADDR_H4, (mchash[1] >> 16) & 0xffff); in yge_setrxfilt()
485 GMAC_WRITE_2(dev, pnum, GM_RX_CTRL, mode); in yge_setrxfilt()
2023 int pnum = port->p_port; in yge_intr_gmac() local
2027 status = CSR_READ_1(dev, MR_ADDR(pnum, GMAC_IRQ_SRC)); in yge_intr_gmac()
2031 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_CLI_RX_FO); in yge_intr_gmac()
2037 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_CLI_TX_FU); in yge_intr_gmac()
2178 int cons, idx, len, pnum; in yge_handle_events() local
2205 pnum = ((control >> 16) & 0x01); in yge_handle_events()
2206 port = dev->d_port[pnum]; in yge_handle_events()
2217 if (heads[pnum] == NULL) in yge_handle_events()
2218 heads[pnum] = mp; in yge_handle_events()
2220 tails[pnum]->b_next = mp; in yge_handle_events()
2221 tails[pnum] = mp; in yge_handle_events()
2224 rxprogs[pnum]++; in yge_handle_events()
2245 if (rxprogs[pnum] > dev->d_process_limit) { in yge_handle_events()
2379 int pnum = port->p_port; in yge_set_tx_stfwd() local
2387 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), in yge_set_tx_stfwd()
2390 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), in yge_set_tx_stfwd()
2397 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_AE_THR), in yge_set_tx_stfwd()
2400 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), in yge_set_tx_stfwd()
2404 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), in yge_set_tx_stfwd()
2416 int32_t pnum; in yge_start_port() local
2421 pnum = port->p_port; in yge_start_port()
2438 CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_RST_SET); in yge_start_port()
2439 CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_RST_CLR); in yge_start_port()
2440 CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_F_LOOPB_OFF); in yge_start_port()
2442 CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), in yge_start_port()
2449 GMAC_WRITE_2(dev, pnum, GM_GP_CTRL, 0); in yge_start_port()
2452 (void) CSR_READ_1(dev, MR_ADDR(pnum, GMAC_IRQ_SRC)); in yge_start_port()
2458 GMAC_WRITE_2(dev, pnum, GM_RX_CTRL, GM_RXCR_CRC_DIS); in yge_start_port()
2461 GMAC_WRITE_2(dev, pnum, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); in yge_start_port()
2464 GMAC_WRITE_2(dev, pnum, GM_TX_FLOW_CTRL, 0xffff); in yge_start_port()
2467 GMAC_WRITE_2(dev, pnum, GM_TX_PARAM, in yge_start_port()
2476 GMAC_WRITE_2(dev, pnum, GM_SERIAL_MODE, gmac); in yge_start_port()
2479 GMAC_WRITE_2(dev, pnum, GM_TX_IRQ_MSK, 0); in yge_start_port()
2480 GMAC_WRITE_2(dev, pnum, GM_RX_IRQ_MSK, 0); in yge_start_port()
2481 GMAC_WRITE_2(dev, pnum, GM_TR_IRQ_MSK, 0); in yge_start_port()
2484 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_SET); in yge_start_port()
2485 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_CLR); in yge_start_port()
2490 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), reg); in yge_start_port()
2496 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); in yge_start_port()
2508 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_FL_THR), reg); in yge_start_port()
2511 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_SET); in yge_start_port()
2512 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_CLR); in yge_start_port()
2513 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_OPER_ON); in yge_start_port()
2516 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF); in yge_start_port()
2517 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF); in yge_start_port()
2523 CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_LP_THR), in yge_start_port()
2525 CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_UP_THR), in yge_start_port()
2528 CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_LP_THR), in yge_start_port()
2530 CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_UP_THR), in yge_start_port()
2540 reg = CSR_READ_4(dev, MR_ADDR(pnum, TX_GMF_EA)); in yge_start_port()
2542 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_EA), reg); in yge_start_port()
2549 CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL), in yge_start_port()
2552 CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL), TXA_ENA_ARB); in yge_start_port()
2620 gmac = GMAC_READ_2(dev, pnum, GM_GP_CTRL); in yge_start_port()
2624 (void) GMAC_READ_2(dev, pnum, GM_GP_CTRL); in yge_start_port()
2635 int pnum; in yge_set_rambuffer() local
2640 pnum = port->p_port; in yge_set_rambuffer()
2649 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_START), dev->d_rxqstart[pnum] / 8); in yge_set_rambuffer()
2650 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_END), dev->d_rxqend[pnum] / 8); in yge_set_rambuffer()
2651 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_WP), dev->d_rxqstart[pnum] / 8); in yge_set_rambuffer()
2652 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_RP), dev->d_rxqstart[pnum] / 8); in yge_set_rambuffer()
2655 (dev->d_rxqend[pnum] + 1 - dev->d_rxqstart[pnum] - RB_ULPP) / 8; in yge_set_rambuffer()
2657 (dev->d_rxqend[pnum] + 1 - dev->d_rxqstart[pnum] - RB_LLPP_B) / 8; in yge_set_rambuffer()
2671 CSR_WRITE_4(dev, RB_ADDR(txq, RB_START), dev->d_txqstart[pnum] / 8); in yge_set_rambuffer()
2672 CSR_WRITE_4(dev, RB_ADDR(txq, RB_END), dev->d_txqend[pnum] / 8); in yge_set_rambuffer()
2673 CSR_WRITE_4(dev, RB_ADDR(txq, RB_WP), dev->d_txqstart[pnum] / 8); in yge_set_rambuffer()
2674 CSR_WRITE_4(dev, RB_ADDR(txq, RB_RP), dev->d_txqstart[pnum] / 8); in yge_set_rambuffer()
2708 int pnum = port->p_port; in yge_stop_port() local
2722 if (pnum == YGE_PORT_A) { in yge_stop_port()
2735 val = GMAC_READ_2(dev, pnum, GM_GP_CTRL); in yge_stop_port()
2737 GMAC_WRITE_2(dev, pnum, GM_GP_CTRL, val); in yge_stop_port()
2739 (void) GMAC_READ_2(dev, pnum, GM_GP_CTRL); in yge_stop_port()
2762 CSR_WRITE_1(dev, MR_ADDR(pnum, GMAC_IRQ_MSK), 0); in yge_stop_port()
2765 CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL), TXA_DIS_ARB); in yge_stop_port()
2778 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_SET); in yge_stop_port()
2780 CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_PAUSE_OFF); in yge_stop_port()
2812 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_SET); in yge_stop_port()
2832 int32_t pnum; in yge_stats_clear() local
2834 pnum = port->p_port; in yge_stats_clear()
2838 gmac = GMAC_READ_2(dev, pnum, GM_PHY_ADDR); in yge_stats_clear()
2839 GMAC_WRITE_2(dev, pnum, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); in yge_stats_clear()
2842 (void) YGE_READ_MIB32(pnum, i); in yge_stats_clear()
2845 GMAC_WRITE_2(dev, pnum, GM_PHY_ADDR, gmac); in yge_stats_clear()
2854 int32_t pnum; in yge_stats_update() local
2857 pnum = port->p_port; in yge_stats_update()
2864 gmac = GMAC_READ_2(dev, pnum, GM_PHY_ADDR); in yge_stats_update()
2865 GMAC_WRITE_2(dev, pnum, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); in yge_stats_update()
2868 stats->rx_ucast_frames += YGE_READ_MIB32(pnum, GM_RXF_UC_OK); in yge_stats_update()
2869 stats->rx_bcast_frames += YGE_READ_MIB32(pnum, GM_RXF_BC_OK); in yge_stats_update()
2870 stats->rx_pause_frames += YGE_READ_MIB32(pnum, GM_RXF_MPAUSE); in yge_stats_update()
2871 stats->rx_mcast_frames += YGE_READ_MIB32(pnum, GM_RXF_MC_OK); in yge_stats_update()
2872 stats->rx_crc_errs += YGE_READ_MIB32(pnum, GM_RXF_FCS_ERR); in yge_stats_update()
2873 (void) YGE_READ_MIB32(pnum, GM_RXF_SPARE1); in yge_stats_update()
2874 stats->rx_good_octets += YGE_READ_MIB64(pnum, GM_RXO_OK_LO); in yge_stats_update()
2875 stats->rx_bad_octets += YGE_READ_MIB64(pnum, GM_RXO_ERR_LO); in yge_stats_update()
2876 stats->rx_runts += YGE_READ_MIB32(pnum, GM_RXF_SHT); in yge_stats_update()
2877 stats->rx_runt_errs += YGE_READ_MIB32(pnum, GM_RXE_FRAG); in yge_stats_update()
2878 stats->rx_pkts_64 += YGE_READ_MIB32(pnum, GM_RXF_64B); in yge_stats_update()
2879 stats->rx_pkts_65_127 += YGE_READ_MIB32(pnum, GM_RXF_127B); in yge_stats_update()
2880 stats->rx_pkts_128_255 += YGE_READ_MIB32(pnum, GM_RXF_255B); in yge_stats_update()
2881 stats->rx_pkts_256_511 += YGE_READ_MIB32(pnum, GM_RXF_511B); in yge_stats_update()
2882 stats->rx_pkts_512_1023 += YGE_READ_MIB32(pnum, GM_RXF_1023B); in yge_stats_update()
2883 stats->rx_pkts_1024_1518 += YGE_READ_MIB32(pnum, GM_RXF_1518B); in yge_stats_update()
2884 stats->rx_pkts_1519_max += YGE_READ_MIB32(pnum, GM_RXF_MAX_SZ); in yge_stats_update()
2885 stats->rx_pkts_too_long += YGE_READ_MIB32(pnum, GM_RXF_LNG_ERR); in yge_stats_update()
2886 stats->rx_pkts_jabbers += YGE_READ_MIB32(pnum, GM_RXF_JAB_PKT); in yge_stats_update()
2887 (void) YGE_READ_MIB32(pnum, GM_RXF_SPARE2); in yge_stats_update()
2888 stats->rx_fifo_oflows += YGE_READ_MIB32(pnum, GM_RXE_FIFO_OV); in yge_stats_update()
2889 (void) YGE_READ_MIB32(pnum, GM_RXF_SPARE3); in yge_stats_update()
2892 stats->tx_ucast_frames += YGE_READ_MIB32(pnum, GM_TXF_UC_OK); in yge_stats_update()
2893 stats->tx_bcast_frames += YGE_READ_MIB32(pnum, GM_TXF_BC_OK); in yge_stats_update()
2894 stats->tx_pause_frames += YGE_READ_MIB32(pnum, GM_TXF_MPAUSE); in yge_stats_update()
2895 stats->tx_mcast_frames += YGE_READ_MIB32(pnum, GM_TXF_MC_OK); in yge_stats_update()
2896 stats->tx_octets += YGE_READ_MIB64(pnum, GM_TXO_OK_LO); in yge_stats_update()
2897 stats->tx_pkts_64 += YGE_READ_MIB32(pnum, GM_TXF_64B); in yge_stats_update()
2898 stats->tx_pkts_65_127 += YGE_READ_MIB32(pnum, GM_TXF_127B); in yge_stats_update()
2899 stats->tx_pkts_128_255 += YGE_READ_MIB32(pnum, GM_TXF_255B); in yge_stats_update()
2900 stats->tx_pkts_256_511 += YGE_READ_MIB32(pnum, GM_TXF_511B); in yge_stats_update()
2901 stats->tx_pkts_512_1023 += YGE_READ_MIB32(pnum, GM_TXF_1023B); in yge_stats_update()
2902 stats->tx_pkts_1024_1518 += YGE_READ_MIB32(pnum, GM_TXF_1518B); in yge_stats_update()
2903 stats->tx_pkts_1519_max += YGE_READ_MIB32(pnum, GM_TXF_MAX_SZ); in yge_stats_update()
2904 (void) YGE_READ_MIB32(pnum, GM_TXF_SPARE1); in yge_stats_update()
2905 stats->tx_colls += YGE_READ_MIB32(pnum, GM_TXF_COL); in yge_stats_update()
2906 stats->tx_late_colls += YGE_READ_MIB32(pnum, GM_TXF_LAT_COL); in yge_stats_update()
2907 stats->tx_excess_colls += YGE_READ_MIB32(pnum, GM_TXF_ABO_COL); in yge_stats_update()
2908 stats->tx_multi_colls += YGE_READ_MIB32(pnum, GM_TXF_MUL_COL); in yge_stats_update()
2909 stats->tx_single_colls += YGE_READ_MIB32(pnum, GM_TXF_SNG_COL); in yge_stats_update()
2910 stats->tx_underflows += YGE_READ_MIB32(pnum, GM_TXE_FIFO_UR); in yge_stats_update()
2913 GMAC_WRITE_2(dev, pnum, GM_PHY_ADDR, gmac); in yge_stats_update()