Lines Matching refs:sc
471 iwp_sc_t *sc; in iwp_attach() local
487 sc = ddi_get_soft_state(iwp_soft_state_p, in iwp_attach()
489 ASSERT(sc != NULL); in iwp_attach()
491 if (sc->sc_flags & IWP_F_RUNNING) { in iwp_attach()
492 (void) iwp_init(sc); in iwp_attach()
495 atomic_and_32(&sc->sc_flags, ~IWP_F_SUSPEND); in iwp_attach()
512 sc = ddi_get_soft_state(iwp_soft_state_p, instance); in iwp_attach()
513 ASSERT(sc != NULL); in iwp_attach()
515 sc->sc_dip = dip; in iwp_attach()
520 err = ddi_regs_map_setup(dip, 0, &sc->sc_cfg_base, 0, 0, in iwp_attach()
521 &iwp_reg_accattr, &sc->sc_cfg_handle); in iwp_attach()
528 sc->sc_dev_id = ddi_get16(sc->sc_cfg_handle, in iwp_attach()
529 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_DEVID)); in iwp_attach()
530 if ((sc->sc_dev_id != 0x422B) && in iwp_attach()
531 (sc->sc_dev_id != 0x422C) && in iwp_attach()
532 (sc->sc_dev_id != 0x4238) && in iwp_attach()
533 (sc->sc_dev_id != 0x4239) && in iwp_attach()
534 (sc->sc_dev_id != 0x008d) && in iwp_attach()
535 (sc->sc_dev_id != 0x008e)) { in iwp_attach()
541 iwp_set_chip_param(sc); in iwp_attach()
543 sc->sc_rev = ddi_get8(sc->sc_cfg_handle, in iwp_attach()
544 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_REVID)); in iwp_attach()
549 ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base + in iwp_attach()
555 sc->sc_clsz = ddi_get16(sc->sc_cfg_handle, in iwp_attach()
556 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ)); in iwp_attach()
557 if (!sc->sc_clsz) { in iwp_attach()
558 sc->sc_clsz = 16; in iwp_attach()
560 sc->sc_clsz = (sc->sc_clsz << 2); in iwp_attach()
562 sc->sc_dmabuf_sz = roundup(0x1000 + sizeof (struct ieee80211_frame) + in iwp_attach()
565 IEEE80211_WEP_CRCLEN), sc->sc_clsz); in iwp_attach()
570 err = ddi_regs_map_setup(dip, 1, &sc->sc_base, in iwp_attach()
571 0, 0, &iwp_reg_accattr, &sc->sc_handle); in iwp_attach()
581 sc->sc_hw_rev = IWP_READ(sc, CSR_HW_REV); in iwp_attach()
597 sc->sc_intr_htable = kmem_zalloc(sizeof (ddi_intr_handle_t), KM_SLEEP); in iwp_attach()
599 err = ddi_intr_alloc(dip, sc->sc_intr_htable, DDI_INTR_TYPE_FIXED, 0, in iwp_attach()
607 err = ddi_intr_get_pri(sc->sc_intr_htable[0], &sc->sc_intr_pri); in iwp_attach()
614 mutex_init(&sc->sc_glock, NULL, MUTEX_DRIVER, in iwp_attach()
615 DDI_INTR_PRI(sc->sc_intr_pri)); in iwp_attach()
616 mutex_init(&sc->sc_tx_lock, NULL, MUTEX_DRIVER, in iwp_attach()
617 DDI_INTR_PRI(sc->sc_intr_pri)); in iwp_attach()
618 mutex_init(&sc->sc_mt_lock, NULL, MUTEX_DRIVER, in iwp_attach()
619 DDI_INTR_PRI(sc->sc_intr_pri)); in iwp_attach()
621 cv_init(&sc->sc_cmd_cv, NULL, CV_DRIVER, NULL); in iwp_attach()
622 cv_init(&sc->sc_put_seg_cv, NULL, CV_DRIVER, NULL); in iwp_attach()
623 cv_init(&sc->sc_ucode_cv, NULL, CV_DRIVER, NULL); in iwp_attach()
628 cv_init(&sc->sc_mt_cv, NULL, CV_DRIVER, NULL); in iwp_attach()
629 sc->sc_mf_thread = NULL; in iwp_attach()
630 sc->sc_mf_thread_switch = 0; in iwp_attach()
635 err = iwp_alloc_shared(sc); in iwp_attach()
642 (void) memset(sc->sc_shared, 0, sizeof (iwp_shared_t)); in iwp_attach()
647 err = iwp_alloc_kw(sc); in iwp_attach()
657 err = iwp_preinit(sc); in iwp_attach()
667 err = iwp_eep_load(sc); in iwp_attach()
677 sc->sc_eep_calib = (struct iwp_eep_calibration *) in iwp_attach()
678 iwp_eep_addr_trans(sc, EEP_CALIBRATION); in iwp_attach()
680 err = iwp_eep_ver_chk(sc); in iwp_attach()
688 iwp_get_mac_from_eep(sc); in iwp_attach()
694 err = iwp_ring_init(sc); in iwp_attach()
701 sc->sc_hdr = (iwp_firmware_hdr_t *)iwp_fw_bin; in iwp_attach()
706 err = iwp_alloc_fw_dma(sc); in iwp_attach()
717 ic = &sc->sc_ic; in iwp_attach()
766 iwp_overwrite_ic_default(sc); in iwp_attach()
778 err = ddi_intr_add_softint(dip, &sc->sc_soft_hdl, DDI_INTR_SOFTPRI_MAX, in iwp_attach()
779 iwp_rx_softintr, (caddr_t)sc); in iwp_attach()
786 err = ddi_intr_add_handler(sc->sc_intr_htable[0], iwp_intr, in iwp_attach()
787 (caddr_t)sc, NULL); in iwp_attach()
794 err = ddi_intr_enable(sc->sc_intr_htable[0]); in iwp_attach()
819 macp->m_driver = sc; in iwp_attach()
859 sc->sc_mf_thread_switch = 1; in iwp_attach()
860 if (NULL == sc->sc_mf_thread) { in iwp_attach()
861 sc->sc_mf_thread = thread_create((caddr_t)NULL, 0, in iwp_attach()
862 iwp_thread, sc, 0, &p0, TS_RUN, minclsyspri); in iwp_attach()
865 atomic_or_32(&sc->sc_flags, IWP_F_ATTACHED); in iwp_attach()
870 (void) ddi_intr_disable(sc->sc_intr_htable[0]); in iwp_attach()
872 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]); in iwp_attach()
874 (void) ddi_intr_remove_softint(sc->sc_soft_hdl); in iwp_attach()
875 sc->sc_soft_hdl = NULL; in iwp_attach()
879 iwp_free_fw_dma(sc); in iwp_attach()
881 iwp_ring_free(sc); in iwp_attach()
883 iwp_free_kw(sc); in iwp_attach()
885 iwp_free_shared(sc); in iwp_attach()
887 iwp_destroy_locks(sc); in iwp_attach()
889 (void) ddi_intr_free(sc->sc_intr_htable[0]); in iwp_attach()
891 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t)); in iwp_attach()
893 ddi_regs_map_free(&sc->sc_handle); in iwp_attach()
895 ddi_regs_map_free(&sc->sc_cfg_handle); in iwp_attach()
905 iwp_sc_t *sc; in iwp_detach() local
909 sc = ddi_get_soft_state(iwp_soft_state_p, ddi_get_instance(dip)); in iwp_detach()
910 ASSERT(sc != NULL); in iwp_detach()
911 ic = &sc->sc_ic; in iwp_detach()
917 atomic_and_32(&sc->sc_flags, ~IWP_F_HW_ERR_RECOVER); in iwp_detach()
918 atomic_and_32(&sc->sc_flags, ~IWP_F_RATE_AUTO_CTL); in iwp_detach()
920 atomic_or_32(&sc->sc_flags, IWP_F_SUSPEND); in iwp_detach()
922 if (sc->sc_flags & IWP_F_RUNNING) { in iwp_detach()
923 iwp_stop(sc); in iwp_detach()
935 if (!(sc->sc_flags & IWP_F_ATTACHED)) { in iwp_detach()
942 sc->sc_mf_thread_switch = 0; in iwp_detach()
944 mutex_enter(&sc->sc_mt_lock); in iwp_detach()
945 while (sc->sc_mf_thread != NULL) { in iwp_detach()
946 if (cv_wait_sig(&sc->sc_mt_cv, &sc->sc_mt_lock) == 0) { in iwp_detach()
950 mutex_exit(&sc->sc_mt_lock); in iwp_detach()
952 err = mac_disable(sc->sc_ic.ic_mach); in iwp_detach()
960 iwp_stop(sc); in iwp_detach()
967 iwp_release_calib_buffer(sc); in iwp_detach()
972 (void) mac_unregister(sc->sc_ic.ic_mach); in iwp_detach()
974 mutex_enter(&sc->sc_glock); in iwp_detach()
975 iwp_free_fw_dma(sc); in iwp_detach()
976 iwp_ring_free(sc); in iwp_detach()
977 iwp_free_kw(sc); in iwp_detach()
978 iwp_free_shared(sc); in iwp_detach()
979 mutex_exit(&sc->sc_glock); in iwp_detach()
981 (void) ddi_intr_disable(sc->sc_intr_htable[0]); in iwp_detach()
982 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]); in iwp_detach()
983 (void) ddi_intr_free(sc->sc_intr_htable[0]); in iwp_detach()
984 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t)); in iwp_detach()
986 (void) ddi_intr_remove_softint(sc->sc_soft_hdl); in iwp_detach()
987 sc->sc_soft_hdl = NULL; in iwp_detach()
992 ieee80211_detach(&sc->sc_ic); in iwp_detach()
994 iwp_destroy_locks(sc); in iwp_detach()
996 ddi_regs_map_free(&sc->sc_handle); in iwp_detach()
997 ddi_regs_map_free(&sc->sc_cfg_handle); in iwp_detach()
1008 iwp_destroy_locks(iwp_sc_t *sc) in iwp_destroy_locks() argument
1010 cv_destroy(&sc->sc_mt_cv); in iwp_destroy_locks()
1011 cv_destroy(&sc->sc_cmd_cv); in iwp_destroy_locks()
1012 cv_destroy(&sc->sc_put_seg_cv); in iwp_destroy_locks()
1013 cv_destroy(&sc->sc_ucode_cv); in iwp_destroy_locks()
1014 mutex_destroy(&sc->sc_mt_lock); in iwp_destroy_locks()
1015 mutex_destroy(&sc->sc_tx_lock); in iwp_destroy_locks()
1016 mutex_destroy(&sc->sc_glock); in iwp_destroy_locks()
1023 iwp_alloc_dma_mem(iwp_sc_t *sc, size_t memsize, in iwp_alloc_dma_mem() argument
1033 err = ddi_dma_alloc_handle(sc->sc_dip, dma_attr_p, in iwp_alloc_dma_mem()
1100 iwp_alloc_fw_dma(iwp_sc_t *sc) in iwp_alloc_fw_dma() argument
1114 if (LE_32(sc->sc_hdr->init_textsz) > RTC_INST_SIZE) { in iwp_alloc_fw_dma()
1117 LE_32(sc->sc_hdr->init_textsz)); in iwp_alloc_fw_dma()
1122 if (LE_32(sc->sc_hdr->init_datasz) > RTC_DATA_SIZE) { in iwp_alloc_fw_dma()
1125 LE_32(sc->sc_hdr->init_datasz)); in iwp_alloc_fw_dma()
1130 if (LE_32(sc->sc_hdr->textsz) > RTC_INST_SIZE) { in iwp_alloc_fw_dma()
1133 LE_32(sc->sc_hdr->textsz)); in iwp_alloc_fw_dma()
1138 if (LE_32(sc->sc_hdr->datasz) > RTC_DATA_SIZE) { in iwp_alloc_fw_dma()
1141 LE_32(sc->sc_hdr->datasz)); in iwp_alloc_fw_dma()
1149 t = (char *)(sc->sc_hdr + 1); in iwp_alloc_fw_dma()
1150 err = iwp_alloc_dma_mem(sc, LE_32(sc->sc_hdr->textsz), in iwp_alloc_fw_dma()
1153 &sc->sc_dma_fw_text); in iwp_alloc_fw_dma()
1160 dma_p = &sc->sc_dma_fw_text; in iwp_alloc_fw_dma()
1167 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->textsz)); in iwp_alloc_fw_dma()
1172 t += LE_32(sc->sc_hdr->textsz); in iwp_alloc_fw_dma()
1173 err = iwp_alloc_dma_mem(sc, LE_32(sc->sc_hdr->datasz), in iwp_alloc_fw_dma()
1176 &sc->sc_dma_fw_data); in iwp_alloc_fw_dma()
1183 dma_p = &sc->sc_dma_fw_data; in iwp_alloc_fw_dma()
1190 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->datasz)); in iwp_alloc_fw_dma()
1192 err = iwp_alloc_dma_mem(sc, LE_32(sc->sc_hdr->datasz), in iwp_alloc_fw_dma()
1195 &sc->sc_dma_fw_data_bak); in iwp_alloc_fw_dma()
1202 dma_p = &sc->sc_dma_fw_data_bak; in iwp_alloc_fw_dma()
1210 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->datasz)); in iwp_alloc_fw_dma()
1215 t += LE_32(sc->sc_hdr->datasz); in iwp_alloc_fw_dma()
1216 err = iwp_alloc_dma_mem(sc, LE_32(sc->sc_hdr->init_textsz), in iwp_alloc_fw_dma()
1219 &sc->sc_dma_fw_init_text); in iwp_alloc_fw_dma()
1226 dma_p = &sc->sc_dma_fw_init_text; in iwp_alloc_fw_dma()
1234 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->init_textsz)); in iwp_alloc_fw_dma()
1239 t += LE_32(sc->sc_hdr->init_textsz); in iwp_alloc_fw_dma()
1240 err = iwp_alloc_dma_mem(sc, LE_32(sc->sc_hdr->init_datasz), in iwp_alloc_fw_dma()
1243 &sc->sc_dma_fw_init_data); in iwp_alloc_fw_dma()
1250 dma_p = &sc->sc_dma_fw_init_data; in iwp_alloc_fw_dma()
1258 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->init_datasz)); in iwp_alloc_fw_dma()
1260 sc->sc_boot = t + LE_32(sc->sc_hdr->init_datasz); in iwp_alloc_fw_dma()
1266 iwp_free_fw_dma(iwp_sc_t *sc) in iwp_free_fw_dma() argument
1268 iwp_free_dma_mem(&sc->sc_dma_fw_text); in iwp_free_fw_dma()
1269 iwp_free_dma_mem(&sc->sc_dma_fw_data); in iwp_free_fw_dma()
1270 iwp_free_dma_mem(&sc->sc_dma_fw_data_bak); in iwp_free_fw_dma()
1271 iwp_free_dma_mem(&sc->sc_dma_fw_init_text); in iwp_free_fw_dma()
1272 iwp_free_dma_mem(&sc->sc_dma_fw_init_data); in iwp_free_fw_dma()
1279 iwp_alloc_shared(iwp_sc_t *sc) in iwp_alloc_shared() argument
1289 err = iwp_alloc_dma_mem(sc, sizeof (iwp_shared_t), in iwp_alloc_shared()
1292 &sc->sc_dma_sh); in iwp_alloc_shared()
1297 sc->sc_shared = (iwp_shared_t *)sc->sc_dma_sh.mem_va; in iwp_alloc_shared()
1300 dma_p = &sc->sc_dma_sh; in iwp_alloc_shared()
1309 iwp_free_shared(sc); in iwp_alloc_shared()
1314 iwp_free_shared(iwp_sc_t *sc) in iwp_free_shared() argument
1316 iwp_free_dma_mem(&sc->sc_dma_sh); in iwp_free_shared()
1323 iwp_alloc_kw(iwp_sc_t *sc) in iwp_alloc_kw() argument
1333 err = iwp_alloc_dma_mem(sc, IWP_KW_SIZE, in iwp_alloc_kw()
1336 &sc->sc_dma_kw); in iwp_alloc_kw()
1342 dma_p = &sc->sc_dma_kw; in iwp_alloc_kw()
1351 iwp_free_kw(sc); in iwp_alloc_kw()
1356 iwp_free_kw(iwp_sc_t *sc) in iwp_free_kw() argument
1358 iwp_free_dma_mem(&sc->sc_dma_kw); in iwp_free_kw()
1365 iwp_alloc_rx_ring(iwp_sc_t *sc) in iwp_alloc_rx_ring() argument
1374 ring = &sc->sc_rxq; in iwp_alloc_rx_ring()
1380 err = iwp_alloc_dma_mem(sc, RX_QUEUE_SIZE * sizeof (uint32_t), in iwp_alloc_rx_ring()
1405 err = iwp_alloc_dma_mem(sc, sc->sc_dmabuf_sz, in iwp_alloc_rx_ring()
1437 iwp_free_rx_ring(sc); in iwp_alloc_rx_ring()
1445 iwp_reset_rx_ring(iwp_sc_t *sc) in iwp_reset_rx_ring() argument
1449 iwp_mac_access_enter(sc); in iwp_reset_rx_ring()
1450 IWP_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); in iwp_reset_rx_ring()
1452 if (IWP_READ(sc, FH_MEM_RSSR_RX_STATUS_REG) & (1 << 24)) { in iwp_reset_rx_ring()
1463 iwp_mac_access_exit(sc); in iwp_reset_rx_ring()
1465 sc->sc_rxq.cur = 0; in iwp_reset_rx_ring()
1469 iwp_free_rx_ring(iwp_sc_t *sc) in iwp_free_rx_ring() argument
1474 if (sc->sc_rxq.data[i].dma_data.dma_hdl) { in iwp_free_rx_ring()
1475 IWP_DMA_SYNC(sc->sc_rxq.data[i].dma_data, in iwp_free_rx_ring()
1479 iwp_free_dma_mem(&sc->sc_rxq.data[i].dma_data); in iwp_free_rx_ring()
1482 if (sc->sc_rxq.dma_desc.dma_hdl) { in iwp_free_rx_ring()
1483 IWP_DMA_SYNC(sc->sc_rxq.dma_desc, DDI_DMA_SYNC_FORDEV); in iwp_free_rx_ring()
1486 iwp_free_dma_mem(&sc->sc_rxq.dma_desc); in iwp_free_rx_ring()
1493 iwp_alloc_tx_ring(iwp_sc_t *sc, iwp_tx_ring_t *ring, in iwp_alloc_tx_ring() argument
1515 err = iwp_alloc_dma_mem(sc, in iwp_alloc_tx_ring()
1541 err = iwp_alloc_dma_mem(sc, in iwp_alloc_tx_ring()
1578 err = iwp_alloc_dma_mem(sc, sc->sc_dmabuf_sz, in iwp_alloc_tx_ring()
1617 iwp_reset_tx_ring(iwp_sc_t *sc, iwp_tx_ring_t *ring) in iwp_reset_tx_ring() argument
1622 iwp_mac_access_enter(sc); in iwp_reset_tx_ring()
1624 IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_CONFIG_REG(ring->qid), 0); in iwp_reset_tx_ring()
1626 if (IWP_READ(sc, IWP_FH_TSSR_TX_STATUS_REG) & in iwp_reset_tx_ring()
1641 iwp_mac_access_exit(sc); in iwp_reset_tx_ring()
1644 if (!(sc->sc_flags & IWP_F_QUIESCED)) { in iwp_reset_tx_ring()
1687 iwp_ring_init(iwp_sc_t *sc) in iwp_ring_init() argument
1696 err = iwp_alloc_tx_ring(sc, &sc->sc_txq[i], TFD_TX_CMD_SLOTS, in iwp_ring_init()
1706 err = iwp_alloc_tx_ring(sc, &sc->sc_txq[IWP_CMD_QUEUE_NUM], in iwp_ring_init()
1712 err = iwp_alloc_rx_ring(sc); in iwp_ring_init()
1722 iwp_ring_free(iwp_sc_t *sc) in iwp_ring_free() argument
1726 iwp_free_rx_ring(sc); in iwp_ring_free()
1728 iwp_free_tx_ring(&sc->sc_txq[i]); in iwp_ring_free()
1790 iwp_sc_t *sc; in iwp_newstate() local
1799 sc = (iwp_sc_t *)ic; in iwp_newstate()
1803 mutex_enter(&sc->sc_glock); in iwp_newstate()
1809 atomic_or_32(&sc->sc_flags, IWP_F_SCANNING); in iwp_newstate()
1810 iwp_set_led(sc, 2, 10, 2); in iwp_newstate()
1816 sc->sc_config.assoc_id = 0; in iwp_newstate()
1817 sc->sc_config.filter_flags &= in iwp_newstate()
1823 LE_16(sc->sc_config.chan), in iwp_newstate()
1824 LE_32(sc->sc_config.flags), in iwp_newstate()
1825 LE_32(sc->sc_config.filter_flags))); in iwp_newstate()
1827 err = iwp_cmd(sc, REPLY_RXON, &sc->sc_config, in iwp_newstate()
1832 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); in iwp_newstate()
1833 mutex_exit(&sc->sc_glock); in iwp_newstate()
1841 err = iwp_cmd(sc, REPLY_ADD_STA, &node, in iwp_newstate()
1846 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); in iwp_newstate()
1847 mutex_exit(&sc->sc_glock); in iwp_newstate()
1852 mutex_exit(&sc->sc_glock); in iwp_newstate()
1854 err = sc->sc_newstate(ic, nstate, arg); in iwp_newstate()
1855 mutex_enter(&sc->sc_glock); in iwp_newstate()
1856 if ((err != 0) || ((err = iwp_scan(sc)) != 0)) { in iwp_newstate()
1859 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); in iwp_newstate()
1862 mutex_exit(&sc->sc_glock); in iwp_newstate()
1867 sc->sc_clk = 0; in iwp_newstate()
1872 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); in iwp_newstate()
1878 sc->sc_config.assoc_id = 0; in iwp_newstate()
1879 sc->sc_config.filter_flags &= ~LE_32(RXON_FILTER_ASSOC_MSK); in iwp_newstate()
1886 if ((err = iwp_hw_set_before_auth(sc)) != 0) { in iwp_newstate()
1889 mutex_exit(&sc->sc_glock); in iwp_newstate()
1896 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); in iwp_newstate()
1901 iwp_set_led(sc, 2, 10, 10); in iwp_newstate()
1908 err = iwp_run_state_config(sc); in iwp_newstate()
1912 mutex_exit(&sc->sc_glock); in iwp_newstate()
1920 atomic_or_32(&sc->sc_flags, IWP_F_RATE_AUTO_CTL); in iwp_newstate()
1932 atomic_and_32(&sc->sc_flags, ~IWP_F_RATE_AUTO_CTL); in iwp_newstate()
1938 iwp_set_led(sc, 2, 0, 1); in iwp_newstate()
1943 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); in iwp_newstate()
1948 iwp_set_led(sc, 2, 1, 0); in iwp_newstate()
1953 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); in iwp_newstate()
1958 mutex_exit(&sc->sc_glock); in iwp_newstate()
1960 return (sc->sc_newstate(ic, nstate, arg)); in iwp_newstate()
1967 iwp_mac_access_enter(iwp_sc_t *sc) in iwp_mac_access_enter() argument
1972 tmp = IWP_READ(sc, CSR_GP_CNTRL); in iwp_mac_access_enter()
1973 IWP_WRITE(sc, CSR_GP_CNTRL, in iwp_mac_access_enter()
1978 if ((IWP_READ(sc, CSR_GP_CNTRL) & in iwp_mac_access_enter()
1999 iwp_mac_access_exit(iwp_sc_t *sc) in iwp_mac_access_exit() argument
2001 uint32_t tmp = IWP_READ(sc, CSR_GP_CNTRL); in iwp_mac_access_exit()
2002 IWP_WRITE(sc, CSR_GP_CNTRL, in iwp_mac_access_exit()
2020 iwp_mem_write(iwp_sc_t *sc, uint32_t addr, uint32_t data) in iwp_mem_write() argument
2022 IWP_WRITE(sc, HBUS_TARG_MEM_WADDR, addr); in iwp_mem_write()
2023 IWP_WRITE(sc, HBUS_TARG_MEM_WDAT, data); in iwp_mem_write()
2030 iwp_reg_read(iwp_sc_t *sc, uint32_t addr) in iwp_reg_read() argument
2032 IWP_WRITE(sc, HBUS_TARG_PRPH_RADDR, addr | (3 << 24)); in iwp_reg_read()
2033 return (IWP_READ(sc, HBUS_TARG_PRPH_RDAT)); in iwp_reg_read()
2040 iwp_reg_write(iwp_sc_t *sc, uint32_t addr, uint32_t data) in iwp_reg_write() argument
2042 IWP_WRITE(sc, HBUS_TARG_PRPH_WADDR, addr | (3 << 24)); in iwp_reg_write()
2043 IWP_WRITE(sc, HBUS_TARG_PRPH_WDAT, data); in iwp_reg_write()
2055 iwp_load_init_firmware(iwp_sc_t *sc) in iwp_load_init_firmware() argument
2060 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG); in iwp_load_init_firmware()
2065 err = iwp_put_seg_fw(sc, sc->sc_dma_fw_init_text.cookie.dmac_address, in iwp_load_init_firmware()
2066 RTC_INST_LOWER_BOUND, sc->sc_dma_fw_init_text.cookie.dmac_size); in iwp_load_init_firmware()
2076 while (!(sc->sc_flags & IWP_F_PUT_SEG)) { in iwp_load_init_firmware()
2077 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) { in iwp_load_init_firmware()
2082 if (!(sc->sc_flags & IWP_F_PUT_SEG)) { in iwp_load_init_firmware()
2088 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG); in iwp_load_init_firmware()
2093 err = iwp_put_seg_fw(sc, sc->sc_dma_fw_init_data.cookie.dmac_address, in iwp_load_init_firmware()
2094 RTC_DATA_LOWER_BOUND, sc->sc_dma_fw_init_data.cookie.dmac_size); in iwp_load_init_firmware()
2106 while (!(sc->sc_flags & IWP_F_PUT_SEG)) { in iwp_load_init_firmware()
2107 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) { in iwp_load_init_firmware()
2112 if (!(sc->sc_flags & IWP_F_PUT_SEG)) { in iwp_load_init_firmware()
2118 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG); in iwp_load_init_firmware()
2124 iwp_load_run_firmware(iwp_sc_t *sc) in iwp_load_run_firmware() argument
2129 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG); in iwp_load_run_firmware()
2134 err = iwp_put_seg_fw(sc, sc->sc_dma_fw_text.cookie.dmac_address, in iwp_load_run_firmware()
2135 RTC_INST_LOWER_BOUND, sc->sc_dma_fw_text.cookie.dmac_size); in iwp_load_run_firmware()
2145 while (!(sc->sc_flags & IWP_F_PUT_SEG)) { in iwp_load_run_firmware()
2146 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) { in iwp_load_run_firmware()
2151 if (!(sc->sc_flags & IWP_F_PUT_SEG)) { in iwp_load_run_firmware()
2157 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG); in iwp_load_run_firmware()
2162 err = iwp_put_seg_fw(sc, sc->sc_dma_fw_data_bak.cookie.dmac_address, in iwp_load_run_firmware()
2163 RTC_DATA_LOWER_BOUND, sc->sc_dma_fw_data.cookie.dmac_size); in iwp_load_run_firmware()
2175 while (!(sc->sc_flags & IWP_F_PUT_SEG)) { in iwp_load_run_firmware()
2176 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) { in iwp_load_run_firmware()
2181 if (!(sc->sc_flags & IWP_F_PUT_SEG)) { in iwp_load_run_firmware()
2187 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG); in iwp_load_run_firmware()
2197 iwp_rx_phy_intr(iwp_sc_t *sc, iwp_rx_desc_t *desc) in iwp_rx_phy_intr() argument
2200 sc->sc_rx_phy_res.flag = 1; in iwp_rx_phy_intr()
2202 (void) memcpy(sc->sc_rx_phy_res.buf, (uint8_t *)(desc + 1), in iwp_rx_phy_intr()
2211 iwp_rx_mpdu_intr(iwp_sc_t *sc, iwp_rx_desc_t *desc) in iwp_rx_mpdu_intr() argument
2213 ieee80211com_t *ic = &sc->sc_ic; in iwp_rx_mpdu_intr()
2215 iwp_rx_ring_t *ring = &sc->sc_rxq; in iwp_rx_mpdu_intr()
2233 stat = (iwp_rx_phy_res_t *)sc->sc_rx_phy_res.buf; in iwp_rx_mpdu_intr()
2281 if ((len < 16) || (len > sc->sc_dmabuf_sz)) { in iwp_rx_mpdu_intr()
2296 sc->sc_rx_err++; in iwp_rx_mpdu_intr()
2304 sc->sc_assoc_id = *((uint16_t *)(wh + 1) + 2); in iwp_rx_mpdu_intr()
2307 sc->sc_assoc_id)); in iwp_rx_mpdu_intr()
2327 sc->sc_rx_nobuf++; in iwp_rx_mpdu_intr()
2342 iwp_tx_intr(iwp_sc_t *sc, iwp_rx_desc_t *desc) in iwp_tx_intr() argument
2344 ieee80211com_t *ic = &sc->sc_ic; in iwp_tx_intr()
2345 iwp_tx_ring_t *ring = &sc->sc_txq[desc->hdr.qid & 0x3]; in iwp_tx_intr()
2361 sc->sc_tx_retries++; in iwp_tx_intr()
2364 sc->sc_tx_retries)); in iwp_tx_intr()
2367 mutex_enter(&sc->sc_mt_lock); in iwp_tx_intr()
2368 sc->sc_tx_timer = 0; in iwp_tx_intr()
2369 mutex_exit(&sc->sc_mt_lock); in iwp_tx_intr()
2371 mutex_enter(&sc->sc_tx_lock); in iwp_tx_intr()
2378 if ((sc->sc_need_reschedule) && (ring->queued <= (ring->count >> 3))) { in iwp_tx_intr()
2379 sc->sc_need_reschedule = 0; in iwp_tx_intr()
2380 mutex_exit(&sc->sc_tx_lock); in iwp_tx_intr()
2382 mutex_enter(&sc->sc_tx_lock); in iwp_tx_intr()
2385 mutex_exit(&sc->sc_tx_lock); in iwp_tx_intr()
2392 iwp_cmd_intr(iwp_sc_t *sc, iwp_rx_desc_t *desc) in iwp_cmd_intr() argument
2398 if (sc->sc_cmd_accum > 0) { in iwp_cmd_intr()
2399 sc->sc_cmd_accum--; in iwp_cmd_intr()
2403 mutex_enter(&sc->sc_glock); in iwp_cmd_intr()
2405 sc->sc_cmd_flag = SC_CMD_FLG_DONE; in iwp_cmd_intr()
2407 cv_signal(&sc->sc_cmd_cv); in iwp_cmd_intr()
2409 mutex_exit(&sc->sc_glock); in iwp_cmd_intr()
2421 iwp_ucode_alive(iwp_sc_t *sc, iwp_rx_desc_t *desc) in iwp_ucode_alive() argument
2427 struct iwp_calib_results *res_p = &sc->sc_calib_results; in iwp_ucode_alive()
2451 (void) memcpy(&sc->sc_card_alive_init, ar, in iwp_ucode_alive()
2457 mutex_enter(&sc->sc_glock); in iwp_ucode_alive()
2459 rv = iwp_alive_common(sc); in iwp_ucode_alive()
2463 mutex_exit(&sc->sc_glock); in iwp_ucode_alive()
2477 rv = iwp_cmd(sc, CALIBRATION_CFG_CMD, &cmd, sizeof (cmd), 1); in iwp_ucode_alive()
2481 mutex_exit(&sc->sc_glock); in iwp_ucode_alive()
2485 mutex_exit(&sc->sc_glock); in iwp_ucode_alive()
2492 (void) memcpy(&sc->sc_card_alive_run, ar, in iwp_ucode_alive()
2495 mutex_enter(&sc->sc_glock); in iwp_ucode_alive()
2500 rv = iwp_alive_common(sc); in iwp_ucode_alive()
2504 mutex_exit(&sc->sc_glock); in iwp_ucode_alive()
2512 rv = iwp_cmd(sc, REPLY_PHY_CALIBRATION_CMD, in iwp_ucode_alive()
2518 mutex_exit(&sc->sc_glock); in iwp_ucode_alive()
2529 rv = iwp_cmd(sc, REPLY_PHY_CALIBRATION_CMD, in iwp_ucode_alive()
2535 mutex_exit(&sc->sc_glock); in iwp_ucode_alive()
2546 rv = iwp_cmd(sc, REPLY_PHY_CALIBRATION_CMD, in iwp_ucode_alive()
2553 mutex_exit(&sc->sc_glock); in iwp_ucode_alive()
2564 rv = iwp_cmd(sc, REPLY_PHY_CALIBRATION_CMD, in iwp_ucode_alive()
2571 mutex_exit(&sc->sc_glock); in iwp_ucode_alive()
2578 atomic_or_32(&sc->sc_flags, IWP_F_FW_INIT); in iwp_ucode_alive()
2579 cv_signal(&sc->sc_ucode_cv); in iwp_ucode_alive()
2581 mutex_exit(&sc->sc_glock); in iwp_ucode_alive()
2594 iwp_sc_t *sc; in iwp_rx_softintr() local
2603 sc = (iwp_sc_t *)arg; in iwp_rx_softintr()
2604 ic = &sc->sc_ic; in iwp_rx_softintr()
2610 index = (sc->sc_shared->val0) & 0xfff; in iwp_rx_softintr()
2612 while (sc->sc_rxq.cur != index) { in iwp_rx_softintr()
2613 data = &sc->sc_rxq.data[sc->sc_rxq.cur]; in iwp_rx_softintr()
2619 index, sc->sc_rxq.cur, desc->hdr.qid, desc->hdr.idx, in iwp_rx_softintr()
2628 iwp_cmd_intr(sc, desc); in iwp_rx_softintr()
2633 iwp_rx_phy_intr(sc, desc); in iwp_rx_softintr()
2637 iwp_rx_mpdu_intr(sc, desc); in iwp_rx_softintr()
2641 iwp_tx_intr(sc, desc); in iwp_rx_softintr()
2645 iwp_ucode_alive(sc, desc); in iwp_rx_softintr()
2665 sc->sc_ostate = sc->sc_ic.ic_state; in iwp_rx_softintr()
2666 ieee80211_new_state(&sc->sc_ic, in iwp_rx_softintr()
2668 atomic_or_32(&sc->sc_flags, in iwp_rx_softintr()
2699 sc->sc_scan_pending++; in iwp_rx_softintr()
2712 iwp_save_calib_result(sc, desc); in iwp_rx_softintr()
2716 mutex_enter(&sc->sc_glock); in iwp_rx_softintr()
2717 atomic_or_32(&sc->sc_flags, IWP_F_FW_INIT); in iwp_rx_softintr()
2718 cv_signal(&sc->sc_ucode_cv); in iwp_rx_softintr()
2719 mutex_exit(&sc->sc_glock); in iwp_rx_softintr()
2740 sc->sc_rxq.cur = (sc->sc_rxq.cur + 1) % RX_QUEUE_SIZE; in iwp_rx_softintr()
2748 IWP_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, index & (~7)); in iwp_rx_softintr()
2753 IWP_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK); in iwp_rx_softintr()
2765 iwp_sc_t *sc; in iwp_intr() local
2771 sc = (iwp_sc_t *)arg; in iwp_intr()
2773 r = IWP_READ(sc, CSR_INT); in iwp_intr()
2781 rfh = IWP_READ(sc, CSR_FH_INT_STATUS); in iwp_intr()
2789 IWP_WRITE(sc, CSR_INT_MASK, 0); in iwp_intr()
2794 IWP_WRITE(sc, CSR_INT, r); in iwp_intr()
2795 IWP_WRITE(sc, CSR_FH_INT_STATUS, rfh); in iwp_intr()
2800 iwp_stop(sc); in iwp_intr()
2801 sc->sc_ostate = sc->sc_ic.ic_state; in iwp_intr()
2804 if (!IWP_CHK_FAST_RECOVER(sc)) { in iwp_intr()
2805 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1); in iwp_intr()
2808 atomic_or_32(&sc->sc_flags, IWP_F_HW_ERR_RECOVER); in iwp_intr()
2813 uint32_t tmp = IWP_READ(sc, CSR_GP_CNTRL); in iwp_intr()
2821 (void) ddi_intr_trigger_softint(sc->sc_soft_hdl, NULL); in iwp_intr()
2826 mutex_enter(&sc->sc_glock); in iwp_intr()
2827 atomic_or_32(&sc->sc_flags, IWP_F_PUT_SEG); in iwp_intr()
2828 cv_signal(&sc->sc_put_seg_cv); in iwp_intr()
2829 mutex_exit(&sc->sc_glock); in iwp_intr()
2842 IWP_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK); in iwp_intr()
2921 iwp_sc_t *sc; in iwp_m_tx() local
2928 sc = (iwp_sc_t *)arg; in iwp_m_tx()
2929 ic = &sc->sc_ic; in iwp_m_tx()
2931 if (sc->sc_flags & IWP_F_SUSPEND) { in iwp_m_tx()
2941 if ((sc->sc_flags & IWP_F_HW_ERR_RECOVER) && in iwp_m_tx()
2942 IWP_CHK_FAST_RECOVER(sc)) { in iwp_m_tx()
2968 iwp_sc_t *sc; in iwp_send() local
2986 sc = (iwp_sc_t *)ic; in iwp_send()
2988 if (sc->sc_flags & IWP_F_SUSPEND) { in iwp_send()
2997 mutex_enter(&sc->sc_tx_lock); in iwp_send()
2998 ring = &sc->sc_txq[0]; in iwp_send()
3012 sc->sc_need_reschedule = 1; in iwp_send()
3013 mutex_exit(&sc->sc_tx_lock); in iwp_send()
3019 sc->sc_tx_nobuf++; in iwp_send()
3026 mutex_exit(&sc->sc_tx_lock); in iwp_send()
3036 mutex_enter(&sc->sc_tx_lock); in iwp_send()
3038 if ((sc->sc_need_reschedule) && (ring->queued <= 0)) { in iwp_send()
3039 sc->sc_need_reschedule = 0; in iwp_send()
3040 mutex_exit(&sc->sc_tx_lock); in iwp_send()
3042 mutex_enter(&sc->sc_tx_lock); in iwp_send()
3044 mutex_exit(&sc->sc_tx_lock); in iwp_send()
3069 sc->sc_tx_err++; in iwp_send()
3071 mutex_enter(&sc->sc_tx_lock); in iwp_send()
3073 if ((sc->sc_need_reschedule) && (ring->queued <= 0)) { in iwp_send()
3074 sc->sc_need_reschedule = 0; in iwp_send()
3075 mutex_exit(&sc->sc_tx_lock); in iwp_send()
3077 mutex_enter(&sc->sc_tx_lock); in iwp_send()
3079 mutex_exit(&sc->sc_tx_lock); in iwp_send()
3113 sc->sc_tx_err++; in iwp_send()
3115 mutex_enter(&sc->sc_tx_lock); in iwp_send()
3117 if ((sc->sc_need_reschedule) && (ring->queued <= 0)) { in iwp_send()
3118 sc->sc_need_reschedule = 0; in iwp_send()
3119 mutex_exit(&sc->sc_tx_lock); in iwp_send()
3121 mutex_enter(&sc->sc_tx_lock); in iwp_send()
3123 mutex_exit(&sc->sc_tx_lock); in iwp_send()
3258 mutex_enter(&sc->sc_tx_lock); in iwp_send()
3283 sc->sc_shared->queues_byte_cnt_tbls[ring->qid]. in iwp_send()
3287 sc->sc_shared->queues_byte_cnt_tbls[ring->qid]. in iwp_send()
3296 IWP_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->desc_cur); in iwp_send()
3298 mutex_exit(&sc->sc_tx_lock); in iwp_send()
3309 mutex_enter(&sc->sc_mt_lock); in iwp_send()
3310 if (0 == sc->sc_tx_timer) { in iwp_send()
3311 sc->sc_tx_timer = 4; in iwp_send()
3313 mutex_exit(&sc->sc_mt_lock); in iwp_send()
3325 iwp_sc_t *sc; in iwp_m_ioctl() local
3332 sc = (iwp_sc_t *)arg; in iwp_m_ioctl()
3333 ic = &sc->sc_ic; in iwp_m_ioctl()
3346 if (sc->sc_flags & IWP_F_RUNNING) { in iwp_m_ioctl()
3347 iwp_m_stop(sc); in iwp_m_ioctl()
3348 (void) iwp_m_start(sc); in iwp_m_ioctl()
3363 iwp_sc_t *sc; in iwp_m_getprop() local
3369 sc = (iwp_sc_t *)arg; in iwp_m_getprop()
3371 err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num, in iwp_m_getprop()
3381 iwp_sc_t *sc; in iwp_m_propinfo() local
3383 sc = (iwp_sc_t *)arg; in iwp_m_propinfo()
3384 ieee80211_propinfo(&sc->sc_ic, pr_name, wldp_pr_num, prh); in iwp_m_propinfo()
3391 iwp_sc_t *sc; in iwp_m_setprop() local
3398 sc = (iwp_sc_t *)arg; in iwp_m_setprop()
3399 ic = &sc->sc_ic; in iwp_m_setprop()
3406 if (sc->sc_flags & IWP_F_RUNNING) { in iwp_m_setprop()
3407 iwp_m_stop(sc); in iwp_m_setprop()
3408 (void) iwp_m_start(sc); in iwp_m_setprop()
3424 iwp_sc_t *sc; in iwp_m_stat() local
3431 sc = (iwp_sc_t *)arg; in iwp_m_stat()
3432 ic = &sc->sc_ic; in iwp_m_stat()
3434 mutex_enter(&sc->sc_glock); in iwp_m_stat()
3444 *val = sc->sc_tx_nobuf; in iwp_m_stat()
3447 *val = sc->sc_rx_nobuf; in iwp_m_stat()
3450 *val = sc->sc_rx_err; in iwp_m_stat()
3466 *val = sc->sc_tx_err; in iwp_m_stat()
3469 *val = sc->sc_tx_retries; in iwp_m_stat()
3481 mutex_exit(&sc->sc_glock); in iwp_m_stat()
3484 mutex_exit(&sc->sc_glock); in iwp_m_stat()
3488 mutex_exit(&sc->sc_glock); in iwp_m_stat()
3500 iwp_sc_t *sc; in iwp_m_start() local
3507 sc = (iwp_sc_t *)arg; in iwp_m_start()
3508 ic = &sc->sc_ic; in iwp_m_start()
3510 err = iwp_init(sc); in iwp_m_start()
3517 atomic_or_32(&sc->sc_flags, IWP_F_HW_ERR_RECOVER); in iwp_m_start()
3523 atomic_or_32(&sc->sc_flags, IWP_F_RUNNING); in iwp_m_start()
3534 iwp_sc_t *sc; in iwp_m_stop() local
3540 sc = (iwp_sc_t *)arg; in iwp_m_stop()
3541 ic = &sc->sc_ic; in iwp_m_stop()
3543 iwp_stop(sc); in iwp_m_stop()
3548 iwp_release_calib_buffer(sc); in iwp_m_stop()
3552 atomic_and_32(&sc->sc_flags, ~IWP_F_HW_ERR_RECOVER); in iwp_m_stop()
3553 atomic_and_32(&sc->sc_flags, ~IWP_F_RATE_AUTO_CTL); in iwp_m_stop()
3555 atomic_and_32(&sc->sc_flags, ~IWP_F_RUNNING); in iwp_m_stop()
3556 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); in iwp_m_stop()
3565 iwp_sc_t *sc; in iwp_m_unicst() local
3572 sc = (iwp_sc_t *)arg; in iwp_m_unicst()
3573 ic = &sc->sc_ic; in iwp_m_unicst()
3577 mutex_enter(&sc->sc_glock); in iwp_m_unicst()
3578 err = iwp_config(sc); in iwp_m_unicst()
3579 mutex_exit(&sc->sc_glock); in iwp_m_unicst()
3611 iwp_thread(iwp_sc_t *sc) in iwp_thread() argument
3613 ieee80211com_t *ic = &sc->sc_ic; in iwp_thread()
3621 while (sc->sc_mf_thread_switch) { in iwp_thread()
3622 tmp = IWP_READ(sc, CSR_GP_CNTRL); in iwp_thread()
3624 atomic_and_32(&sc->sc_flags, ~IWP_F_RADIO_OFF); in iwp_thread()
3626 atomic_or_32(&sc->sc_flags, IWP_F_RADIO_OFF); in iwp_thread()
3632 if (sc->sc_flags & IWP_F_RADIO_OFF) { in iwp_thread()
3641 (sc->sc_flags & IWP_F_HW_ERR_RECOVER)) { in iwp_thread()
3646 iwp_stop(sc); in iwp_thread()
3648 if (IWP_CHK_FAST_RECOVER(sc)) { in iwp_thread()
3650 bcopy(&sc->sc_config, &sc->sc_config_save, in iwp_thread()
3651 sizeof (sc->sc_config)); in iwp_thread()
3657 err = iwp_init(sc); in iwp_thread()
3667 atomic_or_32(&sc->sc_flags, IWP_F_RUNNING); in iwp_thread()
3671 if (!IWP_CHK_FAST_RECOVER(sc) || in iwp_thread()
3672 iwp_fast_recover(sc) != IWP_SUCCESS) { in iwp_thread()
3673 atomic_and_32(&sc->sc_flags, in iwp_thread()
3677 if (sc->sc_ostate != IEEE80211_S_INIT) { in iwp_thread()
3685 (sc->sc_flags & IWP_F_SCANNING) && sc->sc_scan_pending) { in iwp_thread()
3689 sc->sc_scan_pending--; in iwp_thread()
3698 (sc->sc_flags & IWP_F_RATE_AUTO_CTL)) { in iwp_thread()
3700 if (clk > sc->sc_clk + drv_usectohz(1000000)) { in iwp_thread()
3701 iwp_amrr_timeout(sc); in iwp_thread()
3707 mutex_enter(&sc->sc_mt_lock); in iwp_thread()
3708 if (sc->sc_tx_timer) { in iwp_thread()
3711 sc->sc_tx_timer--; in iwp_thread()
3712 if (0 == sc->sc_tx_timer) { in iwp_thread()
3713 atomic_or_32(&sc->sc_flags, in iwp_thread()
3715 sc->sc_ostate = IEEE80211_S_RUN; in iwp_thread()
3723 mutex_exit(&sc->sc_mt_lock); in iwp_thread()
3726 mutex_enter(&sc->sc_mt_lock); in iwp_thread()
3727 sc->sc_mf_thread = NULL; in iwp_thread()
3728 cv_signal(&sc->sc_mt_cv); in iwp_thread()
3729 mutex_exit(&sc->sc_mt_lock); in iwp_thread()
3737 iwp_cmd(iwp_sc_t *sc, int code, const void *buf, int size, int async) in iwp_cmd() argument
3739 iwp_tx_ring_t *ring = &sc->sc_txq[IWP_CMD_QUEUE_NUM]; in iwp_cmd()
3744 ASSERT(mutex_owned(&sc->sc_glock)); in iwp_cmd()
3764 sc->sc_cmd_accum++; in iwp_cmd()
3770 sc->sc_shared->queues_byte_cnt_tbls[ring->qid]. in iwp_cmd()
3773 sc->sc_shared->queues_byte_cnt_tbls[ring->qid]. in iwp_cmd()
3777 IWP_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); in iwp_cmd()
3785 while (sc->sc_cmd_flag != SC_CMD_FLG_DONE) { in iwp_cmd()
3786 if (cv_timedwait(&sc->sc_cmd_cv, in iwp_cmd()
3787 &sc->sc_glock, clk) < 0) { in iwp_cmd()
3792 if (SC_CMD_FLG_DONE == sc->sc_cmd_flag) { in iwp_cmd()
3793 sc->sc_cmd_flag = SC_CMD_FLG_NONE; in iwp_cmd()
3796 sc->sc_cmd_flag = SC_CMD_FLG_NONE; in iwp_cmd()
3806 iwp_set_led(iwp_sc_t *sc, uint8_t id, uint8_t off, uint8_t on) in iwp_set_led() argument
3815 (void) iwp_cmd(sc, REPLY_LEDS_CMD, &led, sizeof (led), 1); in iwp_set_led()
3822 iwp_hw_set_before_auth(iwp_sc_t *sc) in iwp_hw_set_before_auth() argument
3824 ieee80211com_t *ic = &sc->sc_ic; in iwp_hw_set_before_auth()
3832 IEEE80211_ADDR_COPY(sc->sc_config.bssid, in->in_bssid); in iwp_hw_set_before_auth()
3833 sc->sc_config.chan = LE_16(ieee80211_chan2ieee(ic, in->in_chan)); in iwp_hw_set_before_auth()
3835 sc->sc_config.ofdm_ht_triple_stream_basic_rates = 0; in iwp_hw_set_before_auth()
3836 sc->sc_config.ofdm_ht_dual_stream_basic_rates = 0; in iwp_hw_set_before_auth()
3837 sc->sc_config.ofdm_ht_single_stream_basic_rates = 0; in iwp_hw_set_before_auth()
3840 sc->sc_config.cck_basic_rates = 0x03; in iwp_hw_set_before_auth()
3841 sc->sc_config.ofdm_basic_rates = 0; in iwp_hw_set_before_auth()
3844 sc->sc_config.cck_basic_rates = 0; in iwp_hw_set_before_auth()
3845 sc->sc_config.ofdm_basic_rates = 0x15; in iwp_hw_set_before_auth()
3847 sc->sc_config.cck_basic_rates = 0x0f; in iwp_hw_set_before_auth()
3848 sc->sc_config.ofdm_basic_rates = 0xff; in iwp_hw_set_before_auth()
3851 sc->sc_config.flags &= ~LE_32(RXON_FLG_SHORT_PREAMBLE_MSK | in iwp_hw_set_before_auth()
3855 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_SLOT_MSK); in iwp_hw_set_before_auth()
3857 sc->sc_config.flags &= LE_32(~RXON_FLG_SHORT_SLOT_MSK); in iwp_hw_set_before_auth()
3861 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_PREAMBLE_MSK); in iwp_hw_set_before_auth()
3863 sc->sc_config.flags &= LE_32(~RXON_FLG_SHORT_PREAMBLE_MSK); in iwp_hw_set_before_auth()
3870 LE_16(sc->sc_config.chan), LE_32(sc->sc_config.flags), in iwp_hw_set_before_auth()
3871 LE_32(sc->sc_config.filter_flags), in iwp_hw_set_before_auth()
3872 sc->sc_config.cck_basic_rates, sc->sc_config.ofdm_basic_rates, in iwp_hw_set_before_auth()
3873 sc->sc_config.bssid[0], sc->sc_config.bssid[1], in iwp_hw_set_before_auth()
3874 sc->sc_config.bssid[2], sc->sc_config.bssid[3], in iwp_hw_set_before_auth()
3875 sc->sc_config.bssid[4], sc->sc_config.bssid[5])); in iwp_hw_set_before_auth()
3877 err = iwp_cmd(sc, REPLY_RXON, &sc->sc_config, in iwp_hw_set_before_auth()
3881 "failed to config chan%d\n", sc->sc_config.chan); in iwp_hw_set_before_auth()
3888 err = iwp_add_ap_sta(sc); in iwp_hw_set_before_auth()
3901 iwp_scan(iwp_sc_t *sc) in iwp_scan() argument
3903 ieee80211com_t *ic = &sc->sc_ic; in iwp_scan()
3904 iwp_tx_ring_t *ring = &sc->sc_txq[IWP_CMD_QUEUE_NUM]; in iwp_scan()
4067 sc->sc_shared->queues_byte_cnt_tbls[ring->qid] in iwp_scan()
4070 sc->sc_shared->queues_byte_cnt_tbls[ring->qid]. in iwp_scan()
4078 IWP_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); in iwp_scan()
4087 iwp_config(iwp_sc_t *sc) in iwp_config() argument
4089 ieee80211com_t *ic = &sc->sc_ic; in iwp_config()
4102 err = iwp_cmd(sc, POWER_TABLE_CMD, &powertable, in iwp_config()
4117 err = iwp_cmd(sc, REPLY_BT_CONFIG, &bt, in iwp_config()
4128 (void) memset(&sc->sc_config, 0, sizeof (iwp_rxon_cmd_t)); in iwp_config()
4129 IEEE80211_ADDR_COPY(sc->sc_config.node_addr, ic->ic_macaddr); in iwp_config()
4130 IEEE80211_ADDR_COPY(sc->sc_config.wlap_bssid, ic->ic_macaddr); in iwp_config()
4131 sc->sc_config.chan = LE_16(ieee80211_chan2ieee(ic, ic->ic_curchan)); in iwp_config()
4132 sc->sc_config.flags = LE_32(RXON_FLG_BAND_24G_MSK); in iwp_config()
4133 sc->sc_config.flags &= LE_32(~(RXON_FLG_CHANNEL_MODE_MIXED_MSK | in iwp_config()
4138 sc->sc_config.dev_type = RXON_DEV_TYPE_ESS; in iwp_config()
4139 sc->sc_config.filter_flags |= LE_32(RXON_FILTER_ACCEPT_GRP_MSK | in iwp_config()
4145 sc->sc_config.dev_type = RXON_DEV_TYPE_IBSS; in iwp_config()
4147 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_PREAMBLE_MSK); in iwp_config()
4148 sc->sc_config.filter_flags = LE_32(RXON_FILTER_ACCEPT_GRP_MSK | in iwp_config()
4153 sc->sc_config.dev_type = RXON_DEV_TYPE_AP; in iwp_config()
4156 sc->sc_config.dev_type = RXON_DEV_TYPE_SNIFFER; in iwp_config()
4157 sc->sc_config.filter_flags |= LE_32(RXON_FILTER_ACCEPT_GRP_MSK | in iwp_config()
4165 sc->sc_config.cck_basic_rates = 0x0f; in iwp_config()
4170 sc->sc_config.ofdm_basic_rates = 0xff; in iwp_config()
4172 sc->sc_config.rx_chain = LE_16(RXON_RX_CHAIN_DRIVER_FORCE_MSK | in iwp_config()
4177 err = iwp_cmd(sc, REPLY_RXON, &sc->sc_config, in iwp_config()
4192 err = iwp_cmd(sc, REPLY_REMOVE_STA, &rm_sta, sizeof (iwp_rem_sta_t), 0); in iwp_config()
4208 err = iwp_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 0); in iwp_config()
4229 iwp_sc_t *sc; in iwp_quiesce() local
4231 sc = ddi_get_soft_state(iwp_soft_state_p, ddi_get_instance(dip)); in iwp_quiesce()
4232 if (NULL == sc) { in iwp_quiesce()
4245 atomic_or_32(&sc->sc_flags, IWP_F_QUIESCED); in iwp_quiesce()
4250 iwp_stop(sc); in iwp_quiesce()
4256 iwp_stop_master(iwp_sc_t *sc) in iwp_stop_master() argument
4261 tmp = IWP_READ(sc, CSR_RESET); in iwp_stop_master()
4262 IWP_WRITE(sc, CSR_RESET, tmp | CSR_RESET_REG_FLAG_STOP_MASTER); in iwp_stop_master()
4264 tmp = IWP_READ(sc, CSR_GP_CNTRL); in iwp_stop_master()
4271 if (IWP_READ(sc, CSR_RESET) & in iwp_stop_master()
4287 iwp_power_up(iwp_sc_t *sc) in iwp_power_up() argument
4291 iwp_mac_access_enter(sc); in iwp_power_up()
4292 tmp = iwp_reg_read(sc, ALM_APMG_PS_CTL); in iwp_power_up()
4295 iwp_reg_write(sc, ALM_APMG_PS_CTL, tmp); in iwp_power_up()
4296 iwp_mac_access_exit(sc); in iwp_power_up()
4306 iwp_preinit(iwp_sc_t *sc) in iwp_preinit() argument
4316 IWP_WRITE(sc, CSR_INT, 0xffffffff); in iwp_preinit()
4318 tmp = IWP_READ(sc, CSR_GIO_CHICKEN_BITS); in iwp_preinit()
4319 IWP_WRITE(sc, CSR_GIO_CHICKEN_BITS, in iwp_preinit()
4322 tmp = IWP_READ(sc, CSR_GP_CNTRL); in iwp_preinit()
4323 IWP_WRITE(sc, CSR_GP_CNTRL, tmp | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); in iwp_preinit()
4329 if (IWP_READ(sc, CSR_GP_CNTRL) & in iwp_preinit()
4340 iwp_mac_access_enter(sc); in iwp_preinit()
4342 iwp_reg_write(sc, ALM_APMG_CLK_EN, APMG_CLK_REG_VAL_DMA_CLK_RQT); in iwp_preinit()
4345 tmp = iwp_reg_read(sc, ALM_APMG_PCIDEV_STT); in iwp_preinit()
4346 iwp_reg_write(sc, ALM_APMG_PCIDEV_STT, tmp | in iwp_preinit()
4348 iwp_mac_access_exit(sc); in iwp_preinit()
4350 radio_cfg = IWP_READ_EEP_SHORT(sc, EEP_SP_RADIO_CONFIGURATION); in iwp_preinit()
4352 tmp = IWP_READ(sc, CSR_HW_IF_CONFIG_REG); in iwp_preinit()
4353 IWP_WRITE(sc, CSR_HW_IF_CONFIG_REG, in iwp_preinit()
4364 IWP_WRITE(sc, CSR_INT_COALESCING, 512 / 32); in iwp_preinit()
4366 (void) iwp_power_up(sc); in iwp_preinit()
4368 if ((sc->sc_rev & 0x80) == 0x80 && (sc->sc_rev & 0x7f) < 8) { in iwp_preinit()
4369 tmp = ddi_get32(sc->sc_cfg_handle, in iwp_preinit()
4370 (uint32_t *)(sc->sc_cfg_base + 0xe8)); in iwp_preinit()
4371 ddi_put32(sc->sc_cfg_handle, in iwp_preinit()
4372 (uint32_t *)(sc->sc_cfg_base + 0xe8), in iwp_preinit()
4376 vlink = ddi_get8(sc->sc_cfg_handle, in iwp_preinit()
4377 (uint8_t *)(sc->sc_cfg_base + 0xf0)); in iwp_preinit()
4378 ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base + 0xf0), in iwp_preinit()
4381 tmp = IWP_READ(sc, CSR_HW_IF_CONFIG_REG); in iwp_preinit()
4384 IWP_WRITE(sc, CSR_HW_IF_CONFIG_REG, tmp); in iwp_preinit()
4389 iwp_mac_access_enter(sc); in iwp_preinit()
4390 tmp = iwp_reg_read(sc, ALM_APMG_PS_CTL); in iwp_preinit()
4392 iwp_reg_write(sc, ALM_APMG_PS_CTL, tmp); in iwp_preinit()
4395 tmp = iwp_reg_read(sc, ALM_APMG_PS_CTL); in iwp_preinit()
4397 iwp_reg_write(sc, ALM_APMG_PS_CTL, tmp); in iwp_preinit()
4398 iwp_mac_access_exit(sc); in iwp_preinit()
4400 if (PA_TYPE_MIX == sc->sc_chip_param.pa_type) { in iwp_preinit()
4401 IWP_WRITE(sc, CSR_GP_DRIVER_REG, in iwp_preinit()
4405 if (PA_TYPE_INTER == sc->sc_chip_param.pa_type) { in iwp_preinit()
4407 IWP_WRITE(sc, CSR_GP_DRIVER_REG, in iwp_preinit()
4418 iwp_eep_sem_down(iwp_sc_t *sc) in iwp_eep_sem_down() argument
4424 tmp = IWP_READ(sc, CSR_HW_IF_CONFIG_REG); in iwp_eep_sem_down()
4425 IWP_WRITE(sc, CSR_HW_IF_CONFIG_REG, in iwp_eep_sem_down()
4429 if (IWP_READ(sc, CSR_HW_IF_CONFIG_REG) & in iwp_eep_sem_down()
4443 iwp_eep_sem_up(iwp_sc_t *sc) in iwp_eep_sem_up() argument
4447 tmp = IWP_READ(sc, CSR_HW_IF_CONFIG_REG); in iwp_eep_sem_up()
4448 IWP_WRITE(sc, CSR_HW_IF_CONFIG_REG, in iwp_eep_sem_up()
4456 iwp_eep_load(iwp_sc_t *sc) in iwp_eep_load() argument
4460 uint16_t addr, eep_sz = sizeof (sc->sc_eep_map); in iwp_eep_load()
4461 uint16_t *eep_p = (uint16_t *)&sc->sc_eep_map; in iwp_eep_load()
4466 eep_gp = IWP_READ(sc, CSR_EEPROM_GP); in iwp_eep_load()
4474 rr = iwp_eep_sem_down(sc); in iwp_eep_load()
4482 IWP_WRITE(sc, CSR_EEPROM_REG, addr<<1); in iwp_eep_load()
4483 tmp = IWP_READ(sc, CSR_EEPROM_REG); in iwp_eep_load()
4484 IWP_WRITE(sc, CSR_EEPROM_REG, tmp & ~(0x2)); in iwp_eep_load()
4487 rv = IWP_READ(sc, CSR_EEPROM_REG); in iwp_eep_load()
4497 iwp_eep_sem_up(sc); in iwp_eep_load()
4504 iwp_eep_sem_up(sc); in iwp_eep_load()
4512 iwp_get_mac_from_eep(iwp_sc_t *sc) in iwp_get_mac_from_eep() argument
4514 ieee80211com_t *ic = &sc->sc_ic; in iwp_get_mac_from_eep()
4516 IEEE80211_ADDR_COPY(ic->ic_macaddr, &sc->sc_eep_map[EEP_MAC_ADDRESS]); in iwp_get_mac_from_eep()
4528 iwp_init(iwp_sc_t *sc) in iwp_init() argument
4536 iwp_release_calib_buffer(sc); in iwp_init()
4538 mutex_enter(&sc->sc_glock); in iwp_init()
4539 atomic_and_32(&sc->sc_flags, ~IWP_F_FW_INIT); in iwp_init()
4541 err = iwp_init_common(sc); in iwp_init()
4543 mutex_exit(&sc->sc_glock); in iwp_init()
4550 (void) memcpy(sc->sc_dma_fw_data_bak.mem_va, in iwp_init()
4551 sc->sc_dma_fw_data.mem_va, in iwp_init()
4552 sc->sc_dma_fw_data.alength); in iwp_init()
4555 err = iwp_load_init_firmware(sc); in iwp_init()
4559 mutex_exit(&sc->sc_glock); in iwp_init()
4566 IWP_WRITE(sc, CSR_RESET, 0); in iwp_init()
4569 while (!(sc->sc_flags & IWP_F_FW_INIT)) { in iwp_init()
4570 if (cv_timedwait(&sc->sc_ucode_cv, in iwp_init()
4571 &sc->sc_glock, clk) < 0) { in iwp_init()
4576 if (!(sc->sc_flags & IWP_F_FW_INIT)) { in iwp_init()
4579 mutex_exit(&sc->sc_glock); in iwp_init()
4583 mutex_exit(&sc->sc_glock); in iwp_init()
4588 iwp_stop(sc); in iwp_init()
4590 mutex_enter(&sc->sc_glock); in iwp_init()
4591 atomic_and_32(&sc->sc_flags, ~IWP_F_FW_INIT); in iwp_init()
4593 err = iwp_init_common(sc); in iwp_init()
4595 mutex_exit(&sc->sc_glock); in iwp_init()
4602 err = iwp_load_run_firmware(sc); in iwp_init()
4606 mutex_exit(&sc->sc_glock); in iwp_init()
4613 IWP_WRITE(sc, CSR_RESET, 0); in iwp_init()
4616 while (!(sc->sc_flags & IWP_F_FW_INIT)) { in iwp_init()
4617 if (cv_timedwait(&sc->sc_ucode_cv, in iwp_init()
4618 &sc->sc_glock, clk) < 0) { in iwp_init()
4623 if (!(sc->sc_flags & IWP_F_FW_INIT)) { in iwp_init()
4626 mutex_exit(&sc->sc_glock); in iwp_init()
4630 mutex_exit(&sc->sc_glock); in iwp_init()
4634 mutex_enter(&sc->sc_glock); in iwp_init()
4635 atomic_and_32(&sc->sc_flags, ~IWP_F_FW_INIT); in iwp_init()
4641 err = iwp_config(sc); in iwp_init()
4645 mutex_exit(&sc->sc_glock); in iwp_init()
4652 mutex_exit(&sc->sc_glock); in iwp_init()
4660 iwp_stop(iwp_sc_t *sc) in iwp_stop() argument
4666 if (!(sc->sc_flags & IWP_F_QUIESCED)) { in iwp_stop()
4667 mutex_enter(&sc->sc_glock); in iwp_stop()
4670 IWP_WRITE(sc, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); in iwp_stop()
4674 IWP_WRITE(sc, CSR_INT_MASK, 0); in iwp_stop()
4675 IWP_WRITE(sc, CSR_INT, CSR_INI_SET_MASK); in iwp_stop()
4676 IWP_WRITE(sc, CSR_FH_INT_STATUS, 0xffffffff); in iwp_stop()
4682 iwp_reset_tx_ring(sc, &sc->sc_txq[i]); in iwp_stop()
4688 iwp_reset_rx_ring(sc); in iwp_stop()
4690 iwp_mac_access_enter(sc); in iwp_stop()
4691 iwp_reg_write(sc, ALM_APMG_CLK_DIS, APMG_CLK_REG_VAL_DMA_CLK_RQT); in iwp_stop()
4692 iwp_mac_access_exit(sc); in iwp_stop()
4696 iwp_stop_master(sc); in iwp_stop()
4698 mutex_enter(&sc->sc_mt_lock); in iwp_stop()
4699 sc->sc_tx_timer = 0; in iwp_stop()
4700 mutex_exit(&sc->sc_mt_lock); in iwp_stop()
4702 tmp = IWP_READ(sc, CSR_RESET); in iwp_stop()
4703 IWP_WRITE(sc, CSR_RESET, tmp | CSR_RESET_REG_FLAG_SW_RESET); in iwp_stop()
4706 if (!(sc->sc_flags & IWP_F_QUIESCED)) { in iwp_stop()
4707 mutex_exit(&sc->sc_glock); in iwp_stop()
4750 iwp_amrr_timeout(iwp_sc_t *sc) in iwp_amrr_timeout() argument
4752 ieee80211com_t *ic = &sc->sc_ic; in iwp_amrr_timeout()
4763 sc->sc_clk = ddi_get_lbolt(); in iwp_amrr_timeout()
4825 iwp_eep_addr_trans(iwp_sc_t *sc, uint32_t indi_addr) in iwp_eep_addr_trans() argument
4832 return (&sc->sc_eep_map[di_addr]); in iwp_eep_addr_trans()
4837 temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_GENERAL); in iwp_eep_addr_trans()
4840 temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_HOST); in iwp_eep_addr_trans()
4843 temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_REGULATORY); in iwp_eep_addr_trans()
4846 temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_CALIBRATION); in iwp_eep_addr_trans()
4849 temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_PROCESS_ADJST); in iwp_eep_addr_trans()
4852 temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_OTHERS); in iwp_eep_addr_trans()
4863 return (&sc->sc_eep_map[di_addr]); in iwp_eep_addr_trans()
4870 iwp_put_seg_fw(iwp_sc_t *sc, uint32_t addr_s, uint32_t addr_d, uint32_t len) in iwp_put_seg_fw() argument
4873 iwp_mac_access_enter(sc); in iwp_put_seg_fw()
4875 IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_CONFIG_REG(IWP_FH_SRVC_CHNL), in iwp_put_seg_fw()
4878 IWP_WRITE(sc, IWP_FH_SRVC_CHNL_SRAM_ADDR_REG(IWP_FH_SRVC_CHNL), addr_d); in iwp_put_seg_fw()
4880 IWP_WRITE(sc, IWP_FH_TFDIB_CTRL0_REG(IWP_FH_SRVC_CHNL), in iwp_put_seg_fw()
4883 IWP_WRITE(sc, IWP_FH_TFDIB_CTRL1_REG(IWP_FH_SRVC_CHNL), len); in iwp_put_seg_fw()
4885 IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_BUF_STS_REG(IWP_FH_SRVC_CHNL), in iwp_put_seg_fw()
4890 IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_CONFIG_REG(IWP_FH_SRVC_CHNL), in iwp_put_seg_fw()
4895 iwp_mac_access_exit(sc); in iwp_put_seg_fw()
4904 iwp_alive_common(iwp_sc_t *sc) in iwp_alive_common() argument
4915 iwp_mac_access_enter(sc); in iwp_alive_common()
4920 sc->sc_scd_base = iwp_reg_read(sc, IWP_SCD_SRAM_BASE_ADDR); in iwp_alive_common()
4922 for (base = sc->sc_scd_base + IWP_SCD_CONTEXT_DATA_OFFSET; in iwp_alive_common()
4923 base < sc->sc_scd_base + IWP_SCD_TX_STTS_BITMAP_OFFSET; in iwp_alive_common()
4925 iwp_mem_write(sc, base, 0); in iwp_alive_common()
4928 for (; base < sc->sc_scd_base + IWP_SCD_TRANSLATE_TBL_OFFSET; in iwp_alive_common()
4930 iwp_mem_write(sc, base, 0); in iwp_alive_common()
4934 iwp_mem_write(sc, base + i, 0); in iwp_alive_common()
4937 iwp_reg_write(sc, IWP_SCD_DRAM_BASE_ADDR, in iwp_alive_common()
4938 sc->sc_dma_sh.cookie.dmac_address >> 10); in iwp_alive_common()
4940 iwp_reg_write(sc, IWP_SCD_QUEUECHAIN_SEL, in iwp_alive_common()
4943 iwp_reg_write(sc, IWP_SCD_AGGR_SEL, 0); in iwp_alive_common()
4946 iwp_reg_write(sc, IWP_SCD_QUEUE_RDPTR(i), 0); in iwp_alive_common()
4947 IWP_WRITE(sc, HBUS_TARG_WRPTR, 0 | (i << 8)); in iwp_alive_common()
4948 iwp_mem_write(sc, sc->sc_scd_base + in iwp_alive_common()
4950 iwp_mem_write(sc, sc->sc_scd_base + in iwp_alive_common()
4960 iwp_reg_write(sc, IWP_SCD_INTERRUPT_MASK, (1 << IWP_NUM_QUEUES) - 1); in iwp_alive_common()
4962 iwp_reg_write(sc, (IWP_SCD_BASE + 0x10), in iwp_alive_common()
4965 IWP_WRITE(sc, HBUS_TARG_WRPTR, (IWP_CMD_QUEUE_NUM << 8)); in iwp_alive_common()
4966 iwp_reg_write(sc, IWP_SCD_QUEUE_RDPTR(IWP_CMD_QUEUE_NUM), 0); in iwp_alive_common()
4973 iwp_reg_write(sc, IWP_SCD_QUEUE_STATUS_BITS(i), in iwp_alive_common()
4980 iwp_reg_write(sc, IWP_SCD_QUEUE_STATUS_BITS(IWP_CMD_QUEUE_NUM), in iwp_alive_common()
4987 iwp_reg_write(sc, IWP_SCD_QUEUE_STATUS_BITS(i), in iwp_alive_common()
4994 iwp_mac_access_exit(sc); in iwp_alive_common()
4998 rv = iwp_cmd(sc, COEX_PRIORITY_TABLE_CMD, &w_cmd, sizeof (w_cmd), 1); in iwp_alive_common()
5008 c_cmd.data.cap_pin1 = LE_16(sc->sc_eep_calib->xtal_calib[0]); in iwp_alive_common()
5009 c_cmd.data.cap_pin2 = LE_16(sc->sc_eep_calib->xtal_calib[1]); in iwp_alive_common()
5011 rv = iwp_cmd(sc, REPLY_PHY_CALIBRATION_CMD, &c_cmd, sizeof (c_cmd), 1); in iwp_alive_common()
5031 iwp_save_calib_result(iwp_sc_t *sc, iwp_rx_desc_t *desc) in iwp_save_calib_result() argument
5033 struct iwp_calib_results *res_p = &sc->sc_calib_results; in iwp_save_calib_result()
5106 iwp_release_calib_buffer(iwp_sc_t *sc) in iwp_release_calib_buffer() argument
5108 if (sc->sc_calib_results.lo_res != NULL) { in iwp_release_calib_buffer()
5109 kmem_free(sc->sc_calib_results.lo_res, in iwp_release_calib_buffer()
5110 sc->sc_calib_results.lo_res_len); in iwp_release_calib_buffer()
5111 sc->sc_calib_results.lo_res = NULL; in iwp_release_calib_buffer()
5114 if (sc->sc_calib_results.tx_iq_res != NULL) { in iwp_release_calib_buffer()
5115 kmem_free(sc->sc_calib_results.tx_iq_res, in iwp_release_calib_buffer()
5116 sc->sc_calib_results.tx_iq_res_len); in iwp_release_calib_buffer()
5117 sc->sc_calib_results.tx_iq_res = NULL; in iwp_release_calib_buffer()
5120 if (sc->sc_calib_results.tx_iq_perd_res != NULL) { in iwp_release_calib_buffer()
5121 kmem_free(sc->sc_calib_results.tx_iq_perd_res, in iwp_release_calib_buffer()
5122 sc->sc_calib_results.tx_iq_perd_res_len); in iwp_release_calib_buffer()
5123 sc->sc_calib_results.tx_iq_perd_res = NULL; in iwp_release_calib_buffer()
5126 if (sc->sc_calib_results.base_band_res != NULL) { in iwp_release_calib_buffer()
5127 kmem_free(sc->sc_calib_results.base_band_res, in iwp_release_calib_buffer()
5128 sc->sc_calib_results.base_band_res_len); in iwp_release_calib_buffer()
5129 sc->sc_calib_results.base_band_res = NULL; in iwp_release_calib_buffer()
5138 iwp_init_common(iwp_sc_t *sc) in iwp_init_common() argument
5143 (void) iwp_preinit(sc); in iwp_init_common()
5145 tmp = IWP_READ(sc, CSR_GP_CNTRL); in iwp_init_common()
5155 iwp_mac_access_enter(sc); in iwp_init_common()
5156 IWP_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); in iwp_init_common()
5158 IWP_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); in iwp_init_common()
5159 IWP_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_BASE_REG, in iwp_init_common()
5160 sc->sc_rxq.dma_desc.cookie.dmac_address >> 8); in iwp_init_common()
5162 IWP_WRITE(sc, FH_RSCSR_CHNL0_STTS_WPTR_REG, in iwp_init_common()
5163 ((uint32_t)(sc->sc_dma_sh.cookie.dmac_address + in iwp_init_common()
5166 IWP_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, in iwp_init_common()
5172 iwp_mac_access_exit(sc); in iwp_init_common()
5173 IWP_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, in iwp_init_common()
5179 iwp_mac_access_enter(sc); in iwp_init_common()
5180 iwp_reg_write(sc, IWP_SCD_TXFACT, 0); in iwp_init_common()
5185 IWP_WRITE(sc, IWP_FH_KW_MEM_ADDR_REG, in iwp_init_common()
5186 sc->sc_dma_kw.cookie.dmac_address >> 4); in iwp_init_common()
5189 IWP_WRITE(sc, FH_MEM_CBBC_QUEUE(qid), in iwp_init_common()
5190 sc->sc_txq[qid].dma_desc.cookie.dmac_address >> 8); in iwp_init_common()
5191 IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_CONFIG_REG(qid), in iwp_init_common()
5196 iwp_mac_access_exit(sc); in iwp_init_common()
5201 IWP_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); in iwp_init_common()
5202 IWP_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, in iwp_init_common()
5208 IWP_WRITE(sc, CSR_INT, 0xffffffff); in iwp_init_common()
5213 IWP_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK); in iwp_init_common()
5215 IWP_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); in iwp_init_common()
5216 IWP_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); in iwp_init_common()
5222 iwp_fast_recover(iwp_sc_t *sc) in iwp_fast_recover() argument
5224 ieee80211com_t *ic = &sc->sc_ic; in iwp_fast_recover()
5227 mutex_enter(&sc->sc_glock); in iwp_fast_recover()
5230 bcopy(&sc->sc_config_save, &sc->sc_config, in iwp_fast_recover()
5231 sizeof (sc->sc_config)); in iwp_fast_recover()
5233 sc->sc_config.assoc_id = 0; in iwp_fast_recover()
5234 sc->sc_config.filter_flags &= ~LE_32(RXON_FILTER_ASSOC_MSK); in iwp_fast_recover()
5236 if ((err = iwp_hw_set_before_auth(sc)) != IWP_SUCCESS) { in iwp_fast_recover()
5239 mutex_exit(&sc->sc_glock); in iwp_fast_recover()
5243 bcopy(&sc->sc_config_save, &sc->sc_config, in iwp_fast_recover()
5244 sizeof (sc->sc_config)); in iwp_fast_recover()
5247 err = iwp_run_state_config(sc); in iwp_fast_recover()
5251 mutex_exit(&sc->sc_glock); in iwp_fast_recover()
5255 iwp_set_led(sc, 2, 0, 1); in iwp_fast_recover()
5257 mutex_exit(&sc->sc_glock); in iwp_fast_recover()
5259 atomic_and_32(&sc->sc_flags, ~IWP_F_HW_ERR_RECOVER); in iwp_fast_recover()
5270 iwp_run_state_config(iwp_sc_t *sc) in iwp_run_state_config() argument
5272 struct ieee80211com *ic = &sc->sc_ic; in iwp_run_state_config()
5279 sc->sc_config.assoc_id = in->in_associd & 0x3fff; in iwp_run_state_config()
5285 sc->sc_config.flags &= in iwp_run_state_config()
5290 sc->sc_config.flags |= in iwp_run_state_config()
5295 sc->sc_config.flags |= in iwp_run_state_config()
5299 sc->sc_config.filter_flags |= in iwp_run_state_config()
5303 sc->sc_config.filter_flags |= in iwp_run_state_config()
5310 sc->sc_config.chan, sc->sc_config.flags, in iwp_run_state_config()
5311 sc->sc_config.filter_flags)); in iwp_run_state_config()
5313 err = iwp_cmd(sc, REPLY_RXON, &sc->sc_config, in iwp_run_state_config()
5329 iwp_overwrite_ic_default(iwp_sc_t *sc) in iwp_overwrite_ic_default() argument
5331 ieee80211com_t *ic = &sc->sc_ic; in iwp_overwrite_ic_default()
5333 sc->sc_newstate = ic->ic_newstate; in iwp_overwrite_ic_default()
5344 iwp_add_ap_sta(iwp_sc_t *sc) in iwp_add_ap_sta() argument
5346 ieee80211com_t *ic = &sc->sc_ic; in iwp_add_ap_sta()
5359 err = iwp_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 1); in iwp_add_ap_sta()
5373 iwp_eep_ver_chk(iwp_sc_t *sc) in iwp_eep_ver_chk() argument
5375 if ((IWP_READ_EEP_SHORT(sc, EEP_VERSION) < 0x011a) || in iwp_eep_ver_chk()
5376 (sc->sc_eep_calib->tx_pow_calib_hdr.calib_version < 4)) { in iwp_eep_ver_chk()
5389 iwp_set_chip_param(iwp_sc_t *sc) in iwp_set_chip_param() argument
5391 if ((0x008d == sc->sc_dev_id) || in iwp_set_chip_param()
5392 (0x008e == sc->sc_dev_id)) { in iwp_set_chip_param()
5393 sc->sc_chip_param.phy_mode = PHY_MODE_G | in iwp_set_chip_param()
5396 sc->sc_chip_param.tx_ant = ANT_A | ANT_B; in iwp_set_chip_param()
5397 sc->sc_chip_param.rx_ant = ANT_A | ANT_B; in iwp_set_chip_param()
5399 sc->sc_chip_param.pa_type = PA_TYPE_MIX; in iwp_set_chip_param()
5402 if ((0x422c == sc->sc_dev_id) || in iwp_set_chip_param()
5403 (0x4239 == sc->sc_dev_id)) { in iwp_set_chip_param()
5404 sc->sc_chip_param.phy_mode = PHY_MODE_G | in iwp_set_chip_param()
5407 sc->sc_chip_param.tx_ant = ANT_B | ANT_C; in iwp_set_chip_param()
5408 sc->sc_chip_param.rx_ant = ANT_B | ANT_C; in iwp_set_chip_param()
5410 sc->sc_chip_param.pa_type = PA_TYPE_INTER; in iwp_set_chip_param()
5413 if ((0x422b == sc->sc_dev_id) || in iwp_set_chip_param()
5414 (0x4238 == sc->sc_dev_id)) { in iwp_set_chip_param()
5415 sc->sc_chip_param.phy_mode = PHY_MODE_G | in iwp_set_chip_param()
5418 sc->sc_chip_param.tx_ant = ANT_A | ANT_B | ANT_C; in iwp_set_chip_param()
5419 sc->sc_chip_param.rx_ant = ANT_A | ANT_B | ANT_C; in iwp_set_chip_param()
5421 sc->sc_chip_param.pa_type = PA_TYPE_SYSTEM; in iwp_set_chip_param()