Lines Matching refs:v

88 #define	USall_EVENTS_0(v)					\  argument
89 {v, 0x0, "Cycle_cnt"}, \
90 {v, 0x1, "Instr_cnt"}, \
91 {v, 0x2, "Dispatch0_IC_miss"}, \
92 {v, 0x8, "IC_ref"}, \
93 {v, 0x9, "DC_rd"}, \
94 {v, 0xa, "DC_wr"}, \
95 {v, 0xc, "EC_ref"}, \
96 {v, 0xe, "EC_snoop_inv"}
107 #define US3all_EVENTS_0(v) \ argument
108 {v, 0x3, "Dispatch0_br_target"}, \
109 {v, 0x4, "Dispatch0_2nd_br"}, \
110 {v, 0x5, "Rstall_storeQ"}, \
111 {v, 0x6, "Rstall_IU_use"}, \
112 {v, 0xd, "EC_write_hit_RTO"}, \
113 {v, 0xf, "EC_rd_miss"}, \
114 {v, 0x10, "PC_port0_rd"}, \
115 {v, 0x11, "SI_snoop"}, \
116 {v, 0x12, "SI_ciq_flow"}, \
117 {v, 0x13, "SI_owned"}, \
118 {v, 0x14, "SW_count_0"}, \
119 {v, 0x15, "IU_Stat_Br_miss_taken"}, \
120 {v, 0x16, "IU_Stat_Br_count_taken"}, \
121 {v, 0x17, "Dispatch_rs_mispred"}, \
122 {v, 0x18, "FA_pipe_completion"}
124 #define US3_MC_EVENTS_0(v) \ argument
125 {v, 0x20, "MC_reads_0"}, \
126 {v, 0x21, "MC_reads_1"}, \
127 {v, 0x22, "MC_reads_2"}, \
128 {v, 0x23, "MC_reads_3"}, \
129 {v, 0x24, "MC_stalls_0"}, \
130 {v, 0x25, "MC_stalls_2"}
132 #define US3_I_MC_EVENTS_0(v) \ argument
133 {v, 0x20, "MC_read_dispatched"}, \
134 {v, 0x21, "MC_write_dispatched"}, \
135 {v, 0x22, "MC_read_returned_to_JBU"}, \
136 {v, 0x23, "MC_msl_busy_stall"}, \
137 {v, 0x24, "MC_mdb_overflow_stall"}, \
138 {v, 0x25, "MC_miu_spec_request"}
225 #define USall_EVENTS_1(v) \ argument
226 {v, 0x0, "Cycle_cnt"}, \
227 {v, 0x1, "Instr_cnt"}, \
228 {v, 0x2, "Dispatch0_mispred"}, \
229 {v, 0xd, "EC_wb"}, \
230 {v, 0xe, "EC_snoop_cb"}
244 #define US3all_EVENTS_1(v) \ argument
245 {v, 0x3, "IC_miss_cancelled"}, \
246 {v, 0x5, "Re_FPU_bypass"}, \
247 {v, 0x6, "Re_DC_miss"}, \
248 {v, 0x7, "Re_EC_miss"}, \
249 {v, 0x8, "IC_miss"}, \
250 {v, 0x9, "DC_rd_miss"}, \
251 {v, 0xa, "DC_wr_miss"}, \
252 {v, 0xb, "Rstall_FP_use"}, \
253 {v, 0xc, "EC_misses"}, \
254 {v, 0xf, "EC_ic_miss"}, \
255 {v, 0x10, "Re_PC_miss"}, \
256 {v, 0x11, "ITLB_miss"}, \
257 {v, 0x12, "DTLB_miss"}, \
258 {v, 0x13, "WC_miss"}, \
259 {v, 0x14, "WC_snoop_cb"}, \
260 {v, 0x15, "WC_scrubbed"}, \
261 {v, 0x16, "WC_wb_wo_read"}, \
262 {v, 0x18, "PC_soft_hit"}, \
263 {v, 0x19, "PC_snoop_inv"}, \
264 {v, 0x1a, "PC_hard_hit"}, \
265 {v, 0x1b, "PC_port1_rd"}, \
266 {v, 0x1c, "SW_count_1"}, \
267 {v, 0x1d, "IU_Stat_Br_miss_untaken"}, \
268 {v, 0x1e, "IU_Stat_Br_count_untaken"}, \
269 {v, 0x1f, "PC_MS_misses"}, \
270 {v, 0x26, "Re_RAW_miss"}, \
271 {v, 0x27, "FM_pipe_completion"}
273 #define US3_MC_EVENTS_1(v) \ argument
274 {v, 0x20, "MC_writes_0"}, \
275 {v, 0x21, "MC_writes_1"}, \
276 {v, 0x22, "MC_writes_2"}, \
277 {v, 0x23, "MC_writes_3"}, \
278 {v, 0x24, "MC_stalls_1"}, \
279 {v, 0x25, "MC_stalls_3"}
281 #define US3_I_MC_EVENTS_1(v) \ argument
282 {v, 0x20, "MC_open_bank_cmds"}, \
283 {v, 0x21, "MC_reads"}, \
284 {v, 0x22, "MC_writes"}, \
285 {v, 0x23, "MC_page_close_stall"}