Lines Matching refs:v
74 #define P5_EVENTS(v) \ argument
75 {v, 0x0, "data_read"}, \
76 {v, 0x1, "data_write"}, \
77 {v, 0x2, "data_tlb_miss"}, \
78 {v, 0x3, "data_read_miss"}, \
79 {v, 0x4, "data_write_miss"}, \
80 {v, 0x5, "write_hit_to_M_or_E"}, \
81 {v, 0x6, "dcache_lines_wrback"}, \
82 {v, 0x7, "external_snoops"}, \
83 {v, 0x8, "external_dcache_snoop_hits"}, \
84 {v, 0x9, "memory_access_in_both_pipes"}, \
85 {v, 0xa, "bank_conflicts"}, \
86 {v, 0xb, "misaligned_ref"}, \
87 {v, 0xc, "code_read"}, \
88 {v, 0xd, "code_tlb_miss"}, \
89 {v, 0xe, "code_cache_miss"}, \
90 {v, 0xf, "any_segreg_loaded"}, \
91 {v, 0x12, "branches"}, \
92 {v, 0x13, "btb_hits"}, \
93 {v, 0x14, "taken_or_btb_hit"}, \
94 {v, 0x15, "pipeline_flushes"}, \
95 {v, 0x16, "instr_exec"}, \
96 {v, 0x17, "instr_exec_V_pipe"}, \
97 {v, 0x18, "clks_bus_cycle"}, \
98 {v, 0x19, "clks_full_wbufs"}, \
99 {v, 0x1a, "pipe_stall_read"}, \
100 {v, 0x1b, "stall_on_write_ME"}, \
101 {v, 0x1c, "locked_bus_cycle"}, \
102 {v, 0x1d, "io_rw_cycles"}, \
103 {v, 0x1e, "reads_noncache_mem"}, \
104 {v, 0x1f, "pipeline_agi_stalls"}, \
105 {v, 0x22, "flops"}, \
106 {v, 0x23, "bp_match_dr0"}, \
107 {v, 0x24, "bp_match_dr1"}, \
108 {v, 0x25, "bp_match_dr2"}, \
109 {v, 0x26, "bp_match_dr3"}, \
110 {v, 0x27, "hw_intrs"}, \
111 {v, 0x28, "data_rw"}, \
112 {v, 0x29, "data_rw_miss"}
495 #define BITS(v, u, l) \ argument
496 (((v) >> (l)) & ((1 << (1 + (u) - (l))) - 1))