Lines Matching refs:writel
400 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); in mii_rw()
405 writel(reg & ~NVREG_ADAPTCTL_RUNNING, in mii_rw()
410 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl); in mii_rw()
417 writel(value, base + NvRegMIIData); in mii_rw()
420 writel(reg, base + NvRegMIIControl); in mii_rw()
445 writel(reg | NVREG_ADAPTCTL_RUNNING, in mii_rw()
458 writel(0, base + NvRegReceiverControl); in start_rx()
461 writel(np->linkspeed, base + NvRegLinkSpeed); in start_rx()
463 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl); in start_rx()
472 writel(0, base + NvRegReceiverControl); in stop_rx()
478 writel(0, base + NvRegLinkSpeed); in stop_rx()
486 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl); in start_tx()
495 writel(0, base + NvRegTransmitterControl); in stop_tx()
501 writel(0, base + NvRegUnknownTransmitterReg); in stop_tx()
510 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET, in txrx_reset()
514 writel(NVREG_TXRXCTL_BIT2, base + NvRegTxRxControl); in txrx_reset()
625 writel(addr[0], base + NvRegMulticastAddrA); in set_multicast()
626 writel(addr[1], base + NvRegMulticastAddrB); in set_multicast()
627 writel(mask[0], base + NvRegMulticastMaskA); in set_multicast()
628 writel(mask[1], base + NvRegMulticastMaskB); in set_multicast()
629 writel(pff, base + NvRegPacketFilterFlags); in set_multicast()
645 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); in forcedeth_reset()
646 writel(0, base + NvRegMulticastAddrB); in forcedeth_reset()
647 writel(0, base + NvRegMulticastMaskA); in forcedeth_reset()
648 writel(0, base + NvRegMulticastMaskB); in forcedeth_reset()
649 writel(0, base + NvRegPacketFilterFlags); in forcedeth_reset()
650 writel(0, base + NvRegAdapterControl); in forcedeth_reset()
651 writel(0, base + NvRegLinkSpeed); in forcedeth_reset()
652 writel(0, base + NvRegUnknownTransmitterReg); in forcedeth_reset()
654 writel(0, base + NvRegUnknownSetupReg6); in forcedeth_reset()
670 writel(mac[0], base + NvRegMacAddrA); in forcedeth_reset()
671 writel(mac[1], base + NvRegMacAddrB); in forcedeth_reset()
677 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3); in forcedeth_reset()
678 writel(0, base + NvRegTxRxControl); in forcedeth_reset()
680 writel(NVREG_TXRXCTL_BIT1, base + NvRegTxRxControl); in forcedeth_reset()
686 writel(0, base + NvRegUnknownSetupReg4); in forcedeth_reset()
689 writel(NVREG_MIISPEED_BIT8 | NVREG_MIIDELAY, base + NvRegMIISpeed); in forcedeth_reset()
717 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD), in forcedeth_reset()
719 writel(readl(base + NvRegTransmitterStatus), in forcedeth_reset()
721 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags); in forcedeth_reset()
722 writel(NVREG_OFFLOAD_NORMAL, base + NvRegOffloadConfig); in forcedeth_reset()
724 writel(readl(base + NvRegReceiverStatus), in forcedeth_reset()
729 writel(NVREG_RNDSEED_FORCE | (i & NVREG_RNDSEED_MASK), in forcedeth_reset()
731 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1); in forcedeth_reset()
732 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2); in forcedeth_reset()
733 writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval); in forcedeth_reset()
734 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); in forcedeth_reset()
735 writel((np-> in forcedeth_reset()
738 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4); in forcedeth_reset()
739 writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags); in forcedeth_reset()
742 writel((u32) virt_to_le32desc(&rx_ring[0]), in forcedeth_reset()
744 writel((u32) virt_to_le32desc(&tx_ring[0]), in forcedeth_reset()
748 writel(((RX_RING - 1) << NVREG_RINGSZ_RXSHIFT) + in forcedeth_reset()
754 writel(NVREG_POWERSTATE_POWEREDUP | i, in forcedeth_reset()
759 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, in forcedeth_reset()
761 writel(NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl); in forcedeth_reset()
763 writel(0, base + NvRegIrqMask); in forcedeth_reset()
765 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); in forcedeth_reset()
767 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus); in forcedeth_reset()
768 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); in forcedeth_reset()
773 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); in forcedeth_reset()
774 writel(0, base + NvRegMulticastAddrB); in forcedeth_reset()
775 writel(0, base + NvRegMulticastMaskA); in forcedeth_reset()
776 writel(0, base + NvRegMulticastMaskB); in forcedeth_reset()
777 writel(NVREG_PFF_ALWAYS | NVREG_PFF_MYADDR, in forcedeth_reset()
869 writel(NVREG_TXRXCTL_KICK, base + NvRegTxRxControl); in forcedeth_transmit()
896 writel(0, base + NvRegIrqMask); in forcedeth_disable()
903 writel(np->orig_mac[0], base + NvRegMacAddrA); in forcedeth_disable()
904 writel(np->orig_mac[1], base + NvRegMacAddrB); in forcedeth_disable()