Lines Matching refs:prefetch
1169 ! On US-III, the prefetch instruction queue is 8 entries deep.
1174 ! Since prefetch can only bring in 64 bytes at a time (See Sparc
1179 ! Since the prefetch queue is 8 entries deep, we currently can
1199 ! |Preftch| but we enqueue prefetch for addr = XXX1
1201 ! +-------+<--- this queue slot will be a prefetch instruction for
1231 ! we'll need an additional prefetch to get an entire page
1252 prefetch [%o0+STRIDE1], #n_writes
1254 prefetch [%o0+STRIDE2], #n_writes
1258 ! Note on CHEETAH to prefetch for read, we really use #one_write.
1262 prefetch [%o0+STRIDE1], #one_write
1264 prefetch [%o0+STRIDE2], #one_write
1272 ! So prefetch for pp + 1, which is
1286 prefetch [%o0+STRIDE1], #n_writes
1288 prefetch [%o0+STRIDE2], #n_writes
1292 prefetch [%o0+STRIDE1], #n_reads
1294 prefetch [%o0+STRIDE2], #n_reads
1306 prefetch [%o0+STRIDE1], #n_writes
1308 prefetch [%o0+STRIDE2], #n_writes
1312 prefetch [%o0+STRIDE1], #n_writes
1314 prefetch [%o0+STRIDE2], #n_writes
1365 ! The hardware will prefetch the 64 byte cache aligned block
1366 ! that contains the address specified in the prefetch instruction.
1367 ! Since the size of the smap struct is 48 bytes, issuing 1 prefetch
1368 ! per pass will suffice as long as we prefetch far enough ahead to
1370 ! spans multiple hardware prefetch blocks. Let's prefetch as far
1382 prefetch [%o0-SMAP_STRIDE], #n_writes