82 	struct regs	*pregs,	/* Pointer to PCB image of registers. */  in vis_fpu_simulator()  argument
95 	ASSERT(USERMODE(pregs->r_tstate));  in vis_fpu_simulator()
123 		ftt = vis_edge(pfpsd, f.inst, pregs, prw);  in vis_fpu_simulator()
128 		ftt = vis_array(pfpsd, f.inst, pregs, prw);  in vis_fpu_simulator()
132 		ftt = vis_alignaddr(pfpsd, f.inst, pregs, prw, fp);  in vis_fpu_simulator()
135 		ftt = vis_bmask(pfpsd, f.inst, pregs, prw, fp);  in vis_fpu_simulator()
145 		ftt = vis_fcmp(pfpsd, f.inst, pregs, prw);  in vis_fpu_simulator()
165 		ftt = vis_pdist(pfpsd, pinst, pregs, prw, f.inst.opf);  in vis_fpu_simulator()
362 	pregs->r_pc = pregs->r_npc;	/* Do not retry emulated instruction. */  in vis_fpu_simulator()
363 	pregs->r_npc += 4;  in vis_fpu_simulator()
374 	struct regs	*pregs,	/* Pointer to PCB image of registers. */  in vis_edge()  argument
389 	ftt = read_iureg(pfpsd, nrs1, pregs, prw, &addrl);  in vis_edge()
392 	ftt = read_iureg(pfpsd, nrs2, pregs, prw, &addrr);  in vis_edge()
397 	if ((pregs->r_tstate & TSTATE_AM) != 0) {  in vis_edge()
523 	ftt = write_iureg(pfpsd, nrd, pregs, prw, &mask);  in vis_edge()
534 		pregs->r_tstate &= ~((uint64_t)TSTATE_CCR_MASK  in vis_edge()
537 		pregs->r_tstate |= ((uint64_t)ccr << TSTATE_CCR_SHIFT);  in vis_edge()
551 	struct regs	*pregs,	/* Pointer to PCB image of registers. */  in vis_array()  argument
565 	ftt = read_iureg(pfpsd, nrs1, pregs, prw, &laddr);  in vis_array()
568 	ftt = read_iureg(pfpsd, nrs2, pregs, prw, &bsize);  in vis_array()
604 	ftt = write_iureg(pfpsd, nrd, pregs, prw, &baddr);  in vis_array()
616 	struct regs	*pregs,	/* Pointer to PCB image of registers. */  in vis_alignaddr()  argument
629 	ftt = read_iureg(pfpsd, nrs1, pregs, prw, &ea);  in vis_alignaddr()
632 	ftt = read_iureg(pfpsd, nrs2, pregs, prw, &tea);  in vis_alignaddr()
637 	ftt = write_iureg(pfpsd, nrd, pregs, prw, &r);  in vis_alignaddr()
663 	struct regs	*pregs,	/* Pointer to PCB image of registers. */  in vis_bmask()  argument
676 	ftt = read_iureg(pfpsd, nrs1, pregs, prw, &ea);  in vis_bmask()
679 	ftt = read_iureg(pfpsd, nrs2, pregs, prw, &tea);  in vis_bmask()
683 	ftt = write_iureg(pfpsd, nrd, pregs, prw, &ea);  in vis_bmask()
797 	struct regs	*pregs,	/* Pointer to PCB image of registers. */  in vis_fcmp()  argument
895 	ftt = write_iureg(pfpsd, nrd, pregs, prw, &krd.ll);  in vis_fcmp()
1189 	struct regs	*pregs,	/* Pointer to PCB image of registers. */  in vis_pdist()  argument
1235 		(void) write_iureg(pfpsd, nrd, pregs, prw, &lrd.ll);  in vis_pdist()
1373 	struct regs	*pregs,	/* Pointer to PCB image of registers. */  in vis_fldst()  argument
1382 	ASSERT(USERMODE(pregs->r_tstate));  in vis_fldst()
1397 			return (vis_prtl_fst(pfpsd, i.inst, pregs,  in vis_fldst()
1407 			return (vis_short_fls(pfpsd, i.inst, pregs,  in vis_fldst()
1419 			return (vis_blk_fldst(pfpsd, i.inst, pregs,  in vis_fldst()
1433 	struct regs	*pregs,	/* Pointer to PCB image of registers. */  in vis_prtl_fst()  argument
1458 		ftt = read_iureg(pfpsd, nrs1, pregs, prw, &ea);  in vis_prtl_fst()
1461 		ftt = read_iureg(pfpsd, nrs2, pregs, prw, &tmsk);  in vis_prtl_fst()
1466 		pfpsd->fp_trapaddr = (caddr_t)pregs->r_pc;  in vis_prtl_fst()
1583 	pregs->r_pc = pregs->r_npc;	/* Do not retry emulated instruction. */  in vis_prtl_fst()
1584 	pregs->r_npc += 4;  in vis_prtl_fst()
1595 	struct regs	*pregs,	/* Pointer to PCB image of registers. */  in vis_short_fls()  argument
1625 		ftt = read_iureg(pfpsd, nrs1, pregs, prw, &ea);  in vis_short_fls()
1628 		ftt = read_iureg(pfpsd, nrs2, pregs, prw, &tea);  in vis_short_fls()
1635 		ftt = read_iureg(pfpsd, nrs1, pregs, prw, &tea);  in vis_short_fls()
1700 	pregs->r_pc = pregs->r_npc;	/* Do not retry emulated instruction. */  in vis_short_fls()
1701 	pregs->r_npc += 4;  in vis_short_fls()
1714 	struct regs	*pregs,	/* Pointer to PCB image of registers. */  in vis_blk_fldst()  argument
1745 		ftt = read_iureg(pfpsd, nrs1, pregs, prw, &ea);  in vis_blk_fldst()
1748 		ftt = read_iureg(pfpsd, nrs2, pregs, prw, &tea);  in vis_blk_fldst()
1755 		ftt = read_iureg(pfpsd, nrs1, pregs, prw, &tea);  in vis_blk_fldst()
1813 		pfpsd->fp_trapaddr = (caddr_t)pregs->r_pc;  in vis_blk_fldst()
1817 	pregs->r_pc = pregs->r_npc;	/* Do not retry emulated instruction. */  in vis_blk_fldst()
1818 	pregs->r_npc += 4;  in vis_blk_fldst()
1829 	struct regs	*pregs,	/* Pointer to PCB image of registers. */  in vis_rdgsr()  argument
1840 	ftt = write_iureg(pfpsd, nrd, pregs, prw, &r);  in vis_rdgsr()
1841 	pregs->r_pc = pregs->r_npc;	/* Do not retry emulated instruction. */  in vis_rdgsr()
1842 	pregs->r_npc += 4;  in vis_rdgsr()
1853 	struct regs	*pregs,	/* Pointer to PCB image of registers. */  in vis_wrgsr()  argument
1862 	ftt = read_iureg(pfpsd, nrs1, pregs, prw, &r1);  in vis_wrgsr()
1869 		ftt = read_iureg(pfpsd, nrs2, pregs, prw, &r2);  in vis_wrgsr()
1883 	pregs->r_pc = pregs->r_npc;	/* Do not retry emulated instruction. */  in vis_wrgsr()
1884 	pregs->r_npc += 4;  in vis_wrgsr()