Lines Matching refs:uint_t
48 uint_t aaa:5;
49 uint_t ramsel:3; /* Ram bank select. */
50 uint_t bbb:6;
51 uint_t eepromsel:2; /* Eeprom bank select. */
52 uint_t ccc:5;
53 uint_t burst64:3; /* Sbus Burst size, 64 bit mode. */
54 uint_t ddd:2;
55 uint_t parenable:1; /* Partity test enable. */
56 uint_t parsbus:1; /* Sbus Parity checking. */
57 uint_t sbusmode:1; /* Enhanced Sbus mode. */
58 uint_t sbusburst:3; /* Sbus burst size. */
95 uint_t aaa:29; /* Reserved. */
96 uint_t alignment_err:1; /* Soc Alignment Error. */
97 uint_t bad_size_err:1; /* Bad Size error. */
98 uint_t parity_err:1; /* Parity Error. */
116 uint_t comm_param:8; /* Communication Parameters. */
117 uint_t aaa:4;
118 uint_t socal_to_host:4; /* Soc to host attention. */
119 uint_t bbb:4;
120 uint_t host_to_socal:4; /* Host to soc+ attention. */
121 uint_t sae:1; /* Slave access error indicator. */
122 uint_t ccc:3;
123 uint_t int_pending:1; /* Interrupt Pending. */
124 uint_t nqcmd:1; /* Non queued command */
125 uint_t idle:1; /* SOC+ idle indicator. */
126 uint_t reset:1; /* Software Reset. */
179 uint_t reqq0_index:8;
180 uint_t reqq1_index:8;
181 uint_t reqq2_index:8;
182 uint_t reqq3_index:8;
204 uint_t rspq0_index:8;
205 uint_t rspq1_index:8;
206 uint_t rspq2_index:8;
207 uint_t rspq3_index:8;