Lines Matching refs:UINT64

548     UINT64                  Address;            /* Register Base Address */
564     UINT64                  BaseAddress;        /* 4K aligned base address */
565     UINT64                  EndAddress;         /* 4K aligned limit address */
596     UINT64                  BaseAddress;
864     UINT64                  MemoryProperties;       /* Memory access properties */
873     UINT64                  MemoryProperties;       /* Memory access properties */
887     UINT64                  BaseAddress;            /* SMMU base address */
888     UINT64                  Span;                   /* Length of memory range */
896     UINT64                  Interrupts[1];          /* Interrupt array */
915     UINT64                  BaseAddress;            /* SMMUv3 base address */
918     UINT64                  VatosAddress;
947     UINT64                  Reserved;
1005     UINT64                  BaseAddress;        /* IOMMU control registers */
1124     UINT64                  Reserved;
1125     UINT64                  StartAddress;
1126     UINT64                  MemoryLength;
1184     UINT64                  CounterFrequency;
1210     UINT64                  Address;            /* Base address, processor-relative */
1234     UINT64                  ProtocolData;
1431     UINT64                  LogAddress;         /* Address of the event log area */
1438     UINT64                  MinimumLogLength;   /* Minimum length for the event log area */
1439     UINT64                  LogAddress;         /* Address of the event log area */
1485     UINT64                  ControlAddress;