Lines Matching +full:ata +full:- +full:generic
43 #define PCI_CONF_SUBCLASS 0xA /* sub-class code, 1 byte */
175 #define PCI_STAT_FBBC 0x80 /* Fast Back-to-Back Capable */
202 #define PCI_CLASS_NONE 0x0 /* class code for pre-2.0 devices */
222 * PCI Sub-class codes - base class 0x0 (no new devices should use this code).
228 * PCI Sub-class codes - base class 0x1 (mass storage controllers)
235 #define PCI_MASS_ATA 0x5 /* ATA Controller */
236 #define PCI_MASS_SATA 0x6 /* Serial ATA */
251 * programming interface for ATA (subclass 5)
253 #define PCI_ATA_IF_SINGLE_DMA 0x20 /* ATA controller with single DMA */
254 #define PCI_ATA_IF_CHAINED_DMA 0x30 /* ATA controller with chained DMA */
257 * programming interface for ATA (subclass 6) for SATA
264 * programming interface for ATA (subclass 7) for SAS
270 * PCI Sub-class codes - base class 0x2 (Network controllers)
282 * PCI Sub-class codes - base class 03 (display controllers)
296 * PCI Sub-class codes - base class 0x4 (multi-media devices)
305 * PCI Sub-class codes - base class 0x5 (memory controllers)
312 * PCI Sub-class codes - base class 0x6 (Bridge devices)
322 #define PCI_BRIDGE_RACE 0x8 /* RACE-way Bridge */
323 #define PCI_BRIDGE_STPCI 0x9 /* Semi-transparent PCI/PCI Bridge */
329 * programming interface for Bridges class 0x6 (subclass 4) PCI-PCI bridge
331 #define PCI_BRIDGE_PCI_IF_PCI2PCI 0x0 /* PCI-PCI bridge */
343 * Semi-transparent PCI-to-PCI bridge
354 #define PCI_BRIDGE_AS_PORTAL_INTFC 0x1 /* ASI-SIG Portal Interface */
357 * PCI Sub-class codes - base class 0x7 (communication devices)
370 #define PCI_COMM_SERIAL_IF_GENERIC 0x0 /* Generic XT-compat serial */
371 #define PCI_COMM_SERIAL_IF_16450 0x1 /* 16450-compat serial ctrlr */
372 #define PCI_COMM_SERIAL_IF_16550 0x2 /* 16550-compat serial ctrlr */
373 #define PCI_COMM_SERIAL_IF_16650 0x3 /* 16650-compat serial ctrlr */
374 #define PCI_COMM_SERIAL_IF_16750 0x4 /* 16750-compat serial ctrlr */
375 #define PCI_COMM_SERIAL_IF_16850 0x5 /* 16850-compat serial ctrlr */
376 #define PCI_COMM_SERIAL_IF_16950 0x6 /* 16950-compat serial ctrlr */
381 #define PCI_COMM_PARALLEL_IF_GENERIC 0x0 /* Generic Parallel port */
382 #define PCI_COMM_PARALLEL_IF_BIDIRECT 0x1 /* Bi-directional Parallel */
390 #define PCI_COMM_MODEM_IF_GENERIC 0x0 /* Generic Modem */
391 #define PCI_COMM_MODEM_IF_HAYES_16450 0x1 /* Hayes 16450-compat Modem */
392 #define PCI_COMM_MODEM_IF_HAYES_16550 0x2 /* Hayes 16550-compat Modem */
393 #define PCI_COMM_MODEM_IF_HAYES_16650 0x3 /* Hayes 16650-compat Modem */
394 #define PCI_COMM_MODEM_IF_HAYES_16750 0x4 /* Hayes 16750-compat Modem */
397 * PCI Sub-class codes - base class 0x8
399 #define PCI_PERIPH_PIC 0x0 /* Generic PIC */
400 #define PCI_PERIPH_DMA 0x1 /* Generic DMA Controller */
401 #define PCI_PERIPH_TIMER 0x2 /* Generic System Timer Controller */
402 #define PCI_PERIPH_RTC 0x3 /* Generic RTC Controller */
403 #define PCI_PERIPH_HPC 0x4 /* Generic PCI Hot-Plug Controller */
411 #define PCI_PERIPH_PIC_IF_GENERIC 0x0 /* Generic 8259 APIC */
420 #define PCI_PERIPH_DMA_IF_GENERIC 0x0 /* Generic 8237 DMA ctrlr */
427 #define PCI_PERIPH_TIMER_IF_GENERIC 0x0 /* Generic 8254 system timer */
435 #define PCI_PERIPH_RTC_IF_GENERIC 0x0 /* Generic RTC controller */
439 * PCI Sub-class codes - base class 0x9
451 #define PCI_INPUT_GAMEPORT_IF_GENERIC 0x00 /* Generic controller */
455 * PCI Sub-class codes - base class 0xA
457 #define PCI_DOCK_GENERIC 0x00 /* Generic Docking Station */
461 * PCI Sub-class codes - base class 0xB
469 #define PCI_PROCESSOR_COPROC 0x40 /* Co-processor */
473 * PCI Sub-class codes - base class 0xC (Serial Controllers)
510 * PCI Sub-class codes - base class 0xD (Wireless controllers)
528 * PCI Sub-class codes - base class 0xE (Intelligent I/O controllers)
534 * PCI Sub-class codes - base class 0xF (Satellite Communication controllers)
543 * PCI Sub-class codes - base class 0x10 (Encryption/Decryption controllers)
550 * PCI Sub-class codes - base class 0x11 (Signal Processing controllers)
560 #define PCI_HEADER_MULTI 0x80 /* multi-function device */
576 #define PCI_BASE_TYPE_MEM 0x0 /* 32-bit memory address */
578 #define PCI_BASE_TYPE_ALL 0x4 /* 64-bit memory address */
608 #define PCI_CAP_ID_PCIX 0x7 /* PCI-X supported */
614 #define PCI_CAP_ID_P2P_SUBSYS 0xD /* PCI bridge Sub-system ID */
618 #define PCI_CAP_ID_MSI_X 0x11 /* MSI-X supported */
632 #define PCI_PMCSR_BSE 0x6 /* PCI-PCI bridge extensions, 1 byte */
636 * PM capabilities values - 2 bytes
643 #define PCI_PMCAP_AUX_CUR_SELF 0x0 /* 0 aux current - self powered */
662 * PM control/status values - 2 bytes
688 * PM PMCSR PCI to PCI bridge support extension values - 1 byte
690 #define PCI_PMCSR_BSE_B2_B3 0x40 /* bridge D3hot -> secondary B2 */
694 * PCI-X capability related definitions
704 * PCI-X bridge capability related definitions
760 * PCI-X Command Encoding
904 * PCI Message Signalled Interrupts (MSI) capability entry offsets for 32-bit
907 #define PCI_MSI_ADDR_OFFSET 0x04 /* MSI 32-bit msg address, 4 bytes */
908 #define PCI_MSI_32BIT_DATA 0x08 /* MSI 32-bit msg data, 2 bytes */
909 #define PCI_MSI_32BIT_MASK 0x0C /* MSI 32-bit mask bits, 4 bytes */
910 #define PCI_MSI_32BIT_PENDING 0x10 /* MSI 32-bit pending bits, 4 bytes */
913 * PCI Message Signalled Interrupts (MSI) capability entry offsets for 64-bit
915 #define PCI_MSI_64BIT_DATA 0x0C /* MSI 64-bit msg data, 2 bytes */
916 #define PCI_MSI_64BIT_MASKBITS 0x10 /* MSI 64-bit mask bits, 4 bytes */
917 #define PCI_MSI_64BIT_PENDING 0x14 /* MSI 64-bit pending bits, 4 bytes */
931 * PCI Extended Message Signalled Interrupts (MSI-X) capability entry offsets
933 #define PCI_MSIX_CTRL 0x02 /* MSI-X control register, 2 bytes */
934 #define PCI_MSIX_TBL_OFFSET 0x04 /* MSI-X table offset, 4 bytes */
935 #define PCI_MSIX_TBL_BIR_MASK 0x0007 /* MSI-X table BIR mask */
936 #define PCI_MSIX_PBA_OFFSET 0x08 /* MSI-X pending bit array, 4 bytes */
937 #define PCI_MSIX_PBA_BIR_MASK 0x0007 /* MSI-X PBA BIR mask */
939 #define PCI_MSIX_TBL_SIZE_MASK 0x07FF /* table size mask in MSI-X ctrl reg */
940 #define PCI_MSIX_FUNCTION_MASK 0x4000 /* function mask in MSI-X ctrl reg */
941 #define PCI_MSIX_ENABLE_BIT 0x8000 /* MSI-X enable mask in MSI-X ctl reg */
943 #define PCI_MSIX_LOWER_ADDR_OFFSET 0 /* MSI-X lower addr offset */
944 #define PCI_MSIX_UPPER_ADDR_OFFSET 4 /* MSI-X upper addr offset */
945 #define PCI_MSIX_DATA_OFFSET 8 /* MSI-X data offset */
946 #define PCI_MSIX_VECTOR_CTRL_OFFSET 12 /* MSI-X vector ctrl offset */
947 #define PCI_MSIX_VECTOR_SIZE 16 /* MSI-X size of each vector */
953 #define PCI_MSIX_MAX_INTRS 2048 /* maximum MSI-X interrupts supported */
969 * PCI_CAP_ID_HT. The header's upper 16-bits (command reg) contains an HT
1094 * property of a pci-pci bridge device node.
1109 * "assigned-addresses" property for a PCI node. For the "reg" property, it
1111 * windows. For the "assigned-addresses" property, it denotes an assigned
1126 * t is 1 if the address is aliased (for non-relocatable I/O), below
1129 * bbbbbbbb is the 8-bit bus number
1130 * ddddd is the 5-bit device number
1131 * fff is the 3-bit function number
1132 * rrrrrrrr is the 8-bit register number
1133 * should be zero for non-relocatable, when ss is 01, or 10
1134 * hh...hhh is the 32-bit unsigned number
1135 * ll...lll is the 32-bit unsigned number
1142 * hh...hhh is the 32-bit unsigned number
1143 * ll...lll is the 32-bit unsigned number
1188 #define PCI_ADDR_MEM32 0x02000000 /* 32-bit memory address */
1189 #define PCI_ADDR_MEM64 0x03000000 /* 64-bit memory address */
1192 #define PCI_RELOCAT_B PCI_REG_REL_M /* non-relocatable bit */
1195 #define PCI_HARDDEC_8514 2 /* number of reg entries for 8514 hard-decode */
1196 #define PCI_HARDDEC_VGA 3 /* number of reg entries for VGA hard-decode */
1197 #define PCI_HARDDEC_IDE 4 /* number of reg entries for IDE hard-decode */
1226 #define PCI_PDS_CODE_TYPE_PCAT 0x0 /* Intel x86/PC-AT Type */
1234 #define PCI_DEV_CONF_MAP_PROP "pci-parent-indirect"
1242 #define PCI_BUS_CONF_MAP_PROP "pci-conf-indirect"