Lines Matching refs:dev
277 yge_dev_t *dev = port->p_dev; in yge_mii_readreg() local
281 GMAC_WRITE_2(dev, pnum, GM_SMI_CTRL, in yge_mii_readreg()
286 val = GMAC_READ_2(dev, pnum, GM_SMI_CTRL); in yge_mii_readreg()
288 val = GMAC_READ_2(dev, pnum, GM_SMI_DATA); in yge_mii_readreg()
306 yge_dev_t *dev = port->p_dev; in yge_mii_writereg() local
309 GMAC_WRITE_2(dev, pnum, GM_SMI_DATA, val); in yge_mii_writereg()
310 GMAC_WRITE_2(dev, pnum, GM_SMI_CTRL, in yge_mii_writereg()
315 if ((GMAC_READ_2(dev, pnum, GM_SMI_CTRL) & GM_SMI_CT_BUSY) == 0) in yge_mii_writereg()
352 yge_dev_t *dev = port->p_dev; in yge_mii_notify() local
363 DEV_LOCK(dev); in yge_mii_notify()
368 CSR_WRITE_1(dev, MR_ADDR(port->p_port, GMAC_IRQ_MSK), in yge_mii_notify()
418 GMAC_WRITE_2(dev, port->p_port, GM_GP_CTRL, gpcr); in yge_mii_notify()
421 (void) GMAC_READ_2(dev, port->p_port, GM_GP_CTRL); in yge_mii_notify()
424 CSR_WRITE_4(dev, MR_ADDR(port->p_port, GMAC_CTRL), gmac); in yge_mii_notify()
428 gpcr = GMAC_READ_2(dev, port->p_port, GM_GP_CTRL); in yge_mii_notify()
430 GMAC_WRITE_2(dev, port->p_port, GM_GP_CTRL, gpcr); in yge_mii_notify()
433 (void) GMAC_READ_2(dev, port->p_port, GM_GP_CTRL); in yge_mii_notify()
436 DEV_UNLOCK(dev); in yge_mii_notify()
448 yge_dev_t *dev; in yge_setrxfilt() local
454 dev = port->p_dev; in yge_setrxfilt()
459 if (dev->d_suspended) in yge_setrxfilt()
464 GMAC_WRITE_2(dev, pnum, GM_SRC_ADDR_1L + i * 4, in yge_setrxfilt()
468 GMAC_WRITE_2(dev, pnum, GM_SRC_ADDR_2L + i * 4, in yge_setrxfilt()
473 mode = GMAC_READ_2(dev, pnum, GM_RX_CTRL); in yge_setrxfilt()
480 GMAC_WRITE_2(dev, pnum, GM_MC_ADDR_H1, mchash[0] & 0xffff); in yge_setrxfilt()
481 GMAC_WRITE_2(dev, pnum, GM_MC_ADDR_H2, (mchash[0] >> 16) & 0xffff); in yge_setrxfilt()
482 GMAC_WRITE_2(dev, pnum, GM_MC_ADDR_H3, mchash[1] & 0xffff); in yge_setrxfilt()
483 GMAC_WRITE_2(dev, pnum, GM_MC_ADDR_H4, (mchash[1] >> 16) & 0xffff); in yge_setrxfilt()
485 GMAC_WRITE_2(dev, pnum, GM_RX_CTRL, mode); in yge_setrxfilt()
536 yge_setup_rambuffer(yge_dev_t *dev) in yge_setup_rambuffer() argument
542 dev->d_ramsize = CSR_READ_1(dev, B2_E_0) * 4; in yge_setup_rambuffer()
543 if (dev->d_ramsize == 0) in yge_setup_rambuffer()
546 dev->d_pflags |= PORT_FLAG_RAMBUF; in yge_setup_rambuffer()
552 dev->d_rxqsize = (((dev->d_ramsize * 1024 * 2) / 3) & ~(1024 - 1)); in yge_setup_rambuffer()
553 dev->d_txqsize = (dev->d_ramsize * 1024) - dev->d_rxqsize; in yge_setup_rambuffer()
555 for (i = 0, next = 0; i < dev->d_num_port; i++) { in yge_setup_rambuffer()
556 dev->d_rxqstart[i] = next; in yge_setup_rambuffer()
557 dev->d_rxqend[i] = next + dev->d_rxqsize - 1; in yge_setup_rambuffer()
558 next = dev->d_rxqend[i] + 1; in yge_setup_rambuffer()
559 dev->d_txqstart[i] = next; in yge_setup_rambuffer()
560 dev->d_txqend[i] = next + dev->d_txqsize - 1; in yge_setup_rambuffer()
561 next = dev->d_txqend[i] + 1; in yge_setup_rambuffer()
566 yge_phy_power(yge_dev_t *dev, boolean_t powerup) in yge_phy_power() argument
573 CSR_WRITE_1(dev, B0_POWER_CTRL, in yge_phy_power()
576 CSR_WRITE_4(dev, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); in yge_phy_power()
579 if (dev->d_hw_id == CHIP_ID_YUKON_XL && in yge_phy_power()
580 dev->d_hw_rev > CHIP_REV_YU_XL_A1) { in yge_phy_power()
589 CSR_WRITE_1(dev, B2_Y2_CLK_GATE, val); in yge_phy_power()
591 val = pci_config_get32(dev->d_pcih, PCI_OUR_REG_1); in yge_phy_power()
593 if (dev->d_hw_id == CHIP_ID_YUKON_XL && in yge_phy_power()
594 dev->d_hw_rev > CHIP_REV_YU_XL_A1) { in yge_phy_power()
597 if (dev->d_num_port > 1) in yge_phy_power()
602 pci_config_put32(dev->d_pcih, PCI_OUR_REG_1, val); in yge_phy_power()
604 switch (dev->d_hw_id) { in yge_phy_power()
610 CSR_WRITE_2(dev, B0_CTST, Y2_HW_WOL_OFF); in yge_phy_power()
613 pci_config_put32(dev->d_pcih, PCI_OUR_REG_3, 0); in yge_phy_power()
615 our = pci_config_get32(dev->d_pcih, PCI_OUR_REG_4); in yge_phy_power()
619 pci_config_put32(dev->d_pcih, PCI_OUR_REG_4, our); in yge_phy_power()
622 our = pci_config_get32(dev->d_pcih, PCI_OUR_REG_5); in yge_phy_power()
624 pci_config_put32(dev->d_pcih, PCI_OUR_REG_5, our); in yge_phy_power()
626 pci_config_put32(dev->d_pcih, PCI_OUR_REG_1, 0); in yge_phy_power()
632 our = CSR_READ_4(dev, B2_GP_IO); in yge_phy_power()
634 CSR_WRITE_4(dev, B2_GP_IO, our); in yge_phy_power()
636 (void) CSR_READ_4(dev, B2_GP_IO); in yge_phy_power()
643 for (i = 0; i < dev->d_num_port; i++) { in yge_phy_power()
644 CSR_WRITE_2(dev, MR_ADDR(i, GMAC_LINK_CTRL), in yge_phy_power()
646 CSR_WRITE_2(dev, MR_ADDR(i, GMAC_LINK_CTRL), in yge_phy_power()
650 val = pci_config_get32(dev->d_pcih, PCI_OUR_REG_1); in yge_phy_power()
651 if (dev->d_hw_id == CHIP_ID_YUKON_XL && in yge_phy_power()
652 dev->d_hw_rev > CHIP_REV_YU_XL_A1) { in yge_phy_power()
654 if (dev->d_num_port > 1) in yge_phy_power()
660 pci_config_put32(dev->d_pcih, PCI_OUR_REG_1, val); in yge_phy_power()
665 if (dev->d_hw_id == CHIP_ID_YUKON_XL && in yge_phy_power()
666 dev->d_hw_rev > CHIP_REV_YU_XL_A1) { in yge_phy_power()
674 CSR_WRITE_1(dev, B2_Y2_CLK_GATE, val); in yge_phy_power()
675 CSR_WRITE_1(dev, B0_POWER_CTRL, in yge_phy_power()
681 yge_reset(yge_dev_t *dev) in yge_reset() argument
687 ddi_acc_handle_t pcih = dev->d_pcih; in yge_reset()
690 if (dev->d_hw_id == CHIP_ID_YUKON_EX) { in yge_reset()
691 status = CSR_READ_2(dev, B28_Y2_ASF_STAT_CMD); in yge_reset()
697 CSR_WRITE_2(dev, B28_Y2_ASF_STAT_CMD, status); in yge_reset()
699 CSR_WRITE_1(dev, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); in yge_reset()
701 CSR_WRITE_2(dev, B0_CTST, Y2_ASF_DISABLE); in yge_reset()
706 CSR_WRITE_1(dev, B0_CTST, CS_RST_SET); in yge_reset()
707 CSR_WRITE_1(dev, B0_CTST, CS_RST_CLR); in yge_reset()
710 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON); in yge_reset()
714 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON); in yge_reset()
720 CSR_WRITE_1(dev, B0_CTST, CS_MRST_CLR); in yge_reset()
722 switch (dev->d_bustype) { in yge_reset()
725 CSR_PCI_WRITE_4(dev, Y2_CFG_AER + AER_UNCOR_ERR, 0xffffffff); in yge_reset()
728 val = CSR_PCI_READ_4(dev, PEX_UNC_ERR_STAT); in yge_reset()
730 dev->d_intrmask &= ~Y2_IS_HW_ERR; in yge_reset()
731 dev->d_intrhwemask &= ~Y2_IS_PCI_EXP; in yge_reset()
752 yge_phy_power(dev, B_TRUE); in yge_reset()
755 for (i = 0; i < dev->d_num_port; i++) { in yge_reset()
757 CSR_WRITE_4(dev, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); in yge_reset()
758 CSR_WRITE_4(dev, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); in yge_reset()
760 CSR_WRITE_4(dev, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); in yge_reset()
761 CSR_WRITE_4(dev, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); in yge_reset()
762 if (dev->d_hw_id == CHIP_ID_YUKON_EX || in yge_reset()
763 dev->d_hw_id == CHIP_ID_YUKON_SUPR) { in yge_reset()
764 CSR_WRITE_2(dev, MR_ADDR(i, GMAC_CTRL), in yge_reset()
768 CSR_WRITE_2(dev, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); in yge_reset()
771 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in yge_reset()
774 CSR_WRITE_2(dev, B0_CTST, Y2_LED_STAT_ON); in yge_reset()
777 CSR_WRITE_4(dev, B2_I2C_IRQ, I2C_CLR_IRQ); in yge_reset()
780 CSR_WRITE_1(dev, B2_TI_CTRL, TIM_STOP); in yge_reset()
781 CSR_WRITE_1(dev, B2_TI_CTRL, TIM_CLR_IRQ); in yge_reset()
784 CSR_WRITE_1(dev, B28_DPT_CTRL, DPT_STOP); in yge_reset()
787 CSR_WRITE_1(dev, GMAC_TI_ST_CTRL, GMT_ST_STOP); in yge_reset()
788 CSR_WRITE_1(dev, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); in yge_reset()
791 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in yge_reset()
794 for (i = 0; i < dev->d_num_port; i++) in yge_reset()
795 CSR_WRITE_1(dev, MR_ADDR(i, TXA_CTRL), TXA_ENA_ARB); in yge_reset()
798 for (i = 0; i < dev->d_num_port; i++) { in yge_reset()
799 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); in yge_reset()
801 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), RI_TO_53); in yge_reset()
802 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), RI_TO_53); in yge_reset()
803 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), RI_TO_53); in yge_reset()
804 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), RI_TO_53); in yge_reset()
805 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), RI_TO_53); in yge_reset()
806 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), RI_TO_53); in yge_reset()
807 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), RI_TO_53); in yge_reset()
808 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), RI_TO_53); in yge_reset()
809 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), RI_TO_53); in yge_reset()
810 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), RI_TO_53); in yge_reset()
811 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), RI_TO_53); in yge_reset()
812 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), RI_TO_53); in yge_reset()
816 CSR_WRITE_4(dev, B0_HWE_IMSK, 0); in yge_reset()
817 (void) CSR_READ_4(dev, B0_HWE_IMSK); in yge_reset()
818 CSR_WRITE_4(dev, B0_IMSK, 0); in yge_reset()
819 (void) CSR_READ_4(dev, B0_IMSK); in yge_reset()
825 if (dev->d_bustype == PCIX_BUS && dev->d_num_port > 1) { in yge_reset()
829 if ((pcix = yge_find_capability(dev, PCI_CAP_ID_PCIX)) != 0) { in yge_reset()
833 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON); in yge_reset()
835 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in yge_reset()
838 if (dev->d_bustype == PEX_BUS) { in yge_reset()
851 yge_error(dev, NULL, in yge_reset()
857 CLEARRING(&dev->d_status_ring); in yge_reset()
858 SYNCRING(&dev->d_status_ring, DDI_DMA_SYNC_FORDEV); in yge_reset()
860 dev->d_stat_cons = 0; in yge_reset()
862 CSR_WRITE_4(dev, STAT_CTRL, SC_STAT_RST_SET); in yge_reset()
863 CSR_WRITE_4(dev, STAT_CTRL, SC_STAT_RST_CLR); in yge_reset()
866 addr = dev->d_status_ring.r_paddr; in yge_reset()
867 CSR_WRITE_4(dev, STAT_LIST_ADDR_LO, YGE_ADDR_LO(addr)); in yge_reset()
868 CSR_WRITE_4(dev, STAT_LIST_ADDR_HI, YGE_ADDR_HI(addr)); in yge_reset()
871 CSR_WRITE_2(dev, STAT_LAST_IDX, YGE_STAT_RING_CNT - 1); in yge_reset()
872 CSR_WRITE_2(dev, STAT_PUT_IDX, 0); in yge_reset()
874 if (dev->d_hw_id == CHIP_ID_YUKON_EC && in yge_reset()
875 dev->d_hw_rev == CHIP_REV_YU_EC_A1) { in yge_reset()
877 CSR_WRITE_2(dev, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); in yge_reset()
879 CSR_WRITE_1(dev, STAT_FIFO_WM, 0x21); in yge_reset()
880 CSR_WRITE_1(dev, STAT_FIFO_ISR_WM, 7); in yge_reset()
882 CSR_WRITE_2(dev, STAT_TX_IDX_TH, 10); in yge_reset()
883 CSR_WRITE_1(dev, STAT_FIFO_WM, 16); in yge_reset()
886 if (dev->d_hw_id == CHIP_ID_YUKON_XL && in yge_reset()
887 dev->d_hw_rev == CHIP_REV_YU_XL_A0) in yge_reset()
888 CSR_WRITE_1(dev, STAT_FIFO_ISR_WM, 4); in yge_reset()
890 CSR_WRITE_1(dev, STAT_FIFO_ISR_WM, 16); in yge_reset()
892 CSR_WRITE_4(dev, STAT_ISR_TIMER_INI, 0x0190); in yge_reset()
898 CSR_WRITE_4(dev, STAT_TX_TIMER_INI, YGE_USECS(dev, 1000)); in yge_reset()
901 CSR_WRITE_4(dev, STAT_CTRL, SC_STAT_OP_ON); in yge_reset()
903 CSR_WRITE_1(dev, STAT_TX_TIMER_CTRL, TIM_START); in yge_reset()
904 CSR_WRITE_1(dev, STAT_LEV_TIMER_CTRL, TIM_START); in yge_reset()
905 CSR_WRITE_1(dev, STAT_ISR_TIMER_CTRL, TIM_START); in yge_reset()
911 yge_dev_t *dev = port->p_dev; in yge_init_port() local
915 port->p_flags = dev->d_pflags; in yge_init_port()
916 port->p_ppa = ddi_get_instance(dev->d_dip) + (port->p_port * 100); in yge_init_port()
935 if (dev->d_hw_id == CHIP_ID_YUKON_FE) in yge_init_port()
947 port->p_mii = mii_alloc(port, dev->d_dip, &yge_mii_ops); in yge_init_port()
966 CSR_READ_1(dev, B2_MAC_1 + (port->p_port * 8) + i); in yge_init_port()
976 macp->m_dip = dev->d_dip; in yge_init_port()
990 yge_add_intr(yge_dev_t *dev, int intr_type) in yge_add_intr() argument
998 dip = dev->d_dip; in yge_add_intr()
1002 yge_error(dev, NULL, in yge_add_intr()
1014 dev->d_intrcnt = 1; in yge_add_intr()
1016 dev->d_intrsize = count * sizeof (ddi_intr_handle_t); in yge_add_intr()
1017 dev->d_intrh = kmem_zalloc(dev->d_intrsize, KM_SLEEP); in yge_add_intr()
1018 if (dev->d_intrh == NULL) { in yge_add_intr()
1019 yge_error(dev, NULL, "Unable to allocate interrupt handle"); in yge_add_intr()
1023 rv = ddi_intr_alloc(dip, dev->d_intrh, intr_type, 0, dev->d_intrcnt, in yge_add_intr()
1026 yge_error(dev, NULL, in yge_add_intr()
1029 kmem_free(dev->d_intrh, dev->d_intrsize); in yge_add_intr()
1033 if ((rv = ddi_intr_get_pri(dev->d_intrh[0], &dev->d_intrpri)) != in yge_add_intr()
1035 for (i = 0; i < dev->d_intrcnt; i++) in yge_add_intr()
1036 (void) ddi_intr_free(dev->d_intrh[i]); in yge_add_intr()
1037 yge_error(dev, NULL, in yge_add_intr()
1039 kmem_free(dev->d_intrh, dev->d_intrsize); in yge_add_intr()
1043 if ((rv = ddi_intr_get_cap(dev->d_intrh[0], &dev->d_intrcap)) != in yge_add_intr()
1045 yge_error(dev, NULL, in yge_add_intr()
1047 for (i = 0; i < dev->d_intrcnt; i++) in yge_add_intr()
1048 (void) ddi_intr_free(dev->d_intrh[i]); in yge_add_intr()
1049 kmem_free(dev->d_intrh, dev->d_intrsize); in yge_add_intr()
1054 for (i = 0; i < dev->d_intrcnt; i++) { in yge_add_intr()
1055 if ((rv = ddi_intr_add_handler(dev->d_intrh[i], yge_intr, in yge_add_intr()
1056 dev, NULL)) != DDI_SUCCESS) { in yge_add_intr()
1057 yge_error(dev, NULL, in yge_add_intr()
1060 (void) ddi_intr_remove_handler(dev->d_intrh[j]); in yge_add_intr()
1061 for (i = 0; i < dev->d_intrcnt; i++) in yge_add_intr()
1062 (void) ddi_intr_free(dev->d_intrh[i]); in yge_add_intr()
1063 kmem_free(dev->d_intrh, dev->d_intrsize); in yge_add_intr()
1068 mutex_init(&dev->d_rxlock, NULL, MUTEX_DRIVER, in yge_add_intr()
1069 DDI_INTR_PRI(dev->d_intrpri)); in yge_add_intr()
1070 mutex_init(&dev->d_txlock, NULL, MUTEX_DRIVER, in yge_add_intr()
1071 DDI_INTR_PRI(dev->d_intrpri)); in yge_add_intr()
1072 mutex_init(&dev->d_phylock, NULL, MUTEX_DRIVER, in yge_add_intr()
1073 DDI_INTR_PRI(dev->d_intrpri)); in yge_add_intr()
1074 mutex_init(&dev->d_task_mtx, NULL, MUTEX_DRIVER, in yge_add_intr()
1075 DDI_INTR_PRI(dev->d_intrpri)); in yge_add_intr()
1081 yge_attach_intr(yge_dev_t *dev) in yge_attach_intr() argument
1083 dev_info_t *dip = dev->d_dip; in yge_attach_intr()
1090 yge_error(dev, NULL, in yge_attach_intr()
1108 if ((rv = yge_add_intr(dev, DDI_INTR_TYPE_MSIX)) == in yge_attach_intr()
1114 if ((rv = yge_add_intr(dev, DDI_INTR_TYPE_MSI)) == in yge_attach_intr()
1120 if ((rv = yge_add_intr(dev, DDI_INTR_TYPE_FIXED)) == in yge_attach_intr()
1125 yge_error(dev, NULL, "Unable to configure any interrupts"); in yge_attach_intr()
1130 yge_intr_enable(yge_dev_t *dev) in yge_intr_enable() argument
1133 if (dev->d_intrcap & DDI_INTR_FLAG_BLOCK) { in yge_intr_enable()
1135 (void) ddi_intr_block_enable(dev->d_intrh, dev->d_intrcnt); in yge_intr_enable()
1138 for (i = 0; i < dev->d_intrcnt; i++) in yge_intr_enable()
1139 (void) ddi_intr_enable(dev->d_intrh[i]); in yge_intr_enable()
1144 yge_intr_disable(yge_dev_t *dev) in yge_intr_disable() argument
1148 if (dev->d_intrcap & DDI_INTR_FLAG_BLOCK) { in yge_intr_disable()
1149 (void) ddi_intr_block_disable(dev->d_intrh, dev->d_intrcnt); in yge_intr_disable()
1151 for (i = 0; i < dev->d_intrcnt; i++) in yge_intr_disable()
1152 (void) ddi_intr_disable(dev->d_intrh[i]); in yge_intr_disable()
1157 yge_find_capability(yge_dev_t *dev, uint8_t cap) in yge_find_capability() argument
1161 ddi_acc_handle_t pcih = dev->d_pcih; in yge_find_capability()
1179 yge_attach(yge_dev_t *dev) in yge_attach() argument
1181 dev_info_t *dip = dev->d_dip; in yge_attach()
1186 if (pci_config_setup(dip, &dev->d_pcih) != DDI_SUCCESS) { in yge_attach()
1187 yge_error(dev, NULL, "Unable to map PCI configuration space"); in yge_attach()
1196 pm_cap = yge_find_capability(dev, PCI_CAP_ID_PM); in yge_attach()
1199 pmcsr = pci_config_get16(dev->d_pcih, pm_cap + PCI_PMCSR); in yge_attach()
1201 pci_config_put16(dev->d_pcih, pm_cap + PCI_PMCSR, in yge_attach()
1206 pci_config_put16(dev->d_pcih, PCI_CONF_COMM, in yge_attach()
1207 pci_config_get16(dev->d_pcih, PCI_CONF_COMM) | in yge_attach()
1212 rv = ddi_regs_map_setup(dip, 1, &dev->d_regs, 0, 0, &yge_regs_attr, in yge_attach()
1213 &dev->d_regsh); in yge_attach()
1215 yge_error(dev, NULL, "Unable to map device registers"); in yge_attach()
1221 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON); in yge_attach()
1222 pci_config_put32(dev->d_pcih, PCI_OUR_REG_3, 0); in yge_attach()
1223 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in yge_attach()
1225 CSR_WRITE_2(dev, B0_CTST, CS_RST_CLR); in yge_attach()
1226 dev->d_hw_id = CSR_READ_1(dev, B2_CHIP_ID); in yge_attach()
1227 dev->d_hw_rev = (CSR_READ_1(dev, B2_MAC_CFG) >> 4) & 0x0f; in yge_attach()
1236 if (dev->d_hw_id < CHIP_ID_YUKON_XL || in yge_attach()
1237 dev->d_hw_id >= CHIP_ID_YUKON_UL_2) { in yge_attach()
1238 yge_error(dev, NULL, "Unknown device: id=0x%02x, rev=0x%02x", in yge_attach()
1239 dev->d_hw_id, dev->d_hw_rev); in yge_attach()
1246 CSR_WRITE_2(dev, B0_CTST, CS_RST_SET); in yge_attach()
1247 CSR_WRITE_2(dev, B0_CTST, CS_RST_CLR); in yge_attach()
1248 dev->d_pmd = CSR_READ_1(dev, B2_PMD_TYP); in yge_attach()
1249 if (dev->d_pmd == 'L' || dev->d_pmd == 'S' || dev->d_pmd == 'P') in yge_attach()
1250 dev->d_coppertype = 0; in yge_attach()
1252 dev->d_coppertype = 1; in yge_attach()
1254 dev->d_num_port = 1; in yge_attach()
1255 if ((CSR_READ_1(dev, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == in yge_attach()
1257 if (!(CSR_READ_1(dev, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) in yge_attach()
1258 dev->d_num_port++; in yge_attach()
1262 if (yge_find_capability(dev, PCI_CAP_ID_PCI_E) != 0) { in yge_attach()
1263 dev->d_bustype = PEX_BUS; in yge_attach()
1264 } else if (yge_find_capability(dev, PCI_CAP_ID_PCIX) != 0) { in yge_attach()
1265 dev->d_bustype = PCIX_BUS; in yge_attach()
1267 dev->d_bustype = PCI_BUS; in yge_attach()
1270 switch (dev->d_hw_id) { in yge_attach()
1272 dev->d_clock = 125; /* 125 Mhz */ in yge_attach()
1275 dev->d_clock = 125; /* 125 Mhz */ in yge_attach()
1278 dev->d_clock = 125; /* 125 Mhz */ in yge_attach()
1281 dev->d_clock = 125; /* 125 Mhz */ in yge_attach()
1284 dev->d_clock = 125; /* 125 Mhz */ in yge_attach()
1287 dev->d_clock = 100; /* 100 Mhz */ in yge_attach()
1290 dev->d_clock = 50; /* 50 Mhz */ in yge_attach()
1293 dev->d_clock = 156; /* 156 Mhz */ in yge_attach()
1296 dev->d_clock = 156; /* 156 Mhz */ in yge_attach()
1300 dev->d_process_limit = YGE_RX_RING_CNT/2; in yge_attach()
1302 rv = yge_alloc_ring(NULL, dev, &dev->d_status_ring, YGE_STAT_RING_CNT); in yge_attach()
1307 dev->d_task_q = ddi_taskq_create(dip, "tq", 1, TASKQ_DEFAULTPRI, 0); in yge_attach()
1308 if (dev->d_task_q == NULL) { in yge_attach()
1309 yge_error(dev, NULL, "failed to create taskq"); in yge_attach()
1314 cv_init(&dev->d_task_cv, NULL, CV_DRIVER, NULL); in yge_attach()
1317 if ((rv = yge_attach_intr(dev)) != DDI_SUCCESS) { in yge_attach()
1322 dev->d_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; in yge_attach()
1323 dev->d_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | in yge_attach()
1327 yge_reset(dev); in yge_attach()
1329 yge_setup_rambuffer(dev); in yge_attach()
1332 for (int i = 0; i < dev->d_num_port; i++) { in yge_attach()
1333 yge_port_t *port = dev->d_port[i]; in yge_attach()
1339 yge_intr_enable(dev); in yge_attach()
1342 dev->d_periodic = ddi_periodic_add(yge_tick, dev, 1000000000, 0); in yge_attach()
1344 for (int i = 0; i < dev->d_num_port; i++) { in yge_attach()
1345 yge_port_t *port = dev->d_port[i]; in yge_attach()
1356 if (ddi_taskq_dispatch(dev->d_task_q, yge_task, dev, DDI_SLEEP) != in yge_attach()
1358 yge_error(dev, NULL, "failed to start taskq"); in yge_attach()
1367 yge_detach(dev); in yge_attach()
1408 yge_detach(yge_dev_t *dev) in yge_detach() argument
1413 if (dev->d_periodic) in yge_detach()
1414 ddi_periodic_delete(dev->d_periodic); in yge_detach()
1416 for (int i = 0; i < dev->d_num_port; i++) { in yge_detach()
1417 yge_uninit_port(dev->d_port[i]); in yge_detach()
1423 CSR_WRITE_4(dev, B0_IMSK, 0); in yge_detach()
1424 (void) CSR_READ_4(dev, B0_IMSK); in yge_detach()
1425 CSR_WRITE_4(dev, B0_HWE_IMSK, 0); in yge_detach()
1426 (void) CSR_READ_4(dev, B0_HWE_IMSK); in yge_detach()
1429 CSR_WRITE_2(dev, B0_CTST, Y2_LED_STAT_OFF); in yge_detach()
1432 CSR_WRITE_2(dev, B0_CTST, CS_RST_SET); in yge_detach()
1434 yge_free_ring(&dev->d_status_ring); in yge_detach()
1436 if (dev->d_task_q != NULL) { in yge_detach()
1437 yge_dispatch(dev, YGE_TASK_EXIT); in yge_detach()
1438 ddi_taskq_destroy(dev->d_task_q); in yge_detach()
1439 dev->d_task_q = NULL; in yge_detach()
1442 cv_destroy(&dev->d_task_cv); in yge_detach()
1444 yge_intr_disable(dev); in yge_detach()
1446 if (dev->d_intrh != NULL) { in yge_detach()
1447 for (int i = 0; i < dev->d_intrcnt; i++) { in yge_detach()
1448 (void) ddi_intr_remove_handler(dev->d_intrh[i]); in yge_detach()
1449 (void) ddi_intr_free(dev->d_intrh[i]); in yge_detach()
1451 kmem_free(dev->d_intrh, dev->d_intrsize); in yge_detach()
1452 mutex_destroy(&dev->d_phylock); in yge_detach()
1453 mutex_destroy(&dev->d_txlock); in yge_detach()
1454 mutex_destroy(&dev->d_rxlock); in yge_detach()
1455 mutex_destroy(&dev->d_task_mtx); in yge_detach()
1457 if (dev->d_regsh != NULL) in yge_detach()
1458 ddi_regs_map_free(&dev->d_regsh); in yge_detach()
1460 if (dev->d_pcih != NULL) in yge_detach()
1461 pci_config_teardown(&dev->d_pcih); in yge_detach()
1465 yge_alloc_ring(yge_port_t *port, yge_dev_t *dev, yge_ring_t *ring, uint32_t num) in yge_alloc_ring() argument
1474 if (port && !dev) in yge_alloc_ring()
1475 dev = port->p_dev; in yge_alloc_ring()
1476 dip = dev->d_dip; in yge_alloc_ring()
1483 yge_error(dev, port, "Unable to allocate ring DMA handle"); in yge_alloc_ring()
1491 yge_error(dev, port, "Unable to allocate ring DMA memory"); in yge_alloc_ring()
1503 yge_error(dev, port, "Unable to bind ring DMA handle"); in yge_alloc_ring()
1530 yge_dev_t *dev = port->p_dev; in yge_alloc_buf() local
1540 rv = ddi_dma_alloc_handle(dev->d_dip, &yge_buf_dma_attr, in yge_alloc_buf()
1708 yge_suspend(yge_dev_t *dev) in yge_suspend() argument
1710 for (int i = 0; i < dev->d_num_port; i++) { in yge_suspend()
1711 yge_port_t *port = dev->d_port[i]; in yge_suspend()
1716 DEV_LOCK(dev); in yge_suspend()
1718 for (int i = 0; i < dev->d_num_port; i++) { in yge_suspend()
1719 yge_port_t *port = dev->d_port[i]; in yge_suspend()
1727 CSR_WRITE_4(dev, B0_IMSK, 0); in yge_suspend()
1728 (void) CSR_READ_4(dev, B0_IMSK); in yge_suspend()
1729 CSR_WRITE_4(dev, B0_HWE_IMSK, 0); in yge_suspend()
1730 (void) CSR_READ_4(dev, B0_HWE_IMSK); in yge_suspend()
1732 yge_phy_power(dev, B_FALSE); in yge_suspend()
1735 CSR_WRITE_2(dev, B0_CTST, CS_RST_SET); in yge_suspend()
1736 dev->d_suspended = B_TRUE; in yge_suspend()
1738 DEV_UNLOCK(dev); in yge_suspend()
1744 yge_resume(yge_dev_t *dev) in yge_resume() argument
1748 DEV_LOCK(dev); in yge_resume()
1751 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON); in yge_resume()
1753 if ((pm_cap = yge_find_capability(dev, PCI_CAP_ID_PM)) != 0) { in yge_resume()
1755 pmcsr = pci_config_get16(dev->d_pcih, pm_cap + PCI_PMCSR); in yge_resume()
1757 pci_config_put16(dev->d_pcih, pm_cap + PCI_PMCSR, in yge_resume()
1762 pci_config_put16(dev->d_pcih, PCI_CONF_COMM, in yge_resume()
1763 pci_config_get16(dev->d_pcih, PCI_CONF_COMM) | in yge_resume()
1767 switch (dev->d_hw_id) { in yge_resume()
1771 pci_config_put32(dev->d_pcih, PCI_OUR_REG_3, 0); in yge_resume()
1775 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in yge_resume()
1777 yge_reset(dev); in yge_resume()
1780 CSR_WRITE_4(dev, B0_IMSK, 0); in yge_resume()
1781 CSR_WRITE_4(dev, B0_IMSK, Y2_IS_HW_ERR | Y2_IS_STAT_BMU); in yge_resume()
1782 CSR_WRITE_4(dev, B0_HWE_IMSK, in yge_resume()
1786 for (int i = 0; i < dev->d_num_port; i++) { in yge_resume()
1787 yge_port_t *port = dev->d_port[i]; in yge_resume()
1793 dev->d_suspended = B_FALSE; in yge_resume()
1795 DEV_UNLOCK(dev); in yge_resume()
1798 for (int i = 0; i < dev->d_num_port; i++) { in yge_resume()
1799 yge_port_t *port = dev->d_port[i]; in yge_resume()
1813 yge_dev_t *dev = port->p_dev; in yge_rxeof() local
1819 ASSERT(mutex_owned(&dev->d_rxlock)); in yge_rxeof()
1831 if ((dev->d_hw_id == CHIP_ID_YUKON_FE_P) && in yge_rxeof()
1832 (dev->d_hw_rev == CHIP_REV_YU_FE2_A0)) { in yge_rxeof()
1865 CSR_WRITE_2(dev, in yge_rxeof()
1924 yge_restart_task(yge_dev_t *dev) in yge_restart_task() argument
1928 DEV_LOCK(dev); in yge_restart_task()
1931 for (int i = 0; i < dev->d_num_port; i++) { in yge_restart_task()
1932 port = dev->d_port[i]; in yge_restart_task()
1934 yge_stop_port(dev->d_port[i]); in yge_restart_task()
1936 yge_reset(dev); in yge_restart_task()
1937 for (int i = 0; i < dev->d_num_port; i++) { in yge_restart_task()
1938 port = dev->d_port[i]; in yge_restart_task()
1944 DEV_UNLOCK(dev); in yge_restart_task()
1946 for (int i = 0; i < dev->d_num_port; i++) { in yge_restart_task()
1947 port = dev->d_port[i]; in yge_restart_task()
1958 yge_dev_t *dev = arg; in yge_tick() local
1964 DEV_LOCK(dev); in yge_tick()
1966 if (dev->d_suspended) { in yge_tick()
1967 DEV_UNLOCK(dev); in yge_tick()
1971 for (int i = 0; i < dev->d_num_port; i++) { in yge_tick()
1972 port = dev->d_port[i]; in yge_tick()
1986 idx = CSR_READ_2(dev, ridx); in yge_tick()
2004 DEV_UNLOCK(dev); in yge_tick()
2006 yge_dispatch(dev, YGE_TASK_RESTART); in yge_tick()
2009 for (int i = 0; i < dev->d_num_port; i++) { in yge_tick()
2010 port = dev->d_port[i]; in yge_tick()
2022 yge_dev_t *dev = port->p_dev; in yge_intr_gmac() local
2027 status = CSR_READ_1(dev, MR_ADDR(pnum, GMAC_IRQ_SRC)); in yge_intr_gmac()
2031 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_CLI_RX_FO); in yge_intr_gmac()
2037 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_CLI_TX_FU); in yge_intr_gmac()
2055 yge_dev_t *dev = port->p_dev; in yge_handle_hwerr() local
2060 CSR_WRITE_2(dev, SELECT_RAM_BUFFER(port->p_port, B3_RI_CTRL), in yge_handle_hwerr()
2066 CSR_WRITE_2(dev, SELECT_RAM_BUFFER(port->p_port, B3_RI_CTRL), in yge_handle_hwerr()
2072 CSR_WRITE_4(dev, MR_ADDR(port->p_port, TX_GMF_CTRL_T), in yge_handle_hwerr()
2078 CSR_WRITE_4(dev, Q_ADDR(port->p_rxq, Q_CSR), BMU_CLR_IRQ_PAR); in yge_handle_hwerr()
2083 CSR_WRITE_4(dev, Q_ADDR(port->p_txq, Q_CSR), BMU_CLR_IRQ_TCP); in yge_handle_hwerr()
2088 yge_intr_hwerr(yge_dev_t *dev) in yge_intr_hwerr() argument
2093 status = CSR_READ_4(dev, B0_HWE_ISRC); in yge_intr_hwerr()
2096 CSR_WRITE_1(dev, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); in yge_intr_hwerr()
2105 yge_error(dev, NULL, "PCI Express protocol violation error"); in yge_intr_hwerr()
2112 yge_error(dev, NULL, "Unexpected IRQ Status error"); in yge_intr_hwerr()
2114 yge_error(dev, NULL, "Unexpected IRQ Master error"); in yge_intr_hwerr()
2116 v16 = pci_config_get16(dev->d_pcih, PCI_CONF_STAT); in yge_intr_hwerr()
2117 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON); in yge_intr_hwerr()
2118 pci_config_put16(dev->d_pcih, PCI_CONF_STAT, v16 | in yge_intr_hwerr()
2121 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in yge_intr_hwerr()
2136 v32 = CSR_PCI_READ_4(dev, PEX_UNC_ERR_STAT); in yge_intr_hwerr()
2139 yge_error(dev, NULL, in yge_intr_hwerr()
2147 tlphead[i] = CSR_PCI_READ_4(dev, in yge_intr_hwerr()
2151 dev->d_intrhwemask &= ~Y2_IS_PCI_EXP; in yge_intr_hwerr()
2152 CSR_WRITE_4(dev, B0_HWE_IMSK, in yge_intr_hwerr()
2153 dev->d_intrhwemask); in yge_intr_hwerr()
2154 (void) CSR_READ_4(dev, B0_HWE_IMSK); in yge_intr_hwerr()
2158 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON); in yge_intr_hwerr()
2159 CSR_PCI_WRITE_4(dev, PEX_UNC_ERR_STAT, 0xffffffff); in yge_intr_hwerr()
2160 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in yge_intr_hwerr()
2163 if ((status & Y2_HWE_L1_MASK) != 0 && dev->d_port[YGE_PORT_A] != NULL) in yge_intr_hwerr()
2164 yge_handle_hwerr(dev->d_port[YGE_PORT_A], status); in yge_intr_hwerr()
2165 if ((status & Y2_HWE_L2_MASK) != 0 && dev->d_port[YGE_PORT_B] != NULL) in yge_intr_hwerr()
2166 yge_handle_hwerr(dev->d_port[YGE_PORT_B], status >> 8); in yge_intr_hwerr()
2173 yge_handle_events(yge_dev_t *dev, mblk_t **heads, mblk_t **tails, int *txindex) in yge_handle_events() argument
2184 idx = CSR_READ_2(dev, STAT_PUT_IDX); in yge_handle_events()
2185 if (idx == dev->d_stat_cons) { in yge_handle_events()
2189 ring = &dev->d_status_ring; in yge_handle_events()
2191 for (cons = dev->d_stat_cons; cons != idx; ) { in yge_handle_events()
2196 yge_error(dev, NULL, "Status descriptor error: " in yge_handle_events()
2206 port = dev->d_port[pnum]; in yge_handle_events()
2208 yge_error(dev, NULL, "Invalid port opcode: 0x%08x", in yge_handle_events()
2234 yge_error(dev, NULL, "Unhandled opcode: 0x%08x", in yge_handle_events()
2245 if (rxprogs[pnum] > dev->d_process_limit) { in yge_handle_events()
2250 dev->d_stat_cons = cons; in yge_handle_events()
2251 if (dev->d_stat_cons != CSR_READ_2(dev, STAT_PUT_IDX)) in yge_handle_events()
2261 yge_dev_t *dev; in yge_intr() local
2269 dev = (void *)arg1; in yge_intr()
2276 port1 = dev->d_port[YGE_PORT_A]; in yge_intr()
2277 port2 = dev->d_port[YGE_PORT_B]; in yge_intr()
2279 RX_LOCK(dev); in yge_intr()
2281 if (dev->d_suspended) { in yge_intr()
2282 RX_UNLOCK(dev); in yge_intr()
2287 status = CSR_READ_4(dev, B0_Y2_SP_ISRC2); in yge_intr()
2289 (status & dev->d_intrmask) == 0) { /* Stray interrupt ? */ in yge_intr()
2291 CSR_WRITE_4(dev, B0_Y2_SP_ICR, 2); in yge_intr()
2292 RX_UNLOCK(dev); in yge_intr()
2297 yge_intr_hwerr(dev); in yge_intr()
2310 dev->d_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); in yge_intr()
2311 CSR_WRITE_4(dev, B0_IMSK, dev->d_intrmask); in yge_intr()
2312 (void) CSR_READ_4(dev, B0_IMSK); in yge_intr()
2317 dev->d_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); in yge_intr()
2318 CSR_WRITE_4(dev, B0_IMSK, dev->d_intrmask); in yge_intr()
2319 (void) CSR_READ_4(dev, B0_IMSK); in yge_intr()
2323 while (yge_handle_events(dev, heads, tails, txindex)) in yge_intr()
2328 CSR_WRITE_4(dev, STAT_CTRL, SC_STAT_CLR_IRQ); in yge_intr()
2332 CSR_WRITE_4(dev, B0_Y2_SP_ICR, 2); in yge_intr()
2334 RX_UNLOCK(dev); in yge_intr()
2337 yge_dispatch(dev, dispatch_wrk); in yge_intr()
2378 yge_dev_t *dev = port->p_dev; in yge_set_tx_stfwd() local
2381 switch (dev->d_hw_id) { in yge_set_tx_stfwd()
2383 if (dev->d_hw_rev == CHIP_REV_YU_EX_A0) in yge_set_tx_stfwd()
2387 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), in yge_set_tx_stfwd()
2390 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), in yge_set_tx_stfwd()
2397 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_AE_THR), in yge_set_tx_stfwd()
2400 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), in yge_set_tx_stfwd()
2404 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), in yge_set_tx_stfwd()
2414 yge_dev_t *dev = port->p_dev; in yge_start_port() local
2438 CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_RST_SET); in yge_start_port()
2439 CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_RST_CLR); in yge_start_port()
2440 CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_F_LOOPB_OFF); in yge_start_port()
2441 if (dev->d_hw_id == CHIP_ID_YUKON_EX) in yge_start_port()
2442 CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), in yge_start_port()
2449 GMAC_WRITE_2(dev, pnum, GM_GP_CTRL, 0); in yge_start_port()
2452 (void) CSR_READ_1(dev, MR_ADDR(pnum, GMAC_IRQ_SRC)); in yge_start_port()
2458 GMAC_WRITE_2(dev, pnum, GM_RX_CTRL, GM_RXCR_CRC_DIS); in yge_start_port()
2461 GMAC_WRITE_2(dev, pnum, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); in yge_start_port()
2464 GMAC_WRITE_2(dev, pnum, GM_TX_FLOW_CTRL, 0xffff); in yge_start_port()
2467 GMAC_WRITE_2(dev, pnum, GM_TX_PARAM, in yge_start_port()
2476 GMAC_WRITE_2(dev, pnum, GM_SERIAL_MODE, gmac); in yge_start_port()
2479 GMAC_WRITE_2(dev, pnum, GM_TX_IRQ_MSK, 0); in yge_start_port()
2480 GMAC_WRITE_2(dev, pnum, GM_RX_IRQ_MSK, 0); in yge_start_port()
2481 GMAC_WRITE_2(dev, pnum, GM_TR_IRQ_MSK, 0); in yge_start_port()
2484 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_SET); in yge_start_port()
2485 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_CLR); in yge_start_port()
2487 if (dev->d_hw_id == CHIP_ID_YUKON_FE_P || in yge_start_port()
2488 dev->d_hw_id == CHIP_ID_YUKON_EX) in yge_start_port()
2490 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), reg); in yge_start_port()
2496 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); in yge_start_port()
2504 if ((dev->d_hw_id == CHIP_ID_YUKON_FE_P) && in yge_start_port()
2505 (dev->d_hw_rev == CHIP_REV_YU_FE2_A0)) in yge_start_port()
2508 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_FL_THR), reg); in yge_start_port()
2511 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_SET); in yge_start_port()
2512 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_CLR); in yge_start_port()
2513 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_OPER_ON); in yge_start_port()
2516 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF); in yge_start_port()
2517 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF); in yge_start_port()
2521 if ((dev->d_hw_id == CHIP_ID_YUKON_FE_P) && in yge_start_port()
2522 (dev->d_hw_rev == CHIP_REV_YU_FE2_A0)) { in yge_start_port()
2523 CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_LP_THR), in yge_start_port()
2525 CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_UP_THR), in yge_start_port()
2528 CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_LP_THR), in yge_start_port()
2530 CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_UP_THR), in yge_start_port()
2537 if ((dev->d_hw_id == CHIP_ID_YUKON_FE_P) && in yge_start_port()
2538 (dev->d_hw_rev == CHIP_REV_YU_FE2_A0)) { in yge_start_port()
2540 reg = CSR_READ_4(dev, MR_ADDR(pnum, TX_GMF_EA)); in yge_start_port()
2542 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_EA), reg); in yge_start_port()
2549 CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL), in yge_start_port()
2552 CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL), TXA_ENA_ARB); in yge_start_port()
2558 CSR_WRITE_1(dev, RB_ADDR(port->p_txsq, RB_CTRL), RB_RST_SET); in yge_start_port()
2561 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_CLR_RESET); in yge_start_port()
2562 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_OPER_INIT); in yge_start_port()
2563 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_FIFO_OP_ON); in yge_start_port()
2564 CSR_WRITE_2(dev, Q_ADDR(txq, Q_WM), MSK_BMU_TX_WM); in yge_start_port()
2566 switch (dev->d_hw_id) { in yge_start_port()
2568 if (dev->d_hw_rev == CHIP_REV_YU_EC_U_A0) { in yge_start_port()
2570 CSR_WRITE_2(dev, Q_ADDR(txq, Q_AL), MSK_ECU_TXFF_LEV); in yge_start_port()
2578 if (dev->d_hw_rev == CHIP_REV_YU_EX_B0) in yge_start_port()
2579 CSR_WRITE_4(dev, Q_ADDR(txq, Q_F), F_TX_CHK_AUTO_OFF); in yge_start_port()
2584 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_CLR_RESET); in yge_start_port()
2585 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_OPER_INIT); in yge_start_port()
2586 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_FIFO_OP_ON); in yge_start_port()
2587 if (dev->d_bustype == PEX_BUS) { in yge_start_port()
2588 CSR_WRITE_2(dev, Q_ADDR(rxq, Q_WM), 0x80); in yge_start_port()
2590 CSR_WRITE_2(dev, Q_ADDR(rxq, Q_WM), MSK_BMU_RX_WM); in yge_start_port()
2592 if (dev->d_hw_id == CHIP_ID_YUKON_EC_U && in yge_start_port()
2593 dev->d_hw_rev >= CHIP_REV_YU_EC_U_A1) { in yge_start_port()
2595 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS); in yge_start_port()
2601 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), in yge_start_port()
2607 if (port == dev->d_port[YGE_PORT_A]) { in yge_start_port()
2608 dev->d_intrmask |= Y2_IS_PORT_A; in yge_start_port()
2609 dev->d_intrhwemask |= Y2_HWE_L1_MASK; in yge_start_port()
2610 } else if (port == dev->d_port[YGE_PORT_B]) { in yge_start_port()
2611 dev->d_intrmask |= Y2_IS_PORT_B; in yge_start_port()
2612 dev->d_intrhwemask |= Y2_HWE_L2_MASK; in yge_start_port()
2614 CSR_WRITE_4(dev, B0_HWE_IMSK, dev->d_intrhwemask); in yge_start_port()
2615 (void) CSR_READ_4(dev, B0_HWE_IMSK); in yge_start_port()
2616 CSR_WRITE_4(dev, B0_IMSK, dev->d_intrmask); in yge_start_port()
2617 (void) CSR_READ_4(dev, B0_IMSK); in yge_start_port()
2620 gmac = GMAC_READ_2(dev, pnum, GM_GP_CTRL); in yge_start_port()
2624 (void) GMAC_READ_2(dev, pnum, GM_GP_CTRL); in yge_start_port()
2633 yge_dev_t *dev; in yge_set_rambuffer() local
2639 dev = port->p_dev; in yge_set_rambuffer()
2648 CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_RST_CLR); in yge_set_rambuffer()
2649 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_START), dev->d_rxqstart[pnum] / 8); in yge_set_rambuffer()
2650 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_END), dev->d_rxqend[pnum] / 8); in yge_set_rambuffer()
2651 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_WP), dev->d_rxqstart[pnum] / 8); in yge_set_rambuffer()
2652 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_RP), dev->d_rxqstart[pnum] / 8); in yge_set_rambuffer()
2655 (dev->d_rxqend[pnum] + 1 - dev->d_rxqstart[pnum] - RB_ULPP) / 8; in yge_set_rambuffer()
2657 (dev->d_rxqend[pnum] + 1 - dev->d_rxqstart[pnum] - RB_LLPP_B) / 8; in yge_set_rambuffer()
2659 if (dev->d_rxqsize < MSK_MIN_RXQ_SIZE) in yge_set_rambuffer()
2662 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_RX_UTPP), utpp); in yge_set_rambuffer()
2663 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_RX_LTPP), ltpp); in yge_set_rambuffer()
2666 CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_ENA_OP_MD); in yge_set_rambuffer()
2667 (void) CSR_READ_1(dev, RB_ADDR(rxq, RB_CTRL)); in yge_set_rambuffer()
2670 CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_RST_CLR); in yge_set_rambuffer()
2671 CSR_WRITE_4(dev, RB_ADDR(txq, RB_START), dev->d_txqstart[pnum] / 8); in yge_set_rambuffer()
2672 CSR_WRITE_4(dev, RB_ADDR(txq, RB_END), dev->d_txqend[pnum] / 8); in yge_set_rambuffer()
2673 CSR_WRITE_4(dev, RB_ADDR(txq, RB_WP), dev->d_txqstart[pnum] / 8); in yge_set_rambuffer()
2674 CSR_WRITE_4(dev, RB_ADDR(txq, RB_RP), dev->d_txqstart[pnum] / 8); in yge_set_rambuffer()
2676 CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_ENA_STFWD); in yge_set_rambuffer()
2677 CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_ENA_OP_MD); in yge_set_rambuffer()
2678 (void) CSR_READ_1(dev, RB_ADDR(txq, RB_CTRL)); in yge_set_rambuffer()
2682 yge_set_prefetch(yge_dev_t *dev, int qaddr, yge_ring_t *ring) in yge_set_prefetch() argument
2685 CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), in yge_set_prefetch()
2687 CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), in yge_set_prefetch()
2690 CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), in yge_set_prefetch()
2692 CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), in yge_set_prefetch()
2695 CSR_WRITE_2(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), in yge_set_prefetch()
2698 CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), in yge_set_prefetch()
2701 (void) CSR_READ_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); in yge_set_prefetch()
2707 yge_dev_t *dev = port->p_dev; in yge_stop_port() local
2714 dev = port->p_dev; in yge_stop_port()
2723 dev->d_intrmask &= ~Y2_IS_PORT_A; in yge_stop_port()
2724 dev->d_intrhwemask &= ~Y2_HWE_L1_MASK; in yge_stop_port()
2726 dev->d_intrmask &= ~Y2_IS_PORT_B; in yge_stop_port()
2727 dev->d_intrhwemask &= ~Y2_HWE_L2_MASK; in yge_stop_port()
2729 CSR_WRITE_4(dev, B0_HWE_IMSK, dev->d_intrhwemask); in yge_stop_port()
2730 (void) CSR_READ_4(dev, B0_HWE_IMSK); in yge_stop_port()
2731 CSR_WRITE_4(dev, B0_IMSK, dev->d_intrmask); in yge_stop_port()
2732 (void) CSR_READ_4(dev, B0_IMSK); in yge_stop_port()
2735 val = GMAC_READ_2(dev, pnum, GM_GP_CTRL); in yge_stop_port()
2737 GMAC_WRITE_2(dev, pnum, GM_GP_CTRL, val); in yge_stop_port()
2739 (void) GMAC_READ_2(dev, pnum, GM_GP_CTRL); in yge_stop_port()
2745 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_STOP); in yge_stop_port()
2746 val = CSR_READ_4(dev, Q_ADDR(txq, Q_CSR)); in yge_stop_port()
2749 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_STOP); in yge_stop_port()
2750 val = CSR_READ_4(dev, Q_ADDR(txq, Q_CSR)); in yge_stop_port()
2759 CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_RST_SET | RB_DIS_OP_MD); in yge_stop_port()
2762 CSR_WRITE_1(dev, MR_ADDR(pnum, GMAC_IRQ_MSK), 0); in yge_stop_port()
2765 CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL), TXA_DIS_ARB); in yge_stop_port()
2768 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); in yge_stop_port()
2771 CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(txq, PREF_UNIT_CTRL_REG), in yge_stop_port()
2775 CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_RST_SET); in yge_stop_port()
2778 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_SET); in yge_stop_port()
2780 CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_PAUSE_OFF); in yge_stop_port()
2794 CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); in yge_stop_port()
2796 if (CSR_READ_1(dev, RB_ADDR(rxq, Q_RSL)) == in yge_stop_port()
2797 CSR_READ_1(dev, RB_ADDR(rxq, Q_RL))) in yge_stop_port()
2805 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); in yge_stop_port()
2807 CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(rxq, PREF_UNIT_CTRL_REG), in yge_stop_port()
2810 CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_RST_SET); in yge_stop_port()
2812 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_SET); in yge_stop_port()
2821 GMAC_READ_4(dev, x, y)
2830 yge_dev_t *dev; in yge_stats_clear() local
2835 dev = port->p_dev; in yge_stats_clear()
2838 gmac = GMAC_READ_2(dev, pnum, GM_PHY_ADDR); in yge_stats_clear()
2839 GMAC_WRITE_2(dev, pnum, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); in yge_stats_clear()
2845 GMAC_WRITE_2(dev, pnum, GM_PHY_ADDR, gmac); in yge_stats_clear()
2851 yge_dev_t *dev; in yge_stats_update() local
2856 dev = port->p_dev; in yge_stats_update()
2859 if (dev->d_suspended || !port->p_running) { in yge_stats_update()
2864 gmac = GMAC_READ_2(dev, pnum, GM_PHY_ADDR); in yge_stats_update()
2865 GMAC_WRITE_2(dev, pnum, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); in yge_stats_update()
2913 GMAC_WRITE_2(dev, pnum, GM_PHY_ADDR, gmac); in yge_stats_update()
3088 yge_dev_t *dev = port->p_dev; in yge_m_stop() local
3090 DEV_LOCK(dev); in yge_m_stop()
3091 if (!dev->d_suspended) in yge_m_stop()
3098 DEV_UNLOCK(dev); in yge_m_stop()
3369 yge_dispatch(yge_dev_t *dev, int flag) in yge_dispatch() argument
3371 TASK_LOCK(dev); in yge_dispatch()
3372 dev->d_task_flags |= flag; in yge_dispatch()
3373 TASK_SIGNAL(dev); in yge_dispatch()
3374 TASK_UNLOCK(dev); in yge_dispatch()
3380 yge_dev_t *dev = arg; in yge_task() local
3385 TASK_LOCK(dev); in yge_task()
3386 while ((flags = dev->d_task_flags) == 0) in yge_task()
3387 TASK_WAIT(dev); in yge_task()
3389 dev->d_task_flags = 0; in yge_task()
3390 TASK_UNLOCK(dev); in yge_task()
3402 yge_restart_task(dev); in yge_task()
3407 yge_error(yge_dev_t *dev, yge_port_t *port, char *fmt, ...) in yge_error() argument
3417 if (dev == NULL && port == NULL) { in yge_error()
3423 ppa = ddi_get_instance(dev->d_dip); in yge_error()
3431 yge_dev_t *dev; in yge_ddi_attach() local
3436 dev = kmem_zalloc(sizeof (*dev), KM_SLEEP); in yge_ddi_attach()
3437 dev->d_port[0] = kmem_zalloc(sizeof (yge_port_t), KM_SLEEP); in yge_ddi_attach()
3438 dev->d_port[1] = kmem_zalloc(sizeof (yge_port_t), KM_SLEEP); in yge_ddi_attach()
3439 dev->d_dip = dip; in yge_ddi_attach()
3440 ddi_set_driver_private(dip, dev); in yge_ddi_attach()
3442 dev->d_port[0]->p_port = 0; in yge_ddi_attach()
3443 dev->d_port[0]->p_dev = dev; in yge_ddi_attach()
3444 dev->d_port[1]->p_port = 0; in yge_ddi_attach()
3445 dev->d_port[1]->p_dev = dev; in yge_ddi_attach()
3447 rv = yge_attach(dev); in yge_ddi_attach()
3450 kmem_free(dev->d_port[1], sizeof (yge_port_t)); in yge_ddi_attach()
3451 kmem_free(dev->d_port[0], sizeof (yge_port_t)); in yge_ddi_attach()
3452 kmem_free(dev, sizeof (*dev)); in yge_ddi_attach()
3457 dev = ddi_get_driver_private(dip); in yge_ddi_attach()
3458 ASSERT(dev != NULL); in yge_ddi_attach()
3459 return (yge_resume(dev)); in yge_ddi_attach()
3469 yge_dev_t *dev; in yge_ddi_detach() local
3475 dev = ddi_get_driver_private(dip); in yge_ddi_detach()
3478 for (int i = 0; i < dev->d_num_port; i++) { in yge_ddi_detach()
3480 if (((mh = dev->d_port[i]->p_mh) != NULL) && in yge_ddi_detach()
3491 ASSERT(dip == dev->d_dip); in yge_ddi_detach()
3492 yge_detach(dev); in yge_ddi_detach()
3494 for (int i = 0; i < dev->d_num_port; i++) { in yge_ddi_detach()
3495 if ((mh = dev->d_port[i]->p_mh) != NULL) { in yge_ddi_detach()
3500 kmem_free(dev->d_port[1], sizeof (yge_port_t)); in yge_ddi_detach()
3501 kmem_free(dev->d_port[0], sizeof (yge_port_t)); in yge_ddi_detach()
3502 kmem_free(dev, sizeof (*dev)); in yge_ddi_detach()
3506 dev = ddi_get_driver_private(dip); in yge_ddi_detach()
3507 ASSERT(dev != NULL); in yge_ddi_detach()
3508 return (yge_suspend(dev)); in yge_ddi_detach()
3518 yge_dev_t *dev; in yge_quiesce() local
3520 dev = ddi_get_driver_private(dip); in yge_quiesce()
3521 ASSERT(dev != NULL); in yge_quiesce()
3524 for (int i = 0; i < dev->d_num_port; i++) { in yge_quiesce()
3525 yge_port_t *port = dev->d_port[i]; in yge_quiesce()
3531 CSR_WRITE_4(dev, B0_IMSK, 0); in yge_quiesce()
3532 (void) CSR_READ_4(dev, B0_IMSK); in yge_quiesce()
3533 CSR_WRITE_4(dev, B0_HWE_IMSK, 0); in yge_quiesce()
3534 (void) CSR_READ_4(dev, B0_HWE_IMSK); in yge_quiesce()
3537 CSR_WRITE_2(dev, B0_CTST, CS_RST_SET); in yge_quiesce()