1494     int slots, int qid)  in iwp_alloc_tx_ring()  argument
1505 	ring->qid = qid;  in iwp_alloc_tx_ring()
1523 		    "failed\n", qid));  in iwp_alloc_tx_ring()
1549 		    " failed\n", qid));  in iwp_alloc_tx_ring()
1624 	IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_CONFIG_REG(ring->qid), 0);  in iwp_reset_tx_ring()
1627 		    IWP_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ring->qid)) {  in iwp_reset_tx_ring()
1637 		    ring->qid));  in iwp_reset_tx_ring()
2345 	iwp_tx_ring_t *ring = &sc->sc_txq[desc->hdr.qid & 0x3];  in iwp_tx_intr()
2394 	if ((desc->hdr.qid & 7) != 4) {  in iwp_cmd_intr()
2413 	    desc->hdr.qid, desc->hdr.idx, desc->hdr.flags,  in iwp_cmd_intr()
2619 		    index, sc->sc_rxq.cur, desc->hdr.qid, desc->hdr.idx,  in iwp_rx_softintr()
2625 		if (!(desc->hdr.qid & 0x80) &&  in iwp_rx_softintr()
3098 	cmd->hdr.qid = ring->qid;  in iwp_send()
3252 	    ring->qid, ring->cur, len));  in iwp_send()
3283 	sc->sc_shared->queues_byte_cnt_tbls[ring->qid].  in iwp_send()
3287 		sc->sc_shared->queues_byte_cnt_tbls[ring->qid].  in iwp_send()
3296 	IWP_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->desc_cur);  in iwp_send()
3753 	cmd->hdr.qid = ring->qid;  in iwp_cmd()
3770 	sc->sc_shared->queues_byte_cnt_tbls[ring->qid].  in iwp_cmd()
3773 		sc->sc_shared->queues_byte_cnt_tbls[ring->qid].  in iwp_cmd()
3777 	IWP_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);  in iwp_cmd()
3924 	cmd->hdr.qid = ring->qid;  in iwp_scan()
4067 	sc->sc_shared->queues_byte_cnt_tbls[ring->qid]  in iwp_scan()
4070 		sc->sc_shared->queues_byte_cnt_tbls[ring->qid].  in iwp_scan()
4078 	IWP_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);  in iwp_scan()
5140 	int32_t	qid;  in iwp_init_common()  local
5188 	for (qid = 0; qid < IWP_NUM_QUEUES; qid++) {  in iwp_init_common()
5189 		IWP_WRITE(sc, FH_MEM_CBBC_QUEUE(qid),  in iwp_init_common()
5190 		    sc->sc_txq[qid].dma_desc.cookie.dmac_address >> 8);  in iwp_init_common()
5191 		IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_CONFIG_REG(qid),  in iwp_init_common()