195 	outb(chan_addr[chnl].mask_reg, (chnl & 3) | DMA_SETMSK);  in d37A_dma_disable()
214 	outb(chan_addr[chnl].mask_reg, chnl & 3);  in d37A_dma_enable()
297 		outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM | EISA_CMOK);  in dEISA_setchain()
302 		outb(chan_addr[chnl].scm_reg, chnl);  in dEISA_setchain()
389 			outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM);  in d37A_prog_chan()
472 		outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM);  in d37A_dma_swsetup()
496 	outb(chan_addr[chnl].reqt_reg, DMA_SETMSK | chnl); /* set request bit */  in d37A_dma_swstart()
515 	outb(chan_addr[chnl].reqt_reg, chnl & 3);    /* reset request bit */  in d37A_dma_stop()
607 	outb(chan_addr[chnl].mode_reg, mode);  in d37A_set_mode()
645 	outb(chan_addr[chnl].emode_reg, emode);  in d37A_set_mode()
689 	outb(chan_addr[chnl].ff_reg, 0);	/* set flipflop */  in d37A_write_addr()
692 	outb(chan_addr[chnl].addr_reg, adr_byte[0]);  in d37A_write_addr()
693 	outb(chan_addr[chnl].addr_reg, adr_byte[1]);  in d37A_write_addr()
694 	outb(chan_addr[chnl].page_reg, adr_byte[2]);  in d37A_write_addr()
696 	outb(chan_addr[chnl].hpage_reg, adr_byte[3]);  in d37A_write_addr()
720 	outb(chan_addr[chnl].ff_reg, 0);	/* set flipflop */  in d37A_read_addr()
789 	outb(chan_addr[chnl].ff_reg, 0);	/* set flipflop */  in d37A_write_count()
792 	outb(chan_addr[chnl].cnt_reg, count_byte[0]);  in d37A_write_count()
793 	outb(chan_addr[chnl].cnt_reg, count_byte[1]);  in d37A_write_count()
795 	outb(chan_addr[chnl].hcnt_reg, count_byte[2]);  in d37A_write_count()
819 	outb(chan_addr[chnl].ff_reg, 0);	/* set flipflop */  in d37A_read_count()