1057 	pp->current_phase = ECPP_PHASE_PO;  in ecpp_open()
1122 	    pp->current_mode, pp->current_phase,  in ecpp_open()
1209 	    (pp->current_phase != ECPP_PHASE_ECP_FWD_IDLE)) {  in ecpp_close()
2685 		if (pp->current_phase == ECPP_PHASE_ECP_REV_XFER) {  in ecpp_flush()
2686 			pp->current_phase = ECPP_PHASE_ECP_REV_IDLE;  in ecpp_flush()
2688 			pp->current_phase = ECPP_PHASE_ECP_FWD_IDLE;  in ecpp_flush()
2718 	    pp->current_mode, pp->current_phase, ECR_READ(pp), len);  in ecpp_start()
2783 		ASSERT(pp->current_phase == ECPP_PHASE_ECP_FWD_IDLE ||  in ecpp_start()
2784 		    pp->current_phase == ECPP_PHASE_ECP_REV_IDLE);  in ecpp_start()
2787 		if (pp->current_phase == ECPP_PHASE_ECP_REV_IDLE) {  in ecpp_start()
3229 	    pp->current_mode, pp->current_phase);  in ecpp_isr()
3241 	    pp->current_mode, pp->current_phase);  in ecpp_isr()
3305 	    pp->current_phase == ECPP_PHASE_ECP_REV_XFER) {  in ecpp_dma_ihdlr()
3410 	    pp->current_mode, pp->current_phase);  in ecpp_nErr_ihdlr()
3443 		pp->current_phase = ECPP_PHASE_NIBT_REVINTR;  in ecpp_nErr_ihdlr()
4143 	pp->current_phase = ECPP_PHASE_C_IDLE;  in ecpp_1284_init_interface()
4173 	pp->current_phase = ECPP_PHASE_ECP_SETUP;  in ecp_negotiation()
4187 	pp->current_phase = ECPP_PHASE_ECP_FWD_IDLE;  in ecp_negotiation()
4215 		pp->current_phase = ECPP_PHASE_NIBT_AVAIL;  in nibble_negotiation()
4217 		pp->current_phase = ECPP_PHASE_NIBT_NAVAIL;  in nibble_negotiation()
4225 	    pp->current_phase);  in nibble_negotiation()
4272 	pp->current_phase = ECPP_PHASE_NEGO;  in ecpp_1284_negotiation()
4362 	    pp->current_phase == ECPP_PHASE_C_IDLE) ||  in ecpp_1284_termination()
4392 	pp->current_phase = ECPP_PHASE_TERM;  in ecpp_1284_termination()
4431 	pp->current_phase = ECPP_PHASE_C_IDLE;  in ecpp_1284_termination()
4450 	    pp->current_phase == ECPP_PHASE_ECP_REV_IDLE);  in ecp_peripheral2host()
4491 	pp->current_phase = ECPP_PHASE_ECP_REV_XFER;  in ecp_peripheral2host()
4556 	pp->current_phase = ECPP_PHASE_ECP_REV_IDLE;  in ecp_peripheral2host()
4630 	    pp->current_phase == ECPP_PHASE_ECP_REV_XFER);  in ecpp_ecp_read_completion()
4656 	pp->current_phase = ECPP_PHASE_ECP_REV_IDLE;  in ecpp_ecp_read_completion()
4766 		pp->current_phase = ECPP_PHASE_NIBT_AVAIL;  in ecpp_peripheral2host()
4772 		if ((pp->current_phase == ECPP_PHASE_ECP_FWD_IDLE) &&  in ecpp_peripheral2host()
4836 	    pp->current_phase == ECPP_PHASE_ECP_FWD_IDLE);  in ecp_forward2reverse()
4854 	pp->current_phase = ECPP_PHASE_ECP_REV_IDLE;  in ecp_forward2reverse()
4870 	    pp->current_phase == ECPP_PHASE_ECP_REV_IDLE);  in ecp_reverse2forward()
4895 	pp->current_phase = ECPP_PHASE_ECP_FWD_IDLE;  in ecp_reverse2forward()
4943 	    (pp->current_phase != ECPP_PHASE_ECP_FWD_IDLE)) {  in ecpp_mode_negotiation()
5090 		if (pp->current_phase == ECPP_PHASE_NIBT_NAVAIL &&  in ecpp_idle_phase()
5112 		ASSERT(pp->current_phase == ECPP_PHASE_ECP_FWD_IDLE ||  in ecpp_idle_phase()
5113 		    pp->current_phase == ECPP_PHASE_ECP_REV_IDLE);  in ecpp_idle_phase()
5116 		if ((pp->current_phase == ECPP_PHASE_ECP_REV_IDLE) &&  in ecpp_idle_phase()
5161 	pp->current_phase = (DSR_READ(pp) & (ECPP_nERR | ECPP_PE))  in read_nibble_backchan()
5170 	while (pp->current_phase == ECPP_PHASE_NIBT_AVAIL && rval == SUCCESS) {  in read_nibble_backchan()
5194 		pp->current_phase = (DSR_READ(pp) & (ECPP_nERR | ECPP_PE))  in read_nibble_backchan()
5232 		pp->current_phase = ECPP_PHASE_NIBT_AVAIL;  in devidnib_negotiation()
5234 		pp->current_phase = ECPP_PHASE_NIBT_NAVAIL;  in devidnib_negotiation()
5238 	    pp->current_phase);  in devidnib_negotiation()
5276 		if (pp->current_phase != ECPP_PHASE_NIBT_AVAIL) {  in ecpp_getdevid()
5466 	pp->current_phase = ECPP_PHASE_INIT;  in pc87332_config_chip()
5514 	pp->current_phase = ECPP_PHASE_C_IDLE;  in pc87332_config_chip()
6350 	ekp->ek_phase.value.ui32	= pp->current_phase;  in ecpp_kstat_update()