192 static unsigned long ioaddr;  variable
250     if (pci->ioaddr == 0)  in natsemi_probe()
258     nic->ioaddr = pci->ioaddr & ~3;  in natsemi_probe()
260     ioaddr     = pci->ioaddr & ~3;  in natsemi_probe()
278     prev_eedata = eeprom_read(ioaddr, 6);  in natsemi_probe()
280 	int eedata = eeprom_read(ioaddr, i + 7);  in natsemi_probe()
287            nic->node_addr, ioaddr);  in natsemi_probe()
291     outl(ChipReset, ioaddr + ChipCmd);  in natsemi_probe()
295 	u32 chip_config = inl(ioaddr + ChipConfig);  in natsemi_probe()
304 	   nic_name, (int)inl(ioaddr + 0x84), advertising);  in natsemi_probe()
312     SavedClkRun = inl(ioaddr + ClkRun);  in natsemi_probe()
313     outl(SavedClkRun & ~0x100, ioaddr + ClkRun);  in natsemi_probe()
391 	return inl(ioaddr + 0x80 + (location<<2)) & 0xffff;  in mdio_read()
417     outl(SavedClkRun & ~0x100, ioaddr + ClkRun);  in natsemi_init()
427     if (inl(ioaddr + ChipConfig) & 0x20000000) {	/* Full duplex */  in natsemi_init()
434     outl(tx_config, ioaddr + TxConfig);  in natsemi_init()
435     outl(rx_config, ioaddr + RxConfig);  in natsemi_init()
440     outl(RxOn, ioaddr + ChipCmd);  in natsemi_init()
455     outl(ChipReset, ioaddr + ChipCmd);  in natsemi_reset()
462     if (inl(ioaddr + SiliconRev) == 0x302) {  in natsemi_reset()
463 	outw(0x0001, ioaddr + PGSEL);  in natsemi_reset()
464 	outw(0x189C, ioaddr + PMDCSR);  in natsemi_reset()
465 	outw(0x0000, ioaddr + TSTDAT);  in natsemi_reset()
466 	outw(0x5040, ioaddr + DSPCFG);  in natsemi_reset()
467 	outw(0x008C, ioaddr + SDCFG);  in natsemi_reset()
470     outl(0, ioaddr + IntrMask);  in natsemi_reset()
471     outl(0, ioaddr + IntrEnable);  in natsemi_reset()
489 	outl(i, ioaddr + RxFilterAddr);  in natsemi_init_rxfilter()
490 	outw(nic->node_addr[i] + (nic->node_addr[i+1] << 8), ioaddr + RxFilterData);  in natsemi_init_rxfilter()
512     outl(virt_to_bus(&txd), ioaddr + TxRingPtr);   in natsemi_init_txd()
515                inl(ioaddr + TxRingPtr));  in natsemi_init_txd()
545     outl(virt_to_bus(&rxd[0]), ioaddr + RxRingPtr);  in natsemi_init_rxd()
549                inl(ioaddr + RxRingPtr));  in natsemi_init_rxd()
568     outl(rx_mode, ioaddr + RxFilterAddr);  in natsemi_set_rx_mode()
573     int duplex = inl(ioaddr + ChipConfig) & 0x20000000 ? 1 : 0;  in natsemi_check_duplex()
586     outl(tx_config, ioaddr + TxConfig);  in natsemi_check_duplex()
587     outl(rx_config, ioaddr + RxConfig);  in natsemi_check_duplex()
613     outl(TxOff, ioaddr + ChipCmd);  in natsemi_transmit()
616     outl(virt_to_bus(&txd), ioaddr + TxRingPtr);  in natsemi_transmit()
619                inl(ioaddr + TxRingPtr));  in natsemi_transmit()
642     outl(TxOn, ioaddr + ChipCmd);  in natsemi_transmit()
714     outl(RxOn, ioaddr + ChipCmd);  in natsemi_poll()
736     outl(0, ioaddr + IntrMask);  in natsemi_disable()
737     outl(0, ioaddr + IntrEnable);  in natsemi_disable()
740     outl(RxOff | TxOff, ioaddr + ChipCmd);  in natsemi_disable()
743     outl(SavedClkRun, ioaddr + ClkRun);  in natsemi_disable()