Lines Matching refs:g4
70 ! %g4 queue size mask
75 mov CPU_MONDO_Q_TL, %g4
76 ldxa [%g4]ASI_QUEUE, %g7 ! %g7 = tail ptr
84 ldx [%g2 + MCPU_CPU_Q_SIZE], %g4 ! queue size
85 sub %g4, 1, %g4 ! %g4 = queue size mask
452 rdpr %pil, %g4
453 cmp %g4, PIL_14
455 movl %icc, PIL_14, %g4
464 1: mov CPU_RQ_HD, %g4
465 stxa %g3, [%g4]ASI_QUEUE ! set head equal to tail
476 rdpr %pil, %g4
477 cmp %g4, PIL_14
479 movl %icc, PIL_14, %g4
504 mov CPU_NRQ_HD, %g4
505 ldxa [%g4]ASI_QUEUE, %g2 ! %g2 = Q head offset
506 mov CPU_NRQ_TL, %g4
507 ldxa [%g4]ASI_QUEUE, %g3 ! %g3 = Q tail offset
515 mov CPU_NRQ_HD, %g4
516 ldxa [%g4]ASI_QUEUE, %g2 ! %g2 = Q head offset
517 mov CPU_NRQ_TL, %g4
518 ldxa [%g4]ASI_QUEUE, %g3 ! %g3 = Q tail offset
521 CPU_PADDR(%g1, %g4) ! %g1 = cpu struct paddr
523 2: set CPU_NRQ_BASE_OFF, %g4
524 ldxa [%g1 + %g4]ASI_MEM, %g4 ! %g4 = queue base PA
525 add %g6, %g4, %g4 ! %g4 = PA of ER in Q
527 add %g4, %g7, %g7 ! %g7 = PA of ER in kernel buf
536 ldxa [%g4 + %g5]ASI_MEM, %g1
539 ldxa [%g4 + %g5]ASI_MEM, %g1
542 ldxa [%g4 + %g5]ASI_MEM, %g1
545 ldxa [%g4 + %g5]ASI_MEM, %g1
548 ldxa [%g4 + %g5]ASI_MEM, %g1
551 ldxa [%g4 + %g5]ASI_MEM, %g1
554 ldxa [%g4 + %g5]ASI_MEM, %g1
557 ldxa [%g4 + %g5]ASI_MEM, %g1
574 mov CPU_NRQ_HD, %g4
575 stxa %g6, [%g4]ASI_QUEUE ! update head offset
612 rdpr %tpc, %g4
615 cmp %g4, %g5
619 cmp %g4, %g5
624 rdpr %tt, %g4 ! %g4 = tt[1]
626 and %g4, WTRAP_TTMASK, %g4
627 cmp %g4, WTRAP_TYPE
638 mov 1, %g4
639 sllx %g4, ERRH_U_SPILL_FILL_SHIFT, %g4
640 or %g2, %g4, %g2 ! turn on flag in %g2
645 rdpr %pil, %g4
646 cmp %g4, PIL_14
648 movl %icc, PIL_14, %g4
657 rdpr %pil, %g4
658 cmp %g4, PIL_14
660 movl %icc, PIL_14, %g4