Lines Matching refs:INT64_C
58 #undef INT64_C
60 #define INT64_C(x) (x) macro
79 #define DCU_IC INT64_C(0x0000000000000001) /* icache enable */
80 #define DCU_DC INT64_C(0x0000000000000002) /* dcache enable */
81 #define DCU_IM INT64_C(0x0000000000000004) /* immu enable */
82 #define DCU_DM INT64_C(0x0000000000000008) /* dmmu enable */
83 #define DCU_WIH INT64_C(0x0000000000000010) /* Jaguar only - W$ hash index */
84 #define DCU_VW INT64_C(0x0000000000200000) /* virt watchpoint write enable */
85 #define DCU_VR INT64_C(0x0000000000400000) /* virt watchpoint read enable */
86 #define DCU_PW INT64_C(0x0000000000800000) /* phys watchpoint write enable */
87 #define DCU_PR INT64_C(0x0000000001000000) /* phys watchpoint read enable */
88 #define DCU_VM INT64_C(0x00000001FE000000) /* virtual watchpoint write mask */
89 #define DCU_PM INT64_C(0x000001FE00000000) /* phys watchpoint write mask */
90 #define DCU_WE INT64_C(0x0000020000000000) /* write cache enable */
91 #define DCU_SL INT64_C(0x0000040000000000) /* second load control */
92 #define DCU_SPE INT64_C(0x0000080000000000) /* software prefetch enable */
93 #define DCU_HPE INT64_C(0x0000100000000000) /* hardware prefetch enable */
94 #define DCU_PE INT64_C(0x0000200000000000) /* prefetch enable */
95 #define DCU_RE INT64_C(0x0000400000000000) /* RAW bypass enable */
96 #define DCU_ME INT64_C(0x0000800000000000) /* noncache store merging enable */
97 #define DCU_CV INT64_C(0x0001000000000000) /* virt cacheability when DM=0 */
98 #define DCU_CP INT64_C(0x0002000000000000) /* phys cacheable when DM,IM=0 */
100 #define DCU_IPS_MASK INT64_C(0x0030000000000000)
111 #define SAFARI_CONFIG_ECLK_1 INT64_C(0x0000000000000000) /* 1/1 clock */
113 #define SAFARI_CONFIG_ECLK_2 INT64_C(0x0000000040000000) /* 1/2 clock */
115 #define SAFARI_CONFIG_ECLK_32 INT64_C(0x0000000080000000) /* 1/32 clock */
124 #define JBUS_CONFIG_ECLK_1 INT64_C(0x0000000000000000) /* 1/1 clock */
126 #define JBUS_CONFIG_ECLK_2 INT64_C(0x0000000000002000) /* 1/2 clock */
128 #define JBUS_CONFIG_ECLK_32 INT64_C(0x0000000000004000) /* 1/32 clock */
137 #define JP_MCU_FSM_MASK INT64_C(0x0000000006000000) /* 26..25 */
210 #define C_AFSR_TUE_SH INT64_C(0x4000000000000000) /* uncorrectable tag UE */
211 #define C_AFSR_IMC INT64_C(0x2000000000000000) /* intr vector MTAG ECC */
212 #define C_AFSR_IMU INT64_C(0x1000000000000000) /* intr vector MTAG ECC */
213 #define C_AFSR_DTO INT64_C(0x0800000000000000) /* disrupting TO error */
214 #define C_AFSR_DBERR INT64_C(0x0400000000000000) /* disrupting BERR error */
215 #define C_AFSR_THCE INT64_C(0x0200000000000000) /* h/w correctable E$ tag err */
216 #define C_AFSR_TSCE INT64_C(0x0100000000000000) /* s/w correctable E$ tag err */
217 #define C_AFSR_TUE INT64_C(0x0080000000000000) /* uncorrectable E$ tag error */
218 #define C_AFSR_DUE INT64_C(0x0040000000000000) /* disrupting UE error */
220 #define C_AFSR_ME INT64_C(0x0020000000000000) /* errors > 1, same type!=CE */
221 #define C_AFSR_PRIV INT64_C(0x0010000000000000) /* priv code access error */
222 #define C_AFSR_PERR INT64_C(0x0008000000000000) /* system interface protocol */
223 #define C_AFSR_IERR INT64_C(0x0004000000000000) /* internal system interface */
224 #define C_AFSR_ISAP INT64_C(0x0002000000000000) /* system request parity err */
225 #define C_AFSR_EMC INT64_C(0x0001000000000000) /* mtag with CE error */
226 #define C_AFSR_EMU INT64_C(0x0000800000000000) /* mtag with UE error */
227 #define C_AFSR_IVC INT64_C(0x0000400000000000) /* intr vector with CE error */
228 #define C_AFSR_IVU INT64_C(0x0000200000000000) /* intr vector with UE error */
229 #define C_AFSR_TO INT64_C(0x0000100000000000) /* bus timeout from sys bus */
230 #define C_AFSR_BERR INT64_C(0x0000080000000000) /* bus error from system bus */
231 #define C_AFSR_UCC INT64_C(0x0000040000000000) /* E$ with software CE error */
232 #define C_AFSR_UCU INT64_C(0x0000020000000000) /* E$ with software UE error */
233 #define C_AFSR_CPC INT64_C(0x0000010000000000) /* copyout with CE error */
234 #define C_AFSR_CPU INT64_C(0x0000008000000000) /* copyout with UE error */
235 #define C_AFSR_WDC INT64_C(0x0000004000000000) /* writeback ecache CE error */
236 #define C_AFSR_WDU INT64_C(0x0000002000000000) /* writeback ecache UE error */
237 #define C_AFSR_EDC INT64_C(0x0000001000000000) /* ecache CE ECC error */
238 #define C_AFSR_EDU INT64_C(0x0000000800000000) /* ecache UE ECC error */
239 #define C_AFSR_UE INT64_C(0x0000000400000000) /* uncorrectable ECC error */
240 #define C_AFSR_CE INT64_C(0x0000000200000000) /* correctable ECC error */
241 #define C_AFSR_M_SYND INT64_C(0x00000000000f0000) /* mtag ECC syndrome */
242 #define C_AFSR_E_SYND INT64_C(0x00000000000001ff) /* data ECC syndrome */
265 #define C_AFSR_RED_ERR INT64_C(0x0000000000002000) /* redunancy Efuse error */
266 #define C_AFSR_EFA_PAR_ERR INT64_C(0x0000000000001000) /* Efuse parity error */
267 #define C_AFSR_L3_MECC INT64_C(0x0000000000000800) /* L3 address parity */
268 #define C_AFSR_L3_THCE INT64_C(0x0000000000000400) /* tag CE */
269 #define C_AFSR_L3_TUE_SH INT64_C(0x0000000000000200) /* tag UE from snp/cpy */
270 #define C_AFSR_L3_TUE INT64_C(0x0000000000000100) /* tag UE */
271 #define C_AFSR_L3_EDC INT64_C(0x0000000000000080) /* L3 cache CE */
272 #define C_AFSR_L3_EDU INT64_C(0x0000000000000040) /* L3 cache UE */
273 #define C_AFSR_L3_UCC INT64_C(0x0000000000000020) /* software recover CE */
274 #define C_AFSR_L3_UCU INT64_C(0x0000000000000010) /* software recover UE */
275 #define C_AFSR_L3_CPC INT64_C(0x0000000000000008) /* copyout with CE */
276 #define C_AFSR_L3_CPU INT64_C(0x0000000000000004) /* copyout with UE */
277 #define C_AFSR_L3_WDC INT64_C(0x0000000000000002) /* writeback CE */
278 #define C_AFSR_L3_WDU INT64_C(0x0000000000000001) /* writeback UE */
321 #define C_AFSR_JETO INT64_C(0x0200000000000000) /* JBus Timeout */
322 #define C_AFSR_SCE INT64_C(0x0100000000000000) /* Snoop parity error */
323 #define C_AFSR_JEIC INT64_C(0x0080000000000000) /* JBus Illegal Cmd */
324 #define C_AFSR_JEIT INT64_C(0x0040000000000000) /* Illegal ADTYPE */
325 #define C_AFSR_JEIS INT64_C(0x0008000000000000) /* Illegal Install State */
327 #define C_AFSR_ETU INT64_C(0x0001000000000000) /* L2$ tag CE error */
329 #define C_AFSR_ETP INT64_C(0x0001000000000000) /* L2$ tag parity error */
331 #define C_AFSR_OM INT64_C(0x0000800000000000) /* out of range mem error */
332 #define C_AFSR_UMS INT64_C(0x0000400000000000) /* Unsupported store */
333 #define C_AFSR_IVPE INT64_C(0x0000200000000000) /* intr vector parity err */
334 #define C_AFSR_RUE INT64_C(0x0000000100000000) /* remote mem UE error */
335 #define C_AFSR_RCE INT64_C(0x0000000080000000) /* remote mem CE error */
336 #define C_AFSR_BP INT64_C(0x0000000040000000) /* read data parity err */
337 #define C_AFSR_WBP INT64_C(0x0000000020000000) /* wb/bs data parity err */
338 #define C_AFSR_FRC INT64_C(0x0000000010000000) /* foregin mem CE error */
339 #define C_AFSR_FRU INT64_C(0x0000000008000000) /* foregin mem UE error */
340 #define C_AFSR_JREQ INT64_C(0x0000000007000000) /* Active JBus req at err */
341 #define C_AFSR_ETW INT64_C(0x0000000000c00000) /* AID causing UE/CE */
344 #define C_AFSR_EFES INT64_C(0x0000000000200000) /* E-fuse error summary */
345 #define C_AFSR_ETS INT64_C(0x0000000000100000) /* L2$ tag SRAM stuck-at */
348 #define C_AFSR_B_SYND INT64_C(0x00000000000f0000) /* jbus parity syndrome */
351 #define C_AFSR_ETI INT64_C(0x0000000000008000) /* L2$ tag intermittent */
352 #define C_AFSR_ETC INT64_C(0x0000000000004000) /* L2$ tag CE */
355 #define C_AFSR_AID INT64_C(0x0000000000003e00) /* AID causing UE/CE */
434 #define EN_REG_UCEEN INT64_C(0x0000000000000008) /* enable UCC,UCU */
435 #define EN_REG_ISAPEN INT64_C(0x0000000000000004) /* enable ISAP */
436 #define EN_REG_NCEEN INT64_C(0x0000000000000002) /* UE,EDU,WDU,BERR,IVU,EMU */
437 #define EN_REG_CEEN INT64_C(0x0000000000000001) /* enable CE,EDC,WDC,IVC,EMC */
439 #define EN_REG_DISABLE INT64_C(0x0000000000000000) /* no errors enabled */
450 #define ECCR_ASSOC INT64_C(0x0000000001000000) /* Ecache Assoc. */
463 #define EN_REG_FMT INT64_C(0x0000000000040000) /* force system mtag ECC */
464 #define EN_REG_FMECC INT64_C(0x000000000003C000) /* forced mtag ECC vector */
465 #define EN_REG_FMD INT64_C(0x0000000000002000) /* force system data ECC */
466 #define EN_REG_FDECC INT64_C(0x0000000000001ff0) /* forced data ECC vector */
467 #define EN_REG_UCEEN INT64_C(0x0000000000000008) /* enable UCC,UCU */
468 #define EN_REG_ISAPEN INT64_C(0x0000000000000004) /* enable ISAP */
469 #define EN_REG_NCEEN INT64_C(0x0000000000000002) /* UE,EDU,WDU,BERR,IVU,EMU */
470 #define EN_REG_CEEN INT64_C(0x0000000000000001) /* enable CE,EDC,WDC,IVC,EMC */
471 #define EN_REG_DISABLE INT64_C(0x0000000000000000) /* no errors enabled */
646 #define PN_L2_WAY_LIM INT64_C(0x200000)
662 #define PN_L3_WAY_LIM INT64_C(0x2000000)
873 #define JP_ECACHE_IDX_DISP_FLUSH INT64_C(0x0000000080000000)
930 #define CHP_ECACHE_IDX_TAG_ECC INT64_C(0x0000000000800000)
931 #define CHP_ECACHE_IDX_DISP_FLUSH INT64_C(0x0000000001000000)
932 #define PN_L2_IDX_DISP_FLUSH INT64_C(0x0000000000800000)
933 #define PN_L3_IDX_DISP_FLUSH INT64_C(0x0000000004000000)
954 #define CH_DCTAG_PA_MASK INT64_C(0x000007ffffffe000)
956 #define CH_DCTAG_VALID_BIT INT64_C(0x0000000000000001)
963 #define CH_DCSNTAG_MASK INT64_C(0x000007ffffffe000)
972 #define CHP_DCTAG_PARMASK INT64_C(0x000000007ffffffe)
973 #define CHP_DCSNTAG_PARMASK INT64_C(0x000000007ffffffe)
974 #define CHP_DCTAG_MASK INT64_C(0x000003ffffffe000)
975 #define CHP_DCSNTAG_MASK INT64_C(0x000003ffffffe000)
976 #define CHP_DCWAY_MASK INT64_C(0x0000000000003fe0)
1025 #define CH_ICPATAG_MASK INT64_C(0x000007ffffffe000)
1040 #define CH_ICUTAG_MASK INT64_C(0x00000000001fe000)
1043 #define CH_ICSNTAG_MASK INT64_C(0x000007ffffffe000)
1045 #define CH_ICLOWER_VALID INT64_C(0x0004000000000000)
1046 #define CH_ICUPPER_VALID INT64_C(0x0004000000000000)
1065 #define CHP_ICPATAG_MASK INT64_C(0x000003ffffffe000)
1066 #define CHP_ICSNTAG_MASK INT64_C(0x000003ffffffe000)
1067 #define CHP_ICUTAG_MASK INT64_C(0x00000000001fe000)
1068 #define PN_ICUTAG_MASK INT64_C(0x00000000003fc000)
1069 #define CHP_ICWAY_MASK INT64_C(0x0000000000003fe0)
1073 #define CHP_ICPATAG_PARMASK INT64_C(0x0000003fffffff00)
1074 #define CHP_ICSNTAG_PARMASK INT64_C(0x0000003fffffff00)
1082 #define CH_ICDATA_PRED_ISPCREL INT64_C(0x0000008000000000)
1083 #define CHP_ICDATA_PCREL_PARMASK INT64_C(0x0000039ffffff800)
1084 #define CHP_ICDATA_NPCREL_PARMASK INT64_C(0x000003bfffffffff)
1085 #define PN_ICDATA_PARITY_BIT_MASK INT64_C(0x40000000000)
1239 #define MCU_ACT_STATUS INT64_C(0x0000000000000001)
1240 #define SIU_ACT_STATUS INT64_C(0x0000000000000002)