Lines Matching refs:tmp2
802 #define PCACHE_FLUSHALL(tmp1, tmp2, tmp3) \ argument
804 set MMU_PCONTEXT, tmp2 ;\
805 ldxa [tmp2]ASI_DMMU, tmp3 ;\
806 stxa tmp3, [tmp2]ASI_DMMU ;\
836 #define CH_ICACHE_FLUSHALL(arg1, arg2, tmp1, tmp2) \ argument
837 ldxa [%g0]ASI_DCU, tmp2; \
838 andn tmp2, DCU_IC, tmp1; \
851 stxa tmp2, [%g0]ASI_DCU; \
885 #define ECACHE_FLUSHALL(arg1, arg2, tmp1, tmp2) \ argument
886 CPU_INDEX(tmp1, tmp2); \
887 set JP_ECACHE_IDX_DISP_FLUSH, tmp2; \
889 or tmp1, tmp2, tmp1; \
890 srlx arg1, JP_EC_TO_SET_SIZE_SHIFT, tmp2; \
892 subcc tmp2, arg2, tmp2; \
894 ldxa [tmp1 + tmp2]ASI_EC_DIAG, %g0; \
898 mov 1, tmp2; \
899 sllx tmp2, JP_ECFLUSH_EC_WAY_SHIFT, tmp2; \
900 add tmp1, tmp2, tmp1; \
901 mov (JP_ECACHE_NWAY-1), tmp2; \
902 sllx tmp2, JP_ECFLUSH_EC_WAY_SHIFT, tmp2; \
903 andcc tmp1, tmp2, tmp2; \
905 srlx arg1, JP_EC_TO_SET_SIZE_SHIFT, tmp2