1466 					    memregs->madr[j][0]),  in drmach_mbox_prmsg()
1468 					    memregs->madr[j][1]));  in drmach_mbox_prmsg()
1473 					    memregs->madr[j][2]),  in drmach_mbox_prmsg()
1475 					    memregs->madr[j][3]));  in drmach_mbox_prmsg()
1496 					    memregs->madr[j][0]),  in drmach_mbox_prmsg()
1498 					    memregs->madr[j][1]));  in drmach_mbox_prmsg()
1503 					    memregs->madr[j][2]),  in drmach_mbox_prmsg()
1505 					    memregs->madr[j][3]));  in drmach_mbox_prmsg()
1527 					    memregs->madr[j][0]),  in drmach_mbox_prmsg()
1529 					    memregs->madr[j][1]));  in drmach_mbox_prmsg()
1534 					    memregs->madr[j][2]),  in drmach_mbox_prmsg()
1536 					    memregs->madr[j][3]));  in drmach_mbox_prmsg()
2845 drmach_mem_read_madr(drmach_mem_t *mp, int bank, uint64_t *madr)  in drmach_mem_read_madr()  argument
2851 		*madr = lddmcdecode(DRMACH_MC_ASI_ADDR(mp, bank));  in drmach_mem_read_madr()
2853 		*madr = lddphysio(DRMACH_MC_ADDR(mp, bank));  in drmach_mem_read_madr()
2867 		uint64_t madr, bank_offset;  in drmach_prep_mc_rename()  local
2870 		drmach_mem_read_madr(mp, bank, &madr);  in drmach_prep_mc_rename()
2871 		if (madr & DRMACH_MC_VALID_MASK) {  in drmach_prep_mc_rename()
2874 			bank_offset = (DRMACH_MC_UM_TO_PA(madr) |  in drmach_prep_mc_rename()
2875 			    DRMACH_MC_LM_TO_PA(madr)) - current_basepa;  in drmach_prep_mc_rename()
2879 			madr &= ~DRMACH_MC_UM_MASK;  in drmach_prep_mc_rename()
2880 			madr |= DRMACH_MC_PA_TO_UM(bankpa);  in drmach_prep_mc_rename()
2881 			madr &= ~DRMACH_MC_LM_MASK;  in drmach_prep_mc_rename()
2882 			madr |= DRMACH_MC_PA_TO_LM(bankpa);  in drmach_prep_mc_rename()
2889 			*p++ = madr;  in drmach_prep_mc_rename()
6287 		uint64_t madr;  in drmach_mem_new()  local
6289 		drmach_mem_read_madr(mp, bank, &madr);  in drmach_mem_new()
6290 		if (madr & DRMACH_MC_VALID_MASK) {  in drmach_mem_new()
6497 			uint64_t	madr;  in drmach_mem_get_alignment()  local
6500 			drmach_mem_read_madr(mp, bank, &madr);  in drmach_mem_get_alignment()
6502 			if (!(madr & DRMACH_MC_VALID_MASK))  in drmach_mem_get_alignment()
6505 			uk = DRMACH_MC_UK(madr);  in drmach_mem_get_alignment()
6551 			uint64_t addr, madr;  in drmach_mem_get_base_physaddr()  local
6553 			drmach_mem_read_madr(mp, bank, &madr);  in drmach_mem_get_base_physaddr()
6554 			if (madr & DRMACH_MC_VALID_MASK) {  in drmach_mem_get_base_physaddr()
6555 				addr = DRMACH_MC_UM_TO_PA(madr) |  in drmach_mem_get_base_physaddr()
6556 				    DRMACH_MC_LM_TO_PA(madr);  in drmach_mem_get_base_physaddr()
6588 				uint64_t madr;  in drmach_bus_sync_list_update()  local
6590 				drmach_mem_read_madr(mp, bank, &madr);  in drmach_bus_sync_list_update()
6591 				if (madr & DRMACH_MC_VALID_MASK) {  in drmach_bus_sync_list_update()
6594 					pa  = DRMACH_MC_UM_TO_PA(madr);  in drmach_bus_sync_list_update()
6595 					pa |= DRMACH_MC_LM_TO_PA(madr);  in drmach_bus_sync_list_update()
8763 	uint64_t	madr;  in drmach_msg_memregs_init()  local
8785 				drmach_mem_read_madr(mp, bank, &madr);  in drmach_msg_memregs_init()
8786 				if (madr & DRMACH_MC_VALID_MASK) {  in drmach_msg_memregs_init()
8788 					    exp, mcnum, bank, madr);  in drmach_msg_memregs_init()
8789 					memregs->madr[mcnum][bank].hi =  in drmach_msg_memregs_init()
8790 					    DRMACH_U64_TO_MCREGHI(madr);  in drmach_msg_memregs_init()
8791 					memregs->madr[mcnum][bank].lo =  in drmach_msg_memregs_init()
8792 					    DRMACH_U64_TO_MCREGLO(madr);  in drmach_msg_memregs_init()