86 	uint_t	nrs1, nrs2, nrd;	/* Register number fields. */  in vis_fpu_simulator()  local
97 	nrs2 = pinst.rs2;  in vis_fpu_simulator()
103 		if ((nrs2 & 1) == 1)  in vis_fpu_simulator()
104 			nrs2 = (nrs2 & 0x1e) | 0x20;  in vis_fpu_simulator()
193 		_fp_unpack_extword(pfpsd, &lus2, nrs2);  in vis_fpu_simulator()
199 		_fp_unpack_word(pfpsd, &us2, nrs2);  in vis_fpu_simulator()
205 		_fp_unpack_extword(pfpsd, &lus2, nrs2);  in vis_fpu_simulator()
211 		_fp_unpack_word(pfpsd, &us2, nrs2);  in vis_fpu_simulator()
216 		_fp_unpack_extword(pfpsd, &lus2, nrs2);  in vis_fpu_simulator()
221 		_fp_unpack_word(pfpsd, &us2, nrs2);  in vis_fpu_simulator()
227 		_fp_unpack_extword(pfpsd, &lus2, nrs2);  in vis_fpu_simulator()
233 		_fp_unpack_word(pfpsd, &us2, nrs2);  in vis_fpu_simulator()
249 		_fp_unpack_extword(pfpsd, &lus2, nrs2);  in vis_fpu_simulator()
255 		_fp_unpack_word(pfpsd, &us2, nrs2);  in vis_fpu_simulator()
261 		_fp_unpack_extword(pfpsd, &lus2, nrs2);  in vis_fpu_simulator()
267 		_fp_unpack_word(pfpsd, &us2, nrs2);  in vis_fpu_simulator()
273 		_fp_unpack_extword(pfpsd, &lus2, nrs2);  in vis_fpu_simulator()
279 		_fp_unpack_word(pfpsd, &us2, nrs2);  in vis_fpu_simulator()
285 		_fp_unpack_extword(pfpsd, &lus2, nrs2);  in vis_fpu_simulator()
291 		_fp_unpack_word(pfpsd, &us2, nrs2);  in vis_fpu_simulator()
305 		_fp_unpack_extword(pfpsd, &lus2, nrs2);  in vis_fpu_simulator()
311 		_fp_unpack_word(pfpsd, &us2, nrs2);  in vis_fpu_simulator()
316 		_fp_unpack_extword(pfpsd, &lusr, nrs2);  in vis_fpu_simulator()
320 		_fp_unpack_word(pfpsd, &usr, nrs2);  in vis_fpu_simulator()
325 		_fp_unpack_extword(pfpsd, &lus2, nrs2);  in vis_fpu_simulator()
331 		_fp_unpack_word(pfpsd, &us2, nrs2);  in vis_fpu_simulator()
337 		_fp_unpack_extword(pfpsd, &lus2, nrs2);  in vis_fpu_simulator()
343 		_fp_unpack_word(pfpsd, &us2, nrs2);  in vis_fpu_simulator()
378 	uint_t	nrs1, nrs2, nrd;	/* Register number fields. */  in vis_edge()  local
386 	nrs2 = inst.rs2;  in vis_edge()
392 	ftt = read_iureg(pfpsd, nrs2, pregs, prw, &addrr);  in vis_edge()
555 	uint_t	nrs1, nrs2, nrd;	/* Register number fields. */  in vis_array()  local
562 	nrs2 = inst.rs2;  in vis_array()
568 	ftt = read_iureg(pfpsd, nrs2, pregs, prw, &bsize);  in vis_array()
620 	uint_t	nrs1, nrs2, nrd;	/* Register number fields. */  in vis_alignaddr()  local
626 	nrs2 = inst.rs2;  in vis_alignaddr()
632 	ftt = read_iureg(pfpsd, nrs2, pregs, prw, &tea);  in vis_alignaddr()
667 	uint_t	nrs1, nrs2, nrd;	/* Register number fields. */  in vis_bmask()  local
673 	nrs2 = inst.rs2;  in vis_bmask()
679 	ftt = read_iureg(pfpsd, nrs2, pregs, prw, &tea);  in vis_bmask()
702 	uint_t	nrs1, nrs2, nrd;	/* Register number fields. */  in vis_fpaddsub()  local
715 	nrs2 = inst.rs2;  in vis_fpaddsub()
720 		if ((nrs2 & 1) == 1)  in vis_fpaddsub()
721 			nrs2 = (nrs2 & 0x1e) | 0x20;  in vis_fpaddsub()
728 		_fp_unpack_extword(pfpsd, &lrs2.ll, nrs2);  in vis_fpaddsub()
736 		_fp_unpack_word(pfpsd, &krs2.i, nrs2);  in vis_fpaddsub()
744 		_fp_unpack_extword(pfpsd, &lrs2.ll, nrs2);  in vis_fpaddsub()
752 		_fp_unpack_word(pfpsd, &krs2.i, nrs2);  in vis_fpaddsub()
758 		_fp_unpack_extword(pfpsd, &lrs2.ll, nrs2);  in vis_fpaddsub()
766 		_fp_unpack_word(pfpsd, &krs2.i, nrs2);  in vis_fpaddsub()
774 		_fp_unpack_extword(pfpsd, &lrs2.ll, nrs2);  in vis_fpaddsub()
782 		_fp_unpack_word(pfpsd, &krs2.i, nrs2);  in vis_fpaddsub()
800 	uint_t	nrs1, nrs2, nrd;	/* Register number fields. */  in vis_fcmp()  local
811 	nrs2 = inst.rs2;  in vis_fcmp()
816 	if ((nrs2 & 1) == 1)  in vis_fcmp()
817 		nrs2 = (nrs2 & 0x1e) | 0x20;  in vis_fcmp()
820 	_fp_unpack_extword(pfpsd, &krs2.ll, nrs2);  in vis_fcmp()
907 	uint_t	nrs1, nrs2, nrd;	/* Register number fields. */  in vis_fmul()  local
925 	nrs2 = inst.rs2;  in vis_fmul()
936 		if ((nrs2 & 1) == 1)  in vis_fmul()
937 			nrs2 = (nrs2 & 0x1e) | 0x20;  in vis_fmul()
938 		_fp_unpack_extword(pfpsd, &lrs2.ll, nrs2);  in vis_fmul()
953 		_fp_unpack_word(pfpsd, &krs2.i, nrs2);  in vis_fmul()
968 		_fp_unpack_word(pfpsd, &krs2.i, nrs2);  in vis_fmul()
985 		if ((nrs2 & 1) == 1)  in vis_fmul()
986 			nrs2 = (nrs2 & 0x1e) | 0x20;  in vis_fmul()
987 		_fp_unpack_extword(pfpsd, &lrs2.ll, nrs2);  in vis_fmul()
1008 		if ((nrs2 & 1) == 1)  in vis_fmul()
1009 			nrs2 = (nrs2 & 0x1e) | 0x20;  in vis_fmul()
1010 		_fp_unpack_extword(pfpsd, &lrs2.ll, nrs2);  in vis_fmul()
1025 		_fp_unpack_word(pfpsd, &krs2.i, nrs2);  in vis_fmul()
1038 		_fp_unpack_word(pfpsd, &krs2.i, nrs2);  in vis_fmul()
1059 	uint_t	nrs1, nrs2, nrd;	/* Register number fields. */  in vis_fpixel()  local
1078 	nrs2 = inst.rs2;  in vis_fpixel()
1088 		if ((nrs2 & 1) == 1) 	/* fix register encoding */  in vis_fpixel()
1089 			nrs2 = (nrs2 & 0x1e) | 0x20;  in vis_fpixel()
1090 		_fp_unpack_extword(pfpsd, &lrs2.ll, nrs2);  in vis_fpixel()
1114 		if ((nrs2 & 1) == 1)  in vis_fpixel()
1115 			nrs2 = (nrs2 & 0x1e) | 0x20;  in vis_fpixel()
1116 		_fp_unpack_extword(pfpsd, &lrs2.ll, nrs2);  in vis_fpixel()
1138 		if ((nrs2 & 1) == 1)  in vis_fpixel()
1139 			nrs2 = (nrs2 & 0x1e) | 0x20;  in vis_fpixel()
1140 		_fp_unpack_extword(pfpsd, &lrs2.ll, nrs2);  in vis_fpixel()
1161 		_fp_unpack_word(pfpsd, &krs2.i, nrs2);  in vis_fpixel()
1171 		_fp_unpack_word(pfpsd, &krs2.i, nrs2);  in vis_fpixel()
1193 	uint_t	nrs1, nrs2, nrd;	/* Register number fields. */  in vis_pdist()  local
1202 	nrs2 = pinst.rs2;  in vis_pdist()
1207 	if ((nrs2 & 1) == 1)  in vis_pdist()
1208 		nrs2 = (nrs2 & 0x1e) | 0x20;  in vis_pdist()
1213 	_fp_unpack_extword(pfpsd, &lrs2.ll, nrs2);  in vis_pdist()
1248 	uint_t	nrs1, nrs2, nrd;	/* Register number fields. */  in vis_faligndata()  local
1257 	nrs2 = pinst.rs2;  in vis_faligndata()
1261 	if ((nrs2 & 1) == 1)  in vis_faligndata()
1262 		nrs2 = (nrs2 & 0x1e) | 0x20;  in vis_faligndata()
1267 	_fp_unpack_extword(pfpsd, &lrs2.ll, nrs2);  in vis_faligndata()
1292 	uint_t	nrs1, nrs2, nrd;	/* Register number fields. */  in vis_bshuffle()  local
1302 	nrs2 = pinst.rs2;  in vis_bshuffle()
1306 	if ((nrs2 & 1) == 1)  in vis_bshuffle()
1307 		nrs2 = (nrs2 & 0x1e) | 0x20;  in vis_bshuffle()
1312 	_fp_unpack_extword(pfpsd, &lrs2.ll, nrs2);  in vis_bshuffle()
1354 	uint_t	nrs2;			/* Register number fields. */  in vis_siam()  local
1356 	nrs2 = inst.rs2;  in vis_siam()
1360 	r = nrs2 & 0x7;			/* get mode(3 bit) */  in vis_siam()
1437 	uint_t	nrs1, nrs2, nrd;	/* Register number fields. */  in vis_prtl_fst()  local
1451 	nrs2 = inst.rs2;  in vis_prtl_fst()
1461 		ftt = read_iureg(pfpsd, nrs2, pregs, prw, &tmsk);  in vis_prtl_fst()
1599 	uint_t	nrs1, nrs2, nrd;	/* Register number fields. */  in vis_short_fls()  local
1618 	nrs2 = inst.rs2;  in vis_short_fls()
1628 		ftt = read_iureg(pfpsd, nrs2, pregs, prw, &tea);  in vis_short_fls()
1718 	uint_t	nrs1, nrs2, nrd;	/* Register number fields. */  in vis_blk_fldst()  local
1734 	nrs2 = inst.rs2;  in vis_blk_fldst()
1748 		ftt = read_iureg(pfpsd, nrs2, pregs, prw, &tea);  in vis_blk_fldst()
1866 		uint_t nrs2;  in vis_wrgsr()  local
1868 		nrs2 = pinst.rs2;  in vis_wrgsr()
1869 		ftt = read_iureg(pfpsd, nrs2, pregs, prw, &r2);  in vis_wrgsr()